Top heat dissipation power semiconductor structure and packaging method thereof

Abstract

The invention relates to the technical field of semiconductor packaging, in particular to a top heat dissipation power semiconductor structure and a packaging method thereof. The packaging structure comprises a substrate and pins fixedly connected with the substrate. And a chip is fixed on the chip carrying area on the front surface of the substrate and is adaptively connected with the pins through bonding wires. The periphery of the chip is covered with a plastic package body, and the pins extend out of the plastic package body from the outer edge of the substrate. The packaging structure is characterized in that leading-out terminals which protrude outwards and penetrate through the plastic packaging body are arranged on the periphery of the chip loading area. The whole system adopting the semiconductor structure is small in thermal resistance and good in device heat dissipation effect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a top heat dissipation power semiconductor structure and a packaging method thereof. Background Art

[0002] The current discrete device packaging form of power chips is mostly to solder the chip on a copper substrate and then connect the lead-out electrodes to the pins through bonding wires. For surface mount power devices, such as SiC MOSFET or Si IGBT, the back copper plate is usually connected to the PCB board for reflow soldering assembly. At this time, the thermal conductivity of the plastic sealing layer on the front of the package is extremely poor and heat dissipation cannot be achieved. The PCB board on the back is soldered to the device, and the device can only be cooled by connecting the PCB board to an external heat sink, resulting in a large overall system thermal resistance and poor device heat dissipation effect. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a power semiconductor structure with top heat dissipation and a packaging method thereof. The overall system thermal resistance of the semiconductor structure is small and the device heat dissipation effect is good.

[0004] In order to solve the above problems, the following technical solutions are provided:

[0005] The power semiconductor structure with top heat dissipation of the present invention comprises a substrate and pins fixedly connected to the substrate. A chip is fixed on the carrier area on the front side of the substrate, and the chip is connected to the pins through bonding wires. The chip is covered with a plastic package body, and the pins extend from the outer edge of the substrate to the outside of the plastic package body. It is characterized in that there are lead-out terminals protruding outward and penetrating the plastic package body around the carrier area.

[0006] Wherein, the chip carrier area is provided with a limiting groove for indicating the position of the fixed chip.

[0007] There are three lead-out terminals, and the line connecting the centers of the three terminals forms an isosceles triangle.

[0008] Two of the lead terminals are respectively located on the two pins in a one-to-one correspondence, and the other lead terminal is located on the substrate at a side of the carrier area away from the pins.

[0009] The packaging method of the power semiconductor structure with top heat dissipation is characterized by comprising the following steps:

[0010] The first step is to prepare an overall frame containing multiple substrates arranged side by side by an integrated molding method; wherein, the sides of two adjacent substrates away from the pins are connected by a central rib, the two outer sides of the two outermost substrates have side frames, and the outer ends of the sides of the two outermost substrates away from the pins are connected to the corresponding side frames; a side of the overall frame corresponding to the pins has a horizontal rib running through the overall frame in the longitudinal direction, and the sides of the substrates corresponding to the pins are connected to the horizontal ribs, and the pins are integrally molded with the horizontal ribs.

[0011] The second step is to fix the lead terminals to the substrate and pins.

[0012] The third step is to place the chips on each copper substrate carrier area by welding.

[0013] The fourth step is to complete the electrical connection between the front terminal of the chip and the pin through wire bonding.

[0014] The fourth step is to use single-chip single-head injection molding to form a plastic package on each substrate to wrap the chip and pins.

[0015] The fifth step is to cut the ribs, remove the side frames, center ribs and transverse ribs, and complete the electrical connection separation between the pins to form independent pins.

[0016] The sixth step is to polish the plastic package body and exposed lead terminals to complete the device packaging.

[0017] Wherein, positioning holes are processed on the central rib and the side frame.

[0018] Anti-reflection holes are processed on both side frames, and the number of anti-reflection holes on the two side frames is inconsistent.

[0019] The above solution has the following advantages:

[0020] Because the carrier area of ​​the power semiconductor structure with top heat dissipation of the present invention is surrounded by lead terminals protruding outward and penetrating the plastic package body. The packaging process of the semiconductor structure is: first prepare an overall frame containing multiple substrates arranged side by side; then, set lead terminals at the corresponding positions of each substrate and pin; then, solder the chip to the carrier area and connect the chip and the pin through bonding wires; then, perform plastic sealing, cutting and polishing. This power semiconductor structure contains lead terminals, that is, the device is retained to be suitable for reflow soldering assembly. The lead terminals can be connected to the PCB board by reflow soldering, so that the substrate of the power semiconductor structure is separated from the PCB board, and the substrate is connected to the radiator through an insulating gasket or ceramic sheet with excellent thermal conductivity, which greatly reduces the overall system thermal resistance and achieves a better device heat dissipation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1is a schematic diagram of a top heat dissipation power semiconductor structure of the present invention;

[0022] Figure 2 It is a schematic diagram of a power semiconductor structure with top heat dissipation of the present invention when the plastic package is in a perspective state;

[0023] Figure 3 is a schematic diagram of a single substrate in a top heat dissipation power semiconductor structure of the present invention;

[0024] Figure 4 It is a schematic diagram of the overall frame of the top heat dissipation power semiconductor structure of the present invention during packaging. DETAILED DESCRIPTION

[0025] The present invention is further described below in conjunction with the accompanying drawings.

[0026] like Figure 1 and Figure 2 As shown, the top heat dissipation power semiconductor structure of the present invention includes a substrate 1 and a pin 4 fixedly connected to the substrate 1. A chip 6 is fixed on the carrier area on the front side of the substrate 1, and the chip 6 is adapted to be connected to the pin 4 through a bonding wire 5. The chip 6 is covered with a plastic package 2 on all sides. In this embodiment, a clearance groove 8 is provided on one side of the substrate 1 corresponding to the pin 4, one end of the pin 4 is located in the clearance groove 8, there is a spacing between the pin 4 and the substrate 1, and the pin 4 is fixedly connected to the substrate 1 through the plastic package 2. The pin 4 extends from the outer edge of the substrate 1 to the outside of the plastic package 2. There are lead terminals 3 protruding outward and penetrating the plastic package 2 on all sides of the carrier area.

[0027] like Figure 2 and Figure 3 As shown, in this embodiment, there are two pins 4, which are arranged in parallel and side by side, and lead terminals 3 are arranged on one end of the pin 4 located at the recess 8 and on the substrate 1 on the side of the carrier area away from the pin 4, and the line connecting the centers of the three terminals is an isosceles triangle. The shape of the triangle is stable, so that the power semiconductor structure has high strength after being connected to the PCB.

[0028] The chip carrier area is provided with a limiting groove 7 for indicating the position of the fixed chip 6. In this embodiment, the limiting groove 7 is a V-shaped groove to prevent the chip 6 from being displaced due to the overly smooth surface of the chip 6 package.

[0029] The packaging method of the power semiconductor structure with top heat dissipation comprises the following steps:

[0030] In the first step, an integral frame containing multiple substrates 1 arranged side by side is prepared by an integral molding method. Among them, the side away from the pin 4 between two adjacent substrates 1 is connected by a central rib 13, and the two outer sides of the two outermost substrates 1 have side frames 11, and the outer ends of the sides away from the pin 4 of the two outermost substrates 1 are connected to the corresponding side frames 11. On one side of the integral frame corresponding to the pin 4, there is a horizontal rib 9 running through the longitudinal direction of the integral frame, and the side of the substrate 1 corresponding to the pin 4 is connected to the horizontal rib 9, and the pin 4 is integrally molded with the horizontal rib 9, such as Figure 4 As shown. In this embodiment, the overall frame is a long copper plate processed by stamping, so that the center rib 13, the base plate 1, the side frame 11, the transverse rib 9 and the pin 4 are integrally formed. During stamping, the positioning holes 10 of the center rib 13 and the side frame 11, and the anti-reverse holes 12 on the two side frames 11 are processed at the same time. The frame anti-reverse connection is realized by opening the side holes, and together with the openings of the side and center rib 13, the frame is fixed in the subsequent process.

[0031] In the second step, the whole frame is fixed by the limiting mold, and then the lead terminal 3 is fixed to the substrate 1 and the pin 4 in sequence by welding. The limiting mold is a reverse design of the whole frame. The technicians in this field can obtain the structure of the limiting module through the structure of the whole frame, which belongs to the prior art and will not be repeated here. In the third step, the chip 6 is welded and laid out on the carrier area of ​​each copper substrate 1 in sequence. The welding process of the second and third steps belongs to the prior art and will not be repeated here.

[0032] The fourth step is to electrically connect the front terminal of the chip 6 to the pin 4 by wire bonding. The process of wire bonding is a prior art and will not be described in detail here.

[0033] In the fourth step, a single-chip single-head injection molding method is used to form a plastic package 2 on each substrate 1 to encapsulate the chip 6 and the pins 4. The process of forming the plastic package 2 is a prior art and will not be described in detail here.

[0034] The fifth step is to remove the side frame 11, the middle rib 13 and the transverse rib 9 by cutting the ribs, thereby completing the electrical connection separation between the pins 4 and forming independent pins 4.

[0035] Step 6: Polish the plastic package body 2 and the exposed lead terminals 3 to complete the device packaging.

[0036] When the power semiconductor structure is connected to the PCB board, the connection with the PCB board is completed through the lead-out terminal 3 exposed on the front side, and the copper substrate 1 is left exposed, and the device heat dissipation is achieved through the copper substrate 1 on the back side.

[0037] This solution changes the original planar SMD lead frame structure by leading out the front terminals, and realizes the change of the welding direction of different pins 4 and the external PCB board by leading out the terminals 3 in the three-dimensional direction. By forming a fixed frame with the lead-out terminals 3 and the pins 4, on the one hand, the heat dissipation area of ​​the carrier area is supplemented to improve the heat dissipation capacity of the product. On the other hand, the frame structure formed by the lead-out terminals 3 is used to enhance the fixing effect of the separated pins 4, maintain the consistency of the relative position, and avoid displacement of the pins 4. Moreover, through flexible adjustment of the lead frame, the position of the lead-out terminal 3 can be adjusted according to the layout requirements of the PCB board, or the lead-out terminal 3 can be added according to the internal packaged chip 6 and the circuit structure to adapt to different circuit layouts.

Claims

1. A power semiconductor structure with top heat dissipation, comprising a substrate and pins fixedly connected to the substrate; a chip is fixed on the chip carrier area on the front side of the substrate, and the chip is adaptively connected to the pins through bonding wires; the chip is covered with a plastic package, and the pins extend from the outer edge of the substrate to the outside of the plastic package; characterized in that: The chip carrier area is surrounded by lead terminals that protrude outward and penetrate the plastic package body.

2. The top heat dissipation power semiconductor structure according to claim 1, characterized in that: The chip carrier area is provided with a limiting groove for indicating the position of the fixed chip.

3. The top-heat-dissipating power semiconductor structure according to claim 1, characterized in that: It is characterized in that There are three lead-out terminals, and the line connecting the centers of the three terminals forms an isosceles triangle.

4. The top-heat-dissipating power semiconductor structure according to claim 3, characterized in that: Two of the lead terminals are respectively located on the two pins in a one-to-one correspondence, and the other lead terminal is located on the substrate at a side of the carrier area away from the pins.

5. The packaging method of a power semiconductor structure with top heat dissipation according to claim 1, characterized in that: The steps include: The first step is to prepare an integral frame containing a plurality of substrates arranged side by side by an integral molding method; wherein the sides of two adjacent substrates away from the pins are connected by a central rib, the two outer sides of the two outermost substrates are provided with side frames, and the outer ends of the sides of the two outermost substrates away from the pins are connected to the corresponding side frames; a side of the integral frame corresponding to the pins is provided with a transverse rib running through the longitudinal direction of the integral frame, and the sides of the substrates corresponding to the pins are connected to the transverse ribs, and the pins are integrally molded with the transverse ribs; The second step is to fix the lead terminals to the substrate and pins; The third step is to place the chips on each copper substrate carrier area by welding in turn; The fourth step is to complete the electrical connection between the front terminal of the chip and the pin through wire bonding; The fourth step is to form a plastic package on each substrate by single-head injection molding to wrap the chip and pins; The fifth step is to remove the side frames, middle ribs and transverse ribs by cutting the ribs, and complete the electrical connection separation between the pins to form independent pins; The sixth step is to polish the plastic package body and exposed lead terminals to complete the device packaging.

6. The packaging method of a power semiconductor structure with top heat dissipation according to claim 5, characterized in that: Positioning holes are processed on the center rib and the side frame.

7. The packaging method of a power semiconductor structure with top heat dissipation according to claim 5, characterized in that: Anti-reflection holes are processed on both side frames, and the number of anti-reflection holes on the two side frames is inconsistent.

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