Semiconductor device, manufacturing method thereof and electronic device

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and an electronic device, and the method comprises the steps: providing a first semiconductor substrate which comprises a first surface and a second surface which are opposite to each other; etching the first surface of the first semiconductor substrate so as to form a deep groove on the first surface; forming a first filling layer in the deep groove; annealing the first semiconductor substrate to repair lattice damage of the first semiconductor substrate; ion implantation is carried out on the first surface of the first semiconductor substrate to form pixel units, and the deep grooves are located between the adjacent pixel units. According to the method, etching of the deep groove is completed before ion implantation is executed, then lattice damage of the semiconductor substrate is repaired through high-temperature annealing, and white pixels and dark currents caused by lattice damage can be restrained on the premise that electrical drifting of a semiconductor device does not occur.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] In CIS (CMOS image sensor), there are hundreds of millions of PDs (Photodiodes, photoelectric conversion area). When PDs are illuminated, electronic transitions will occur, converting optical signals into electrical signals. Image sensors are mainly divided into two structures: FSI (Front side illumination CMOS imager sensor, front-illuminated image sensor) and BSI (Backside illumination CMOS image sensor, back-illuminated image sensor). BSI arranges the photosensitive area containing PDs on the top of the circuit to reduce light loss, such as metal wire reflection, dielectric layer absorption, etc., so that the photoelectric conversion effect is significantly increased and the image quality is significantly improved. BDTI (Backside deep trench isolation, backside deep trench isolation) is an important structure in BSI, especially in small-size and large-pixel products. It can be used as both electrical isolation and optical isolation to prevent electrons or photons in the PD area from migrating to adjacent PD areas to cause electrical / optical crosstalk and reduce image quality.

[0003] In the BSI process, although the BDTI process can form a good electrical / optical isolation structure, the etching process to form the BDTI groove will cause damage to the device surface, and the damage cannot be repaired by long-term high-temperature annealing in the BSI process, otherwise it will cause the device electrical drift. Therefore, the damage caused by etching is one of the important sources of white pixels and dark current in the BDTI process. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: Providing a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other; Etching the first surface of the first semiconductor substrate to form deep trenches on the first surface; Annealing the first semiconductor substrate to repair lattice damage of the first semiconductor substrate; forming a first filling layer in the deep trench; Ion implantation is performed on the first surface of the first semiconductor substrate to form pixel units, and the deep trenches are located between adjacent pixel units.

[0006] In one embodiment, after forming the pixel unit, the method further includes: forming an interlayer dielectric layer on the first surface of the first semiconductor substrate, wherein an interconnect structure is formed in the interlayer dielectric layer; Providing a second semiconductor substrate, and bonding the interlayer dielectric layer to the second semiconductor substrate; Thinning the second surface of the first semiconductor substrate to expose the bottom of the deep trench; removing the first filling layer filled in the deep trench; A second filling layer is formed in the deep trench.

[0007] In one embodiment, etching the first surface of the first semiconductor substrate to form a deep trench on the first surface includes: forming a patterned first hard mask layer on the first surface of the first semiconductor substrate; Using the patterned first hard mask layer as a mask, etching the first surface of the first semiconductor substrate to form the deep trench; The first hard mask layer is removed.

[0008] In one embodiment, after forming the first filling layer in the deep trench and before performing ion implantation on the first semiconductor substrate, the method further includes: forming a patterned second hard mask layer on the first surface of the first semiconductor substrate; Using the patterned second hard mask layer as a mask, etching the first semiconductor substrate to form a shallow trench; Filling a third filling layer in the shallow trench to form a shallow trench isolation structure; The second hard mask layer is removed.

[0009] In one embodiment, before etching the first surface of the first semiconductor substrate to form the deep trench, the method further includes: forming a buffer layer on the first surface of the first semiconductor substrate; Sequentially etching the buffer layer and the first semiconductor substrate to form an alignment mark; The buffer layer is removed.

[0010] In one embodiment, the annealing temperature is not less than 750° C., and the annealing time is not less than 30 minutes.

[0011] In one embodiment, the material of the first filling layer includes silicon nitride and / or silicon oxide.

[0012] In one embodiment, the process of removing the first filling layer includes a wet etching process.

[0013] In one embodiment, the material of the second filling layer includes at least one of the following: silicon oxide, a high-K dielectric layer, and a metal.

[0014] A second aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the method described above.

[0015] A third aspect of an embodiment of the present invention provides an electronic device, which includes the semiconductor device described above.

[0016] According to the method for manufacturing a semiconductor device provided by the present invention, deep trench etching is completed before ion implantation, and then high-temperature annealing is performed to repair lattice damage of the semiconductor substrate, thereby suppressing white pixels and dark current caused by lattice damage without causing the electrical properties of the device to drift. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings:

[0018] Figure 1 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention; FIG. 2A to FIG. 2N The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0019] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0020] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0021] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0022] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0023] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0024] In the manufacturing process of BDTI, silicon dry etching is used to etch deeper grooves to isolate the crosstalk caused by electron diffusion / drift between pixel arrays in the semiconductor substrate to adjacent pixels. However, the groove etching process will cause damage to the BDTI surface, and the damage cannot be repaired by processes such as high-temperature annealing, resulting in interface states on the BDTI surface, which is prone to dangling bonds, and is one of the important sources of adverse factors such as white pixels and dark current.

[0025] In order to avoid etching damage during the formation of deep trenches, a process flow is as follows: after depositing an interlayer dielectric layer (ILD) on the surface of the semiconductor substrate, a photoresist layer is formed on the interlayer dielectric layer, and the interlayer dielectric layer is etched using the photoresist layer as a mask to form an opening for the deep trench, and the semiconductor substrate is etched using the interlayer dielectric layer with the opening as a hard mask layer, thereby forming a deep trench in the semiconductor substrate. After etching, annealing is performed at 750℃~1000℃ to repair lattice damage, and then the dielectric layer is filled in the deep trench. However, when annealing is performed after etching to repair lattice damage, the optoelectronic device has already been formed, and excessively high temperatures will cause the injected ions to diffuse, causing the electrical properties of the device to drift.

[0026] Therefore, in view of the existence of the above-mentioned technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, it mainly includes the following steps: In step S101, a first semiconductor substrate is provided, wherein the first semiconductor substrate comprises a first surface and a second surface opposite to each other; In step S102, the first surface of the first semiconductor substrate is etched to form deep trenches on the first surface; In step S103, annealing is performed on the first semiconductor substrate to repair lattice damage of the first semiconductor substrate; In step S104, a first filling layer is formed in the deep trench; In step S105 , ion implantation is performed on the first surface of the first semiconductor substrate to form pixel units, and the deep trenches are located between adjacent pixel units.

[0027] The method for manufacturing a semiconductor device provided by an embodiment of the present invention completes deep trench etching before ion implantation, and then performs high-temperature and long-term annealing. This repairs the lattice damage of the first semiconductor substrate and suppresses white pixels and dark currents caused by the lattice damage without causing the electrical properties of the device to drift.

[0028] Embodiment 1 Below, reference FIG. 2A to FIG. 2N A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: FIG. 2A to FIG. 2N The cross-sectional view of a semiconductor device obtained by sequentially performing various steps in a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0029] First, if Figure 2A As shown, a first semiconductor substrate 200 is provided, and the first semiconductor substrate 200 includes a first surface and a second surface opposite to each other. The first semiconductor substrate 200 can be used as a pixel wafer to form a pixel array to receive incident light and convert it into an electrical signal. The material of the first semiconductor substrate 200 includes but is not limited to at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI). As an example, in this embodiment, the first semiconductor substrate 200 is made of single crystal silicon material.

[0030] Exemplarily, a buffer layer 201 may be formed on the first surface of the first semiconductor substrate 200; Figure 2B As shown, a first photoresist layer 202 is formed on the buffer layer 201, and the buffer layer 201 and the first semiconductor substrate 200 are sequentially etched using the first photoresist layer 202 as a mask to form an alignment mark 203. Figure 2C As shown, the buffer layer is removed. Exemplarily, the material of the buffer layer 201 includes silicon oxide, and the buffer layer 201 can be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method. The buffer layer 201 can isolate the first photoresist layer 202 from the first semiconductor substrate 200, preventing the first photoresist layer 202 from directly contacting the first semiconductor substrate 200 and causing contamination.

[0031] Next, the first surface of the first semiconductor substrate 200 is etched to form deep trenches on the first surface. Figure 2D As shown, a first hard mask layer 204 is formed on the first surface of the first semiconductor substrate 200. The first hard mask layer 204 may include a silicon oxide layer and a silicon nitride layer formed in sequence, and may also include other hard mask material layers such as amorphous carbon.

[0032] Then, if Figure 2E As shown, a patterned second photoresist layer 205 is formed on the first hard mask layer 204; then Figure 2F As shown, the first hard mask layer 204 is etched with the patterned second photoresist layer 205 as a mask to obtain a patterned first hard mask layer 204, and the first surface of the first semiconductor substrate 200 is etched with the patterned first hard mask layer 204 as a mask to form a deep trench 206; finally, the first hard mask layer 204 is removed. The depth of the deep trench 206 can be adjusted according to the requirement of the remaining thickness of the first semiconductor substrate 200 after thinning.

[0033] Exemplarily, the lithography machine for etching to form deep grooves can use an ArF light source or a KrF light source. When the pixel size is small enough, the width of the corresponding deep groove structure also needs to be small and precise enough, and an ArF lithography process is usually required; when the deep groove reaches a certain depth, the thickness of the photoresist of the ArF lithography process may not be able to bear the etching loss. The embodiment of the present invention uses a furnace tube machine in the front-end process to prepare high-quality silicon oxide and silicon nitride as a hard mask layer, which can make up for the disadvantage of insufficient photoresist. Optionally, the first semiconductor substrate 200 can also be directly etched using the second photoresist layer 205 as a mask to form a deep groove 206, that is, deep trench etching is performed using a photoresist mode rather than a hard mask mode.

[0034] After etching is completed, the first semiconductor substrate 200 is annealed to repair the lattice damage caused to the first semiconductor substrate 200 during the process of etching to form the deep trench 206. Exemplarily, the annealing temperature is not less than 750°C, and the annealing time is more than 30 minutes. Since ion implantation has not been performed at this time, there is no need to consider the device electrical drift, and a long high-temperature annealing can be performed to repair the lattice damage. Therefore, further, the annealing temperature can be not less than 1000°C, and the annealing time can be not less than 2 hours.

[0035] Then, if Figure 2GAs shown, a first filling layer 207 is formed in the deep trench 206. Among them, a material with a large etching selectivity ratio with the first semiconductor substrate can be selected as the first filling layer 207 to facilitate subsequent removal. For example, silicon nitride or silicon oxide can be selected as the first filling layer 207, and after the silicon nitride or silicon oxide material is deposited by a plasma enhanced chemical vapor deposition (PECVD) process, the filling material on the surface of the first semiconductor substrate 200 can be removed by a chemical mechanical polishing process, and the filling material filled in the deep trench 206 is retained as the first filling layer 207.

[0036] For example, after forming the first filling layer 207, a shallow trench isolation structure may be formed on the first surface of the first semiconductor substrate 200. Figure 2H As shown, a second hard mask layer 208 is formed on the first surface of the first semiconductor substrate 200 , and the second hard mask layer 208 includes but is not limited to a silicon oxide layer and a silicon nitride layer formed in sequence, and may also include other hard mask material layers such as amorphous carbon.

[0037] Next, a photoresist layer is formed on the second hard mask layer 208, and the second hard mask layer 208 is etched using the photoresist layer as a mask to form a patterned second hard mask layer, and Fig.2I As shown, the first semiconductor substrate 200 is etched using the patterned second hard mask layer 208 as a mask to form a shallow trench 209, wherein the depth of the shallow trench 209 is less than the depth of the deep trench 206. Figure 2J As shown, a third filling layer 210 is filled in the shallow trench 209 to form a shallow trench isolation structure. Finally, the second hard mask layer 208 is removed. A filling material may be deposited in the shallow trench 209 and on the second hard mask layer 208, and the second hard mask layer 208 and the filling material thereon are removed by a chemical mechanical polishing process.

[0038] Next, ion implantation is performed on the first surface of the first semiconductor substrate 200 to form pixel units, and deep trenches 206 are located between adjacent pixel units to prevent crosstalk between adjacent pixel units. In the embodiment of the present invention, ion implantation is performed after deep trench etching and annealing to prevent electrical drift caused by high temperature annealing.

[0039] After forming the pixel unit, as Figure 2K As shown, an interlayer dielectric layer 211 is formed on the first surface of the first semiconductor substrate 200, and an interconnection structure 212 is formed in the interlayer dielectric layer 211. The interlayer dielectric layer 211 can be a silicon oxide layer or other dielectric material layer, and the interlayer dielectric layer 211 can be formed by chemical vapor deposition and physical vapor deposition. A metal layer is formed in the interlayer dielectric layer 211 as an interconnection structure 212, and the interconnection structure 212 is used to lead out the electrical signal generated by the pixel unit.

[0040] Then, if Figure 2L As shown, a second semiconductor substrate 213 is provided, and the interlayer dielectric layer 211 is bonded to the second semiconductor substrate 213. The second semiconductor substrate 213 can be used as a logic wafer, which includes electrical devices for processing electrical signals from the pixel array. The second semiconductor substrate 213 can also carry the first semiconductor substrate 200 during the thinning process. The electrical devices in the second semiconductor substrate 213 are electrically connected to the interconnection structure 212 in the interlayer dielectric layer 211.

[0041] Next, continue to refer to Figure 2L , the second surface of the first semiconductor substrate 200 is thinned to expose the bottom of the deep trench 206, that is, to expose the first filling layer 207 filled in the deep trench 206. Figure 2M As shown, the first filling layer 207 filled in the deep trench 206 can be removed by an etching process. Since the material of the first filling layer 207 has a high etching selectivity with the first semiconductor substrate 200, it is beneficial to remove the first filling layer 207 without damaging the first filling layer. Exemplarily, a wet etching process can be used to remove the first filling layer.

[0042] Then, if Figure 2N As shown, a second filling layer 214 is formed in the deep trench 206. The material of the second filling layer 214 includes at least one of the following: silicon oxide, a high-K dielectric layer, and a metal. Exemplarily, the material of the second filling layer 214 includes at least a high-K dielectric layer, wherein the material of the high-K dielectric layer includes Al 2 O 3 , HfO 2 、 2 O 5 、ZrO 2 and TiO 2 At least one of the above. The high-K dielectric layer may be formed by atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, and other processes, and the high-K dielectric layer and other filling materials formed on the second surface of the semiconductor substrate 200 may be removed by a chemical mechanical polishing process. Since the annealing process has been completed before the high-K dielectric layer is formed, the high temperature of the annealing process will not affect the quality of the high-K dielectric layer, and crosstalk between adjacent pixel units can be effectively prevented.

[0043] At this point, the process steps implemented in the manufacturing method of a semiconductor device according to an embodiment of the present invention have been completed. It can be understood that the semiconductor device manufacturing method of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0044] According to the method for manufacturing a semiconductor device provided by the present invention, by completing deep trench etching before ion implantation and then performing high-temperature long-term annealing, the lattice damage of the first semiconductor substrate is repaired and white pixels and dark currents caused by the lattice damage are suppressed without causing the electrical properties of the device to drift.

[0045] Embodiment 2 The present invention also provides a semiconductor device, which can be prepared by the method in the above-mentioned embodiment 1.

[0046] Below, reference Figure 2N The semiconductor device of the present invention is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment 1. For specific explanations and descriptions, reference can be made to the description in embodiment 1.

[0047] Specifically, Figure 2N As shown, the semiconductor device of the embodiment of the present invention includes a first semiconductor substrate 200, the first semiconductor substrate 200 includes a first surface and a second surface relative to each other, pixel units are formed on the first surface, a deep trench isolation structure is formed between adjacent pixel units, the deep trench isolation structure runs through the first surface and the second surface, and the deep trench isolation structure includes a second filling layer 214 filled in the deep trench; an interlayer dielectric layer 211 and an interconnection structure formed in the interlayer dielectric layer 211 are formed on the first surface of the semiconductor substrate 200, and the other side of the interlayer dielectric layer 211 is bonded to the second semiconductor substrate 213.

[0048] Since the semiconductor device in the embodiment of the present invention is manufactured by the method in the first embodiment, white pixels and dark current can be effectively avoided.

[0049] Embodiment 3 Another embodiment of the present invention provides an electronic device, comprising the aforementioned semiconductor device, wherein the semiconductor device is manufactured according to the aforementioned method.

[0050] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including a circuit. The electronic device of the embodiment of the present invention has better performance because the above-mentioned semiconductor device is used.

[0051] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a first semiconductor substrate, the first semiconductor substrate comprising a first surface and a second surface opposite to each other; Etching the first surface of the first semiconductor substrate to form deep trenches on the first surface; Annealing the first semiconductor substrate to repair lattice damage of the first semiconductor substrate; forming a first filling layer in the deep trench; Ion implantation is performed on the first surface of the first semiconductor substrate to form pixel units, and the deep trenches are located between adjacent pixel units.

2. The manufacturing method according to claim 1, characterized in that After forming the pixel unit, the method further includes: forming an interlayer dielectric layer on the first surface of the first semiconductor substrate, wherein an interconnect structure is formed in the interlayer dielectric layer; Providing a second semiconductor substrate, and bonding the interlayer dielectric layer to the second semiconductor substrate; Thinning the second surface of the first semiconductor substrate to expose the bottom of the deep trench; removing the first filling layer filled in the deep trench; A second filling layer is formed in the deep trench.

3. The manufacturing method according to claim 1, characterized in that: The etching the first surface of the first semiconductor substrate to form a deep trench on the first surface includes: forming a patterned first hard mask layer on the first surface of the first semiconductor substrate; Using the patterned first hard mask layer as a mask, etching the first surface of the first semiconductor substrate to form the deep trench; The first hard mask layer is removed.

4. The manufacturing method according to claim 1, characterized in that: After forming the first filling layer in the deep trench and before performing ion implantation on the first semiconductor substrate, the method further includes: forming a patterned second hard mask layer on the first surface of the first semiconductor substrate; Using the patterned second hard mask layer as a mask, etching the first semiconductor substrate to form a shallow trench; Filling a third filling layer in the shallow trench to form a shallow trench isolation structure; The second hard mask layer is removed.

5. The manufacturing method according to claim 1, characterized in that: Before etching the first surface of the first semiconductor substrate to form the deep trench, the method further includes: forming a buffer layer on the first surface of the first semiconductor substrate; Sequentially etching the buffer layer and the first semiconductor substrate to form an alignment mark; The buffer layer is removed.

6. The manufacturing method according to claim 1, characterized in that: The annealing temperature is not less than 750° C., and the annealing time is not less than 30 minutes.

7. The manufacturing method according to claim 1, characterized in that: The material of the first filling layer includes silicon nitride and / or silicon oxide.

8. The manufacturing method according to claim 1, characterized in that: The process of removing the first filling layer includes a wet etching process.

9. The manufacturing method according to claim 2, characterized in that: The material of the second filling layer includes at least one of the following: silicon oxide, a high-K dielectric layer, and metal.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to claim 10.

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