Semiconductor memory device

Abstract

The invention provides a semiconductor memory device which can operate well. The device includes a semiconductor substrate and a plurality of transistors. A first transistor among the plurality of transistors includes: a first gate insulating film provided on the semiconductor substrate; a first gate electrode provided on the first gate insulating film; side wall insulating films provided on both side surfaces of the first gate electrode; a first region included in the semiconductor substrate and overlapping the first gate electrode when viewed from a first direction intersecting a surface of the semiconductor substrate; a first diffusion layer which is included in the semiconductor substrate, is connected to the first contact electrode extending in the first direction, and contains an impurity of the first conductivity type; a second diffusion layer that is included in the semiconductor substrate, is provided between the first region and the first diffusion layer, and contains an impurity of the first conductivity type; and a third diffusion layer which is included in the semiconductor substrate, is provided between the second diffusion layer and the first diffusion layer, is connected to the second diffusion layer, and contains impurities of the first conductivity type at a concentration lower than that of the second diffusion layer.

Description

[0001] [Related applications]

[0002] This application claims the priority of Japanese Patent Application No. 2023-100347 (filing date: June 19, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device including a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate is known. Summary of the invention

[0005] Provided is a semiconductor memory device that operates preferably.

[0006] A semiconductor memory device according to one embodiment includes a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate. A first transistor among the plurality of transistors includes: a first gate insulating film provided on the semiconductor substrate; a first gate electrode provided on the first gate insulating film; a sidewall insulating film provided on both sides of the first gate electrode; a first region included in the semiconductor substrate and overlapping with the first gate electrode when viewed from a first direction intersecting the surface of the semiconductor substrate; a first diffusion layer included in the semiconductor substrate, connected to a first contact electrode extending in the first direction, and containing impurities of the first conductivity type; a second diffusion layer included in the semiconductor substrate, provided between the first region and the first diffusion layer, and containing impurities of the first conductivity type; and a third diffusion layer included in the semiconductor substrate, provided between the second diffusion layer and the first diffusion layer, connected to the second diffusion layer, and containing impurities of the first conductivity type. The concentration of the second diffusion layer is higher than that of the third diffusion layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic block diagram showing the structure of the memory die MD.

[0008] Figure 2 It is a schematic circuit diagram showing a partial structure of the memory chip MD.

[0009] Figure 3 It is a schematic circuit diagram showing a partial structure of the memory chip MD.

[0010] Figure 4 This is a schematic exploded perspective view showing a configuration example of the semiconductor memory device according to the first embodiment.

[0011] Figure 5 It means chip C MA schematic bottom view of an example of the structure of .

[0012] Figure 6 It is a schematic cross-sectional view showing a partial structure of the memory die MD.

[0013] Figure 7 It is a schematic cross-sectional view showing a partial structure of the memory die MD.

[0014] Figure 8 It means chip C M A schematic bottom view of a portion of FIG.

[0015] Fig. 9 It means chip C M A schematic cross-sectional view of a portion of .

[0016] Fig.10 This is a schematic cross-sectional view showing a partial structure of the semiconductor memory device according to the first embodiment.

[0017] Fig.11 The N-type high voltage transistor Tr of the first embodiment is shown. NH Schematic top view of the structure.

[0018] Fig.12 The N-type high voltage transistor Tr of the first embodiment is shown. NH A schematic cross-sectional view of the structure.

[0019] Fig.13 The N-type high voltage transistor Tr is used to explain the first embodiment. NH Figure 2 shows the impurity concentration of .

[0020] Fig.14 The N-type high voltage transistor Tr of the first embodiment is shown. NH A cross-sectional view of a portion of the structure.

[0021] Fig.15 It is conceptually expressed Fig.11 A graph of the impurity concentration in the region shown along the AA' dashed line.

[0022] Fig.16 Yes means Fig.10 The P-type high voltage transistor Tr shown PH A schematic cross-sectional view of the structure.

[0023] Fig.17 Yes means Fig.10 The N-type low voltage transistor Tr shown NL A schematic cross-sectional view of the structure.

[0024] Fig.18 Yes means Fig.10 The P-type low voltage transistor Tr shown PL A schematic cross-sectional view of the structure.

[0025] Fig.19 An N-type high voltage transistor Tr is shown as a modified example of the first embodiment. NHA A schematic cross-sectional view of the structure.

[0026] Fig. 20 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0027] Fig.21 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0028] Fig. 22 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0029] Fig.23 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0030] Fig.24 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0031] Fig.25 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0032] Fig.26 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0033] Fig. 27 The N-type high voltage transistor Tr of the first embodiment is used NH Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0034] Fig.28 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0035] Fig.29The N-type high voltage transistor Tr of the first embodiment is used NH A schematic top view for explaining the manufacturing method.

[0036] Fig.30 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0037] Fig.31 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic top view for explaining the manufacturing method.

[0038] Fig.32 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0039] Fig.33 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0040] Fig.34 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic top view for explaining the manufacturing method.

[0041] Fig.35 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0042] Fig.36 The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0043] Fig.37 The N-type low voltage transistor Tr of the first embodiment is used NL Schematic cross-sectional view for explaining the manufacturing method of the present invention.

[0044] Fig.38 The N-type high voltage transistor Tr of the modification example of the first embodiment is used NHA A schematic cross-sectional view for explaining the manufacturing method.

[0045] Fig.39 The N-type high voltage transistor Tr of the modification example of the first embodiment is used NHA A schematic cross-sectional view for explaining the manufacturing method.

[0046] Fig.40The N-type high voltage transistor Tr of the first embodiment is used NH A schematic cross-sectional view for explaining the manufacturing method.

[0047] Fig.41 The N-type high voltage transistor Tr of the second embodiment is shown. NH A schematic cross-sectional view of the structure.

[0048] Fig.42 The N-type high voltage transistor Tr constituting the second embodiment is shown. NH Schematic top view of the well formation region.

[0049] Fig.43 It conceptually means along Fig.41 The N-type high voltage transistor Tr of the BB' dashed line NH2 Graph of impurity concentration in the depth direction (Z direction).

[0050] Fig.44 The N-type high voltage transistor Tr of the second embodiment is used NH2 A schematic cross-sectional view for explaining the manufacturing method.

[0051] Fig.45 The N-type high voltage transistor Tr of the second embodiment is used NH2 A schematic cross-sectional view for explaining the manufacturing method.

[0052] Fig.46 The N-type high voltage transistor Tr of the second embodiment is used NH2 A schematic cross-sectional view for explaining the manufacturing method.

[0053] Fig.47 The N-type high voltage transistor Tr of the second embodiment is used NH2 A schematic cross-sectional view for explaining the manufacturing method.

[0054] Fig.48 The N-type high voltage transistor Tr of the second embodiment is used NH2 A schematic cross-sectional view for explaining the manufacturing method.

[0055] Fig.49 The N-type high voltage transistor Tr of the second embodiment is used NH2 A schematic cross-sectional view for explaining the manufacturing method. DETAILED DESCRIPTION

[0056] Next, the semiconductor memory device of the embodiment is described in detail with reference to the accompanying drawings. In addition, the following embodiment is only an example and is not shown to limit the present invention. In addition, the following drawings are schematic diagrams, and for the convenience of description, a part of the structure is sometimes omitted. In addition, for parts common to multiple embodiments, the same symbols are sometimes marked and the description is omitted.

[0057] In this specification, when a "semiconductor storage device" is mentioned, it may refer to a memory bare chip, or a memory system including a controller bare chip such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host such as a smartphone, a tablet terminal, or a personal computer.

[0058] In addition, in this specification, when it is mentioned that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, semiconductor components, transistors, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the off state.

[0059] In this specification, when it is mentioned that the first configuration is “connected between” the second configuration and the third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration via the first configuration.

[0060] In addition, in this specification, when it is mentioned that a circuit or the like makes two wirings or the like "conduct", for example, it sometimes means that the circuit or the like includes a transistor or the like, and the transistor or the like is set in the current path between the two wirings and the transistor or the like is in the on state.

[0061] In this specification, a specified direction parallel to the upper surface of the substrate is referred to as an X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as a Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as a Z direction.

[0062] In addition, in this specification, a direction along a designated surface is sometimes referred to as a first direction, a direction along the designated surface and intersecting the first direction is sometimes referred to as a second direction, and a direction intersecting the designated surface is sometimes referred to as a third direction. The first direction, the second direction, and the third direction may correspond to any one of the X direction, the Y direction, and the Z direction, or may not correspond to any one of the X direction, the Y direction, and the Z direction.

[0063] In addition, in this specification, expressions such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called upper, and the direction close to the substrate along the Z direction is called lower. In addition, when the lower surface or lower end of a certain structure is mentioned, it refers to the surface or end of the substrate side of the structure, and when the upper surface or upper end is mentioned, it refers to the surface or end of the structure on the opposite side of the substrate. In addition, the surface intersecting the X direction or the Y direction is called the side surface, etc.

[0064] In addition, in this specification, when "width", "length" or "thickness" in a specified direction is mentioned for a structure, component, etc., it sometimes refers to the width, length or thickness in a cross section observed using a SEM (Scanning electron microscopy) or TEM (Transmission electron microscopy).

[0065] In addition, in this specification, when "wiring" is mentioned, it may include wiring, through-hole contact electrode, the connection part for connecting wiring and through-hole contact electrode, bonding electrode, etc.

[0066] [First embodiment]

[0067] [Circuit Configuration of Memory Bare Chip MD]

[0068] Figure 1 This is a schematic block diagram showing the structure of the memory die MD according to the first embodiment. Figure 2 It is a schematic circuit diagram showing a partial structure of the memory chip MD. Figure 3 It is a schematic circuit diagram showing a partial structure of the memory chip MD.

[0069] In addition, Figure 1 The figure shows a plurality of control terminals, etc. Among the plurality of control terminals, there are cases where the control terminals are shown as corresponding to high-state valid signals (positive logic signals). In addition, there are cases where the plurality of control terminals are shown as control terminals corresponding to low-state valid signals (negative logic signals). In addition, there are cases where the plurality of control terminals are shown as control terminals corresponding to both high-state valid signals and low-state valid signals. Figure 1 In the present specification, the symbol of the control terminal corresponding to the low-state active signal includes an upper horizontal line (overline). In the present specification, the symbol of the control terminal corresponding to the low-state active signal includes a slash (" / "). In addition, Figure 1 The description is for illustration only, and the specific form can be adjusted appropriately. For example, it is also possible to make a part or all of the high-state active signals into low-state active signals, or to make a part or all of the low-state active signals into high-state active signals.

[0070] like Figure 1As shown, the memory die MD includes a memory cell array MCA and a peripheral circuit PC. The peripheral circuit PC includes a voltage generating circuit VG, a row decoder RD, a sense amplifier module SAM, and a sequencer SQC. In addition, the peripheral circuit PC includes a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR.

[0071] [Circuit Configuration of Memory Cell Array MCA]

[0072] like Figure 2 As shown, the memory cell array MCA has a plurality of memory blocks BLK. The plurality of memory blocks BLK respectively have a plurality of string components SU. The plurality of string components SU respectively have a plurality of memory strings MS. One end of the plurality of memory strings MS is respectively connected to the peripheral circuit PC via a bit line BL. In addition, the other ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via a common source line SL.

[0073] The memory string MS includes a drain side selection transistor STD, a plurality of memory cells MC (memory transistors), and a source side selection transistor STS. The drain side selection transistor STD, the plurality of memory cells MC, and the source side selection transistor STS are connected in series between the bit line BL and the source line SL. Hereinafter, the drain side selection transistor STD and the source side selection transistor STS are sometimes referred to as selection transistors (STD, STS).

[0074] The memory cell MC is a field effect transistor. The memory cell MC includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. The threshold voltage of the memory cell MC varies according to the amount of charge in the charge storage film. The memory cell MC stores 1 or more bits of data. In addition, the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS are respectively connected to word lines WL. These word lines WL are respectively connected in common to all memory strings MS in one memory block BLK.

[0075] The selection transistor (STD, STS) is a field effect transistor. The selection transistor (STD, STS) includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film may also include a charge storage layer. The gate electrodes of the selection transistors (STD, STS) are respectively connected to the selection gate lines (SGD, SGS). One drain side selection gate line SGD is commonly connected to all memory strings MS in one string component SU. One source side selection gate line SGS is commonly connected to all memory strings MS in one storage block BLK. In addition, the drain side selection gate line SGD and the source side selection gate line SGS are sometimes referred to as selection gate lines SG, respectively.

[0076] [Circuit Configuration of Voltage Generating Circuit VG]

[0077] For example, Figure 3 As shown, the voltage generating circuit VG( Figure 1 ) has a plurality of voltage generating elements vg1 to vg3. The voltage generating elements vg1 to vg3 generate voltages of a specified magnitude in the read operation, the write operation, and the erase operation, and supply voltages to the voltages through the voltage supply lines L VG1 ~L VG3 Output. For example, the voltage generating component vg1 outputs the programming voltage V in the writing operation. PGM In addition, the voltage generating element vg2 outputs the read path voltage in the read operation. In addition, the voltage generating element vg2 outputs the write path voltage in the write operation. Hereinafter, the read path voltage and the write path voltage are sometimes referred to as the non-selection voltage V USEL In addition, the voltage generating element vg3 outputs a read voltage in a read operation. In addition, the voltage generating element vg3 outputs a verification voltage in a write operation. Hereinafter, the read voltage and the verification voltage are sometimes referred to as the selection voltage V CGR The voltage generating elements vg1 to vg3 may be, for example, boosting circuits such as charge pump circuits or step-down circuits such as regulators. These step-down circuits and boosting circuits are connected to voltage supply lines L P . For the voltage supply line L P Supply voltage V CC or ground voltage V SS ( Figure 1 ). These voltage supply lines L P For example, it is connected to the pad electrode P. The operating voltage output from the voltage generating circuit VG is appropriately adjusted in accordance with a control signal from the sequencer SQC.

[0078] In addition, referring to the Figure 3 The voltage generating circuit VG( Figure 1) is a configuration for generating a programming voltage, a read path voltage, a write path voltage, a read voltage, and a verification voltage applied to the word line WL via the wiring CGI. However, the voltage generating circuit VG can generate not only an operation voltage applied to the word line WL, but also a plurality of operation voltages applied to the bit line BL, the source line SL, and the selection gate line (SGD, SGS) during the read operation, the write operation, and the erase operation for the memory cell array MCA, and output them to a plurality of voltage supply lines. These operation voltages are appropriately adjusted according to the control signal from the sequencer SQC.

[0079] [Circuit Configuration of Row Decoder RD]

[0080] For example, Figure 3 As shown, the row decoder RD ( Figure 1 ) includes a row control circuit RowC, a word line decoder WLD, a driver circuit DRV, and an address decoder not shown. The row control circuit RowC includes a plurality of block decoder elements blkd and a block decoder not shown.

[0081] The plurality of block decoder elements blkd correspond to the plurality of memory blocks BLK in the memory cell array MCA. The block decoder element blkd includes a plurality of word line switches WLSW. The plurality of word line switches WLSW correspond to the plurality of word lines WL in the memory blocks BLK.

[0082] The word line switch WLSW is, for example, a field effect type NMOS (N-channel Metal Oxide Semiconductor) transistor. The drain electrode of the word line switch WLSW is connected to the word line WL. The source electrode of the word line switch WLSW is connected to the wiring CGI. The wiring CGI is connected to all the block decoder components blkd in the row control circuit RowC. The gate electrode of the word line switch WLSW is connected to the signal supply line BLKSEL. The signal supply line BLKSEL is provided in plurality corresponding to all the block decoder components blkd. In addition, the signal supply line BLKSEL is connected to all the word line switches WLSW in the block decoder components blkd.

[0083] In a read operation, a write operation, etc., for example, with the address register ADR ( Figure 1 ) in the address data D ADDThe signal supply line BLKSEL corresponding to one block decoder component blkd corresponding to the included block address becomes "H (High)" state. In addition, the signal supply line BLKSEL corresponding to the other block decoder components blkd becomes "L (Low)" state. In addition, the voltage corresponding to the plurality of word lines WL is supplied to the wiring CGI. Thus, the voltage is supplied to the word line WL in one memory block BLK corresponding to the block address. In addition, the word lines WL in the other memory blocks BLK become floating.

[0084] The word line decoder WLD includes a plurality of word line decoding elements wld. The plurality of word line decoding elements wld correspond to a plurality of memory cells MC in the memory string MS. Figure 3 In the example, the word line decoding element wld has two transistors T WLS , T WLU . Transistor T WLS , T WLU For example, it is a field effect type NMOS transistor. WLS , T WLU The drain electrode of the transistor T is connected to the wiring CGI. WLS The source electrode is connected to the wiring CGI S . Transistor T WLU The source electrode is connected to the wiring CGI U . Transistor T WLS The gate electrode is connected to the signal line WLSEL S . Transistor T WLU The gate electrode is connected to the signal line WLSEL U Signal line WLSEL S Corresponding to a transistor T included in all word line decoding elements wld WLS A plurality of signal lines WLSEL are provided. U Corresponding to another transistor T included in all word line decoding components wld WLU In addition, the two transistors T WLS , T WLU The structure will be described below.

[0085] In a read operation, a write operation, etc., for example, with the address register ADR ( Figure 1 ) in the address data D ADD The signal line WLSEL corresponding to a word line decoding component wld corresponding to the page address included S becomes "H" state, and its corresponding WLSEL U In addition, the signal line WLSEL corresponding to the other word line decoding elements wld isS Becomes "L" state, and its corresponding WLSEL U In addition, the wiring CGI S A voltage corresponding to the selected word line WL is supplied. U A voltage corresponding to the non-selected word line WL is supplied. Thus, a voltage corresponding to the selected word line WL is supplied to one word line WL corresponding to the page address. In addition, a voltage corresponding to the non-selected word line WL is supplied to the other word lines WL.

[0086] The driver circuit DRV includes, for example, six transistors T DRV1 ~T DRV6 . Transistor T DRV1 ~T DRV6 For example, it is a field effect type NMOS transistor. DRV1 ~T DRV4 The drain electrode is connected to the wiring CGI S . Transistor T DRV5 、T DRV6 The drain electrode is connected to the wiring CGI U . Transistor T DRV1 The source electrode is supplied with a voltage via a voltage line L VG1 Connected to the output terminal of the voltage generating element vg1. Transistor T DRV2 、T DRV5 The source electrode is supplied with a voltage via a voltage line L VG2 Connected to the output terminal of the voltage generating component vg2. Transistor T DRV3 The source electrode is supplied with a voltage via a voltage line L VG3 Connected to the output terminal of the voltage generating component vg3. Transistor T DRV4 、T DRV6 The source electrode is supplied with a voltage via a voltage line L P Connected to the pad electrode P. In the transistor T DRV1 ~T DRV6 The gate electrodes of the six transistors T1 and T2 are connected to the signal lines VSEL1 to VSEL6, respectively. DRV1 ~T DRV6 The structure will be described below.

[0087] In the read operation, write operation, etc., for example, with the wiring CGI S One of the corresponding signal lines VSEL1 to VSEL4 becomes "H" state, and the others become "L" state. U One of the corresponding two signal lines VSEL5 and VSEL6 becomes the "H" state, and the other becomes the "L" state.

[0088] The address decoder (not shown) is configured to receive the address from the sequencer SQC ( Figure 1 ) control signals refer to the address register ADR ( Figure 1 ) of the row address RA. The row address RA includes the block address and the page address. The address decoder transmits the signal lines BLKSEL and WLSEL S 、WLSEL U The voltage is controlled to be "H" state or "L" state.

[0089] In addition, Figure 3 In the example of FIG. 1 , in the row decoder RD, one block decoder component blkd is provided for each storage block BLK. However, this configuration can be changed as appropriate. For example, one block decoder component blkd may be provided for each of two or more storage blocks BLK.

[0090] [Circuit configuration of sense amplifier module SAM]

[0091] Sense Amplifier Module SAM( Figure 1 ) detects the on state / off state of the memory cell MC and obtains data representing the state of the memory cell MC. This action is sometimes called a sensing action. The sense amplifier module SAM includes a plurality of sense amplifier components. The plurality of sense amplifier components correspond to the plurality of bit lines BL. The plurality of sense amplifier components respectively include a sense amplifier circuit and a latch circuit.

[0092] [Circuit Configuration of Cache Memory CM]

[0093] Cache memory CM ( Figure 1 ) has a plurality of latch circuits. The plurality of latch circuits are connected to the latch circuit in the sense amplifier module SAM via the wiring DBUS. The data DAT contained in the plurality of latch circuits is sequentially transmitted to the sense amplifier module SAM or the input / output control circuit I / O.

[0094] In addition, a decoding circuit and a switch circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA stored in the address register ADR. The switch circuit switches the latch circuit corresponding to the column address CA to the bus BUS ( Figure 1 ) is turned on.

[0095] [Circuit configuration of sequencer SQC]

[0096] Sequencer SQC( Figure 1 ) According to the instruction data D stored in the instruction register CMR CMD, outputs the internal control signal to the row decoder RD, the sense amplifier module SAM and the voltage generating circuit VG. In addition, the sequencer SQC appropriately outputs the state data D indicating its own state. ST Output to status register STR.

[0097] In addition, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY / ( / BY). During the period when the terminal RY / ( / BY) is in the "L" state (busy period), access to the memory die MD is basically prohibited. In addition, during the period when the terminal RY / ( / BY) is in the "H" state (ready period), access to the memory die MD is allowed.

[0098] [Circuit Configuration of Input / Output Control Circuit I / O]

[0099] The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, trigger signal input / output terminals DQS and / DQS, a plurality of input circuits, a plurality of output circuits, a shift register, and a buffer circuit. The plurality of input circuits, the plurality of output circuits, the shift register, and the buffer circuit are connected to the power supply voltage V CCQ and ground voltage V SS Terminals.

[0100] The data inputted through the data signal input / output terminals DQ0 to DQ7 are outputted from the buffer circuit to the cache memory CM, the address register ADR or the instruction register CMR according to the internal control signal from the logic circuit CTR. In addition, the data outputted through the data signal input / output terminals DQ0 to DQ7 are inputted from the cache memory CM or the status register STR to the buffer circuit according to the internal control signal from the logic circuit CTR.

[0101] The plurality of input circuits include, for example, a comparator connected to any one of the data signal input / output terminals DQ0 to DQ7 or both of the trigger signal input / output terminals DQS and / DQS. The plurality of output circuits include, for example, an OCD (Off Chip Driver) circuit connected to any one of the data signal input / output terminals DQ0 to DQ7 or either of the trigger signal input / output terminals DQS and / DQS.

[0102] [Circuit configuration of logic circuit CTR]

[0103] Logic circuit CTR( Figure 1 ) receives external control signals from a controller bare chip (not shown) via external control terminals / CEn, CLE, ALE, / WE, RE, and / RE, and outputs internal control signals to the input / output control circuit I / O accordingly.

[0104] [Structure of memory die MD]

[0105] Figure 4 FIG. 1 is a schematic exploded perspective view showing a configuration example of a semiconductor storage device according to the first embodiment. Figure 4 As shown, the memory die MD has a chip C on the side of the memory cell array MCA. M , and peripheral circuit PC side chip C P .

[0106] In Chip C M The upper surface of the substrate is provided with a plurality of external pad electrodes P that can be connected to bonding wires (not shown). X In addition, in chip C M The lower surface is provided with a plurality of bonding electrodes P I1 In addition, in chip C P The upper surface is provided with a plurality of bonding electrodes P I2 . Below, about chip C M , multiple bonding electrodes P will be set I1 The surface is called the front surface, where multiple external pad electrodes P are set. X The surface of the chip C is called the back surface. P , multiple bonding electrodes P will be set I2 The surface facing the chip C is called the front side, and the surface opposite to the front side is called the back side. P The front side is set at the ratio chip C P The back of the chip is further up. M The back side is set at the ratio chip C M The front is further up.

[0107] Chip C M and Chip C P Chip C M The front side with chip C P The plurality of electrodes P are arranged facing each other. I1 Corresponding to a plurality of bonded electrodes P I2 The arrangement is configured to be able to be bonded with multiple electrodes P I2 Bonding position. Bonding electrode P I1 With the bonding electrode P I2 As a chip C M With chip C P The bonded electrodes that are bonded and electrically connected function.

[0108] In addition, Figure 4 In the example, chip C M The corners a1, a2, a3, and a4 of the chip C are P The corners b1, b2, b3, and b4 correspond to each other.

[0109] Figure 5 It means chip C M A schematic bottom view of an example of the structure of . Figure 5 In the figure, the bonding electrode P is omitted. I1 etc. Figure 6 and Figure 7 It is a schematic cross-sectional view showing a partial structure of the memory die MD. Figure 8 It means chip C M A schematic bottom view of a portion of FIG. Figure 8 In FIG. 1 , an XY cross section at a height position corresponding to the word line WL is shown in the left region, and an XY cross section at a height position corresponding to the drain side selection gate line SGD is shown in the right region. Figure 8 In the right area of ​​, the through-hole contact electrodes ch, Vy and the bit line BL are also shown to show the connection portion between the semiconductor layer 120 and the bit line BL. Figure 8 In the left region, through-hole contact electrodes ch, Vy and a bit line BL are also provided. Fig. 9 It means chip C M A schematic cross-sectional view of a portion of . Fig. 9 The YZ cross section is shown, but when a cross section other than the YZ cross section (for example, the XZ cross section) along the central axis of the semiconductor layer 120 is observed, the same Fig. 9 Same structure.

[0110] [Chip C M Structure of

[0111] exist Figure 5 In the example, chip C M The four memory planes MP0 to MP3 are arranged along the X direction. In addition, the four memory planes MP0 to MP3 are sometimes referred to as memory planes MP. In addition, the four memory planes MP0 to MP3 each include a plurality of memory blocks BLK arranged along the Y direction. Figure 5 In the example, the four memory planes MP0 to MP3 each include a connection area R disposed at both ends in the X direction. HU , and a memory hole region R disposed therebetween MH (Memory area). In addition, chip C M A peripheral region R is provided on one end side of the four memory planes MP0 to MP3 in the Y direction. P .

[0112] In the example shown in the figure, the connection area R HU The wiring area R is provided at both ends of the storage plane MP in the X direction. However, this configuration is only an example, and the specific configuration can be adjusted appropriately. HUThe wiring area R may be arranged at one end of the memory plane MP in the X direction instead of at both ends of the memory plane MP in the X direction. HU Alternatively, the storage plane MP may be provided at the center or near the center of the storage plane MP in the X direction.

[0113] For example, Figure 6 As shown, chip C M With base layer L SB , set in the base layer L SB The memory cell array layer L below MCA , set in the memory cell array layer L MCA The through-hole contact electrode layer CH below, the plurality of wiring layers M0 and M1 provided below the through-hole contact electrode layer CH, and the die bonding electrode layer MB provided below the wiring layers M0 and M1.

[0114] [Chip C M The base layer L SB Structure of

[0115] For example, Figure 6 As shown, the base layer L SB A memory cell array layer L is provided. MCA A conductive layer 100 is disposed on the upper surface of the conductive layer 100 , an insulating layer 101 is disposed on the upper surface of the conductive layer 100 , a back wiring layer MA is disposed on the upper surface of the insulating layer 101 , and an insulating layer 102 is disposed on the upper surface of the back wiring layer MA.

[0116] Conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) implanted with N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), a metal such as tungsten (W), or a silicide such as tungsten silicide (WSi).

[0117] The conductive layer 100 serves as the source line SL ( Figure 1 ) part functions. The conductive layer 100 corresponds to the four storage planes MP0 to MP3 ( Figure 5 ) and four are provided. Regions VZ not including the conductive layer 100 are provided at the ends of the memory plane MP in the X direction and the Y direction.

[0118] The insulating layer 101 includes, for example, silicon oxide (SiO 2 ) or the like.

[0119] The back wiring layer MA includes a plurality of wirings ma. The plurality of wirings ma may include, for example, aluminum (Al) or the like.

[0120] Some of the plurality of wiring lines ma are used as source lines SL ( Figure 2 ) part. The wiring ma corresponds to the four storage planes MP0 to MP3 ( Figure 5The wirings ma are electrically connected to the conductive layer 100, respectively.

[0121] In addition, a part of the plurality of wirings ma is used as an external pad electrode P X The wiring ma is arranged in the peripheral area R P The wiring line ma is connected to the memory cell array layer L in the region VZ not including the conductive layer 100. MCA The through-hole in the insulating layer 102 contacts the electrode CC. In addition, part of the wiring ma is exposed to the outside of the memory chip MD through the opening TV provided in the insulating layer 102.

[0122] The insulating layer 102 is, for example, a passivation layer made of an insulating material such as polyimide.

[0123] [Chip C M The memory cell array layer L MCA The memory hole area R MH Structure in

[0124] Like reference Figure 5 As described above, in the memory cell array layer L MCA A plurality of storage blocks BLK arranged along the Y direction are provided in the Figure 6 As shown, an inter-block insulating layer ST made of silicon oxide (SiO2) or the like is provided between two memory blocks BLK adjacent to each other in the Y direction. A plurality of stacked structures including a plurality of conductive layers 110 arranged in the Z direction and arranged in the Y direction correspond to the plurality of memory blocks BLK.

[0125] For example, Figure 6 As shown in FIG. 1 , the memory block BLK includes a plurality of conductive layers 110 arranged along the Z direction and a plurality of semiconductor layers 120 extending in the Z direction. Fig. 9 As shown, gate insulating films 130 are respectively disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120 .

[0126] The conductive layer 110 has a substantially plate-like shape extending in the X direction. The conductive layer 110 may also include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or molybdenum (Mo). In addition, the conductive layer 110 may also include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between the plurality of conductive layers 110 arranged in the Z direction.

[0127] One or more conductive layers 110 located at the top of the plurality of conductive layers 110 serve as source side selection transistors STS ( Figure 2 ) and the source side selection gate line SGS function (refer to Figure 6The plurality of conductive layers 110 are electrically independent of each memory block BLK.

[0128] In addition, a plurality of conductive layers 110 located below the conductive layer 110 serve as memory cells MC ( Figure 2 ) functions as a gate electrode and a word line WL. The plurality of conductive layers 110 are electrically independent for each memory block BLK.

[0129] In addition, one or more conductive layers 110 located below the conductive layer 110 function as the gate electrode of the drain-side selection transistor STD and the drain-side selection gate line SGD. Figure 8 As shown in FIG. 1 , the width Y of the plurality of conductive layers 110 in the Y direction is SGD smaller than the width Y in the Y direction of the conductive layer 110 functioning as the word line WL. WL In addition, an inter-string component insulating layer SHE such as silicon oxide (SiO 2 ) is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0130] For example, Figure 8 As shown in FIG. 1 , the semiconductor layer 120 is arranged in a specified pattern in the X direction and the Y direction. The semiconductor layer 120 is respectively used as a memory string MS ( Figure 2 ) and the channel region of the selection transistors (STD, STS). The semiconductor layer 120 includes, for example, polycrystalline silicon (Si). The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the center. The outer peripheral surface of the semiconductor layer 120 is respectively surrounded by a plurality of conductive layers 110 and faces the plurality of conductive layers 110.

[0131] In addition, an impurity region (not shown) is provided at the upper end of the semiconductor layer 120. The impurity region is connected to the conductive layer 100 (see Figure 6 ). The impurity region contains, for example, N-type impurities such as phosphorus (P) or P-type impurities such as boron (B).

[0132] In addition, an impurity region (not shown) is provided at the lower end of the semiconductor layer 120. The impurity region is connected to the bit line BL via the via contact electrode ch and the via contact electrode Vy. The impurity region contains, for example, N-type impurities such as phosphorus (P).

[0133] For example, Figure 8 As shown in FIG. 1 , the gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. Fig. 9As shown in the figure, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132 and a blocking insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the blocking insulating film 133 include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), etc. The charge storage film 132 includes, for example, a film capable of storing charges such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132 and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 100.

[0134] In addition, Fig. 9 2 shows an example in which the gate insulating film 130 includes a charge storage film 132 made of silicon nitride or the like. However, the gate insulating film 130 may include a floating gate made of, for example, polysilicon containing N-type or P-type impurities.

[0135] [Chip C M The memory cell array layer L MCA Wiring area R HU Structure in

[0136] like Figure 7 As shown, in the wiring area R HU A plurality of through-hole contact electrodes CC are provided in the conductive layer 110. The plurality of through-hole contact electrodes CC extend in the Z direction respectively and are connected to the conductive layer 110 (WL, SGD, SGS) at the upper ends.

[0137] [Chip C M The memory cell array layer L MCA The surrounding area R P Structure in

[0138] In the surrounding area R P For example, Figure 6 As shown, corresponding to the external pad electrode P X A plurality of through-hole contact electrodes CC are provided. The plurality of through-hole contact electrodes CC are connected at the upper ends to the external pad electrodes P X .

[0139] [Structure of Through-hole Contact Electrode Layer CH]

[0140] The plurality of through-hole contact electrodes ch included in the through-hole contact electrode layer CH are electrically connected to the memory cell array layer L. MCA The composition and chip C P At least one of the components.

[0141] The through hole contact electrode layer CH includes a plurality of through hole contact electrodes ch. The plurality of through hole contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The through hole contact electrodes ch are provided corresponding to the plurality of semiconductor layers 120 and are connected to the lower ends of the plurality of semiconductor layers 120.

[0142] [Chip C M The structure of the wiring layers M0 and M1]

[0143] The plurality of wirings included in the wiring layers M0 and M1 are electrically connected to the memory cell array layer L. MCA The composition and chip C P At least one of the components.

[0144] The wiring layer M0 includes a plurality of wirings m0. The plurality of wirings m0 may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu). In addition, some of the plurality of wirings m0 function as bit lines BL. For example, Figure 8 As shown, the bit lines BL are arranged along the X direction and extend in the Y direction.

[0145] For example, Figure 6 As shown in FIG. 1 , the wiring layer M1 includes a plurality of wirings m1. The plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Figure 6 and Figure 7 As shown, the plurality of wirings m1 are electrically connected to the wiring m0 via the through-hole contact electrode V1.

[0146] [Structure of chip bonding electrode layer MB]

[0147] The plurality of wirings included in the die attach electrode layer MB are electrically connected to the memory cell array layer L, for example. MCA The composition and chip C P At least one of the components.

[0148] The chip bonding electrode layer MB includes a plurality of bonding electrodes P I1 (bonding pad). The plurality of bonding electrodes P I1 For example, the barrier conductive film p may include titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I1B And copper (Cu) and other metal films I1M Laminated films, etc.

[0149] In addition, for example Figure 6 As shown, chip CP The semiconductor device includes a semiconductor substrate 200, an electrode layer GC provided above the semiconductor substrate 200, wiring layers D0, D1, D2, D3, and D4 provided above the electrode layer GC, and a chip bonding electrode layer DB provided above the wiring layers D0, D1, D2, D3, and D4.

[0150] [Chip C P Structure of the semiconductor substrate 200]

[0151] The semiconductor substrate 200 includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B). On the front surface of the semiconductor substrate 200, for example, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S where the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region STI are provided. A portion of the P-type well region 200P is provided in the semiconductor substrate region 200S, and a portion of the P-type well region 200P is provided in the N-type well region 200N. The N-type well region 200N, the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S function as a portion of a plurality of transistors Tr, a plurality of capacitors, etc. constituting the peripheral circuit PC, respectively. A portion of the plurality of transistors Tr functions as a word line switch WLSW. The insulating region STI includes, for example, silicon oxide (SiO 2 ) or the like, and is provided to extend from the front surface of the semiconductor substrate 200 in the Z direction.

[0152] [Chip C P The structure of the electrode layer GC]

[0153] An electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the front surface of the semiconductor substrate 200. In addition, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to the through-hole contact electrodes CS.

[0154] The N-type well region 200N of the semiconductor substrate 200 , the P-type well region 200P provided in the N-type well region 200N and the semiconductor substrate region 200S, and the semiconductor substrate region 200S function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC, and one electrode of a plurality of capacitors.

[0155] The plurality of electrodes gc included in the electrode layer GC function as gate electrodes of the plurality of transistors Tr constituting the peripheral circuit PC, other electrodes of the plurality of capacitors, and the like.

[0156] The through hole contact electrode CS extends in the Z direction and is connected to the semiconductor substrate 200 or the upper surface of the electrode gc at the lower end. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the through hole contact electrode CS and the semiconductor substrate 200. The through hole contact electrode CS may also include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0157] [Chip C P The structure of the wiring layers D0, D1, D2, D3, and D4]

[0158] For example, Figure 6 As shown in FIG. 1 , a plurality of connection portions and a plurality of wirings included in D0, D1, D2, D3, and D4 are electrically connected to the memory cell array layer L, for example. MCA The composition and chip C P At least one of the components.

[0159] The wiring layers D0, D1, and D2 include a plurality of connection portions d0, d1, and d2 and a plurality of wirings, respectively. The plurality of connection portions d0, d1, and d2 and the plurality of wirings may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0160] The wiring layers D3 and D4 include a plurality of connection portions d3 and d4 and a plurality of wirings, respectively. The plurality of connection portions d3 and d4 and the plurality of wirings may include, for example, barrier conductive films such as titanium nitride (TiN), tantalum nitride (TaN), and a laminated film of tantalum nitride (TaN) and tantalum (Ta), and a laminated film of a metal film such as copper (Cu).

[0161] [Structure of chip bonding electrode layer DB]

[0162] The plurality of wirings included in the die attach electrode layer DB are electrically connected to the memory cell array layer L MCA The composition and chip C P At least one of the components.

[0163] The chip bonding electrode layer DB includes a plurality of bonding electrodes P I2 The plurality of bonded electrodes P I2 For example, the barrier conductive film p may include titanium nitride (TiN), tantalum nitride (TaN), or a laminated film of tantalum nitride (TaN) and tantalum (Ta). I2B And copper (Cu) and other metal films I2M Laminated films, etc.

[0164] In addition, if the bonded electrode P I1 With the bonding electrode P I2 Using metal films such as copper (Cu) I1M 、pI2M , then the metal film p I1M With metal film I2M However, the electrodes P can be integrated and the boundaries between them can be difficult to identify. I1 With the bonding electrode P I2 Deformation of the shape after bonding and the barrier conductive film p I1B 、p I2B The bonding structure is confirmed by the positional deviation (discontinuous portion on the side). I1 And bonding electrode P I2 In the case of , their respective side surfaces have an inclined shape. I1 With the bonding electrode P I2 In the cross-sectional shape of the bonded portion along the Z direction, the side wall is not linear and is not rectangular. I1 With the bonding electrode P I2 When bonded, the bottom, side and top surfaces of the Cu layers are covered with barrier metal. In contrast, in a general wiring layer using Cu, an insulating layer (SiN or SiCN, etc.) having the function of preventing Cu oxidation is provided on the top surface of Cu, and no barrier metal is provided. Therefore, even if there is no positional deviation during bonding, it can be distinguished from a general wiring layer.

[0165] [Structure of transistor Tr]

[0166] Fig.10 FIG. 1 is a schematic cross-sectional view showing a part of the structure of the semiconductor memory device according to the first embodiment. Fig.10 2 shows an example of the structure of a plurality of transistors Tr provided in the semiconductor substrate region 200S according to the present embodiment.

[0167] like Fig.10 As shown, on the front side of the semiconductor substrate 200, for example, P-type well regions 310a, 310 containing P-type impurities such as boron (B), N-type well regions 311a, 311 containing N-type impurities such as phosphorus (P), a semiconductor substrate region 200S where the N-type well regions 311a, 311 and the P-type well regions 310a, 310 are not provided, and an insulating region STI is provided. The P-type well regions 310a, 310 are reference Figure 6 The N-type well regions 311a and 311b are examples of the P-type well region 200P described above. Figure 6 An example of the N-type well region 200N described above.

[0168] Like reference Figure 6 and Figure 7As described above, a plurality of transistors Tr are provided in the chip C. P The plurality of transistors Tr include a plurality of N-type high voltage transistors Tr. NH , multiple P-type high voltage transistors Tr PH , multiple N-type low voltage transistors Tr NL And multiple P-type low voltage transistors Tr PL . P-type high voltage transistor Tr PH , N-type low voltage transistor Tr NL And P-type low voltage transistor Tr PL With high voltage transistor Tr NH The same semiconductor substrate 200 is provided. In addition, sometimes the high voltage transistor Tr NH Tr PH Supplying a voltage greater than 10V, for example. High voltage transistor Tr NH For example, the row decoder RD is set. For example, refer to Figure 3 The two transistors T in the word line decoder WLD are shown in FIG. WLS 、T WLU Through the high voltage transistor Tr NH In addition, for example, refer to Figure 3 The six transistors T in the driver circuit DRV are shown in FIG. DRV1 ~T DRV6 Also through the high voltage transistor Tr NH accomplish.

[0169] Next, the N-type high voltage transistor Tr NH , P-type high voltage transistor Tr PH , N-type low voltage transistor Tr NL And P-type low voltage transistor Tr PL The structure of is described below.

[0170] [High voltage transistor Tr NH Structure of

[0171] Fig.11 The N-type high voltage transistor Tr of the first embodiment is shown. NH Schematic top view of the structure. Fig.12 The N-type high voltage transistor Tr of the first embodiment is shown. NH In addition, Fig.12 Yes Fig.11 The structure shown is a diagram in which the structure is cut along the dotted line AA'. Fig.13 The N-type high voltage transistor Tr of the first embodiment is used NH FIG. 5 is a diagram illustrating the impurity concentration of α. Fig.14The N-type high voltage transistor Tr of the first embodiment is shown. NH A cross-sectional view of a portion of the structure. In addition, Fig.14 Yes Fig.13 A cross-sectional view showing an enlarged area a in FIG. Fig.15 It is conceptually expressed Fig.11 A graph of the impurity concentration in the region shown along the dashed line AA'. Fig.15 Indicates the impurity concentration of N-type impurities such as phosphorus (P) or arsenic (As).

[0172] For example, Fig.12 As shown in the figure, the high voltage transistor Tr NH The semiconductor substrate region 200S is provided in the semiconductor substrate 200. For example, Fig.12 and Fig.14 As shown, the high voltage transistor Tr NH A semiconductor substrate 200S is provided with a portion of the semiconductor substrate region 200S, a gate insulating film 241 such as silicon oxide (SiO2) disposed on the front surface of the semiconductor substrate 200, a gate electrode component 243 such as polysilicon (Si) disposed on the upper surface of the gate insulating film 241, a gate electrode component 244 such as tungsten (W) disposed on the upper surface of the gate electrode component 243, a covering insulating layer 245 such as silicon oxide (SiO2) or silicon nitride (Si3N4) disposed on the upper surface of the gate electrode component 244, and a sidewall insulating film 246 such as silicon oxide (SiO2) or silicon nitride (Si3N4) disposed on the side surfaces of the gate electrode component 243, the gate electrode component 244, and the covering insulating layer 245 in the X direction or Y direction. In addition, the gate electrode component 243 contains, for example, N-type impurities such as phosphorus (P) or arsenic (As) or P-type impurities such as boron (B). The gate electrode component 243 and the gate electrode component 244 are reference Figure 6 One of the plurality of electrodes gc described above functions as a gate electrode 201 provided on a gate insulating film 241. The gate insulating film 241 is a Figure 6 One of the multiple insulating layers 200G described above.

[0173] For example, Fig.12 and Fig.14 As shown, the high voltage transistor Tr NH It has a liner insulating layer 247 such as silicon oxide (SiO2) and a liner insulating layer 248 such as silicon nitride (Si3N4) stacked on the front surface of the semiconductor substrate 200, the side surface of the gate insulating film 241 in the X direction or Y direction, the side surface of the sidewall insulating film 246 in the X direction or Y direction, and the upper surface of the covering insulating layer 245.

[0174] For example, Fig.12 As shown, in the high voltage transistor Tr NHA through hole contact electrode CS extending in the Z direction is connected. The through hole contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The through hole contact electrode CS penetrates the liner insulating layer 247 and the liner insulating layer 248 and is connected to the front surface of the semiconductor substrate 200, serving as a high voltage transistor Tr NH In addition, the through-hole contact electrode CS not shown in the figure can also penetrate the liner insulating layer 248, the liner insulating layer 247 and the cover insulating layer 245 and be connected to the upper surface of the gate electrode part 244. The through-hole contact electrode CS not shown in the figure serves as a high voltage transistor Tr NH A portion of the gate electrode functions.

[0175] For example, Fig.12 As shown in the figure, the high voltage transistor Tr NH The surface of the semiconductor substrate 200 facing the gate electrode component 243 has a channel region 206. In other words, the channel region 206 is a region included in the semiconductor substrate 200 and provided at a position overlapping with the gate electrode 201 when viewed from the Z direction intersecting the surface of the semiconductor substrate 200. Fig.11 and Fig.12 As shown in FIG. 1 , a high concentration N-diffusion layer 202, a low concentration N-diffusion layer 203 and an N+ diffusion layer 204 are provided on the front surface of the semiconductor substrate 200. Fig.11 In the figure, the high concentration N-diffusion layer 202, the low concentration N-diffusion layer 203 and the N+ diffusion layer 204 on the left side function as the source region, and the high concentration N-diffusion layer 202, the low concentration N-diffusion layer 203 and the N+ diffusion layer 204 on the right side function as the drain region.

[0176] The N+ diffusion layer 204 is a diffusion layer region included in the semiconductor substrate 200, connected to the through-hole contact electrode CS extending in the Z direction, and contains first conductivity type impurities. The first conductivity type impurities are, for example, N-type impurities such as phosphorus (P) or arsenic (As). In addition, the impurity concentration of the N-type impurities contained in the N+ diffusion layer 204 is greater than the impurity concentration of the N-type impurities contained in the high-concentration N-diffusion layer 202 and the low-concentration N-diffusion layer 203.

[0177] The high concentration N-diffusion layer 202 is a diffusion layer region included in the semiconductor substrate 200, disposed between the channel region 206 and the N+ diffusion layer 204, and containing first conductivity type impurities. At least a portion of the high concentration N-diffusion layer 202 is disposed at a position overlapping the sidewall insulating film 246 when viewed from the Z direction. In addition, Fig.14The region b shown is a region provided at a position overlapping with the channel region 206 when viewed from the Z direction, and is sometimes referred to as an overlapping region. The impurity concentration of the N-type impurities contained in the high-concentration N-diffusion layer 202 is higher than the impurity concentration of the N-type impurities contained in the low-concentration N-diffusion layer 203. In addition, the impurity concentration of the N-type impurities contained in the high-concentration N-diffusion layer 202 is lower than the impurity concentration of the N-type impurities contained in the N+ diffusion layer 204.

[0178] The low concentration N-diffusion layer 203 is a diffusion layer region included in the semiconductor substrate 200, provided between the high concentration N-diffusion layer 202 and the N+ diffusion layer 204, connected to the high concentration N-diffusion layer 202, and containing first conductivity type impurities.

[0179] Here, if Fig.15 As shown, Fig.11 and Fig.12 The high voltage transistor Tr shown in the figure NH The peak value of the impurity concentration of the low concentration N-diffusion layer 203 is, for example, 3 to 11×10 17 atoms / cm 3 On the other hand, the peak value of the impurity concentration of the high concentration N-diffusion layer 202 is, for example, 5 to 15×10 17 atoms / cm 3 In addition, the peak value of the impurity concentration of the N+ diffusion layer 204 is, for example, 0.1 to 10×10 20 atoms / cm 3 . Fig.15 The region b shown is the overlapping region.

[0180] In addition, if Fig.11 and Fig.14 As shown, the width L1 of the high concentration N-diffusion layer 202 in the Y direction is greater than the width L3 of the sidewall insulating film 246 in the Y direction. The distance L2 in the Y direction between the high concentration N-diffusion layer 202 and the N+ diffusion layer 204 is greater than the width L1 of the high concentration N-diffusion layer 202 in the Y direction. Here, the width L1 of the high concentration N-diffusion layer 202 in the Y direction is, for example, about 325 nm, but may also be greater than 250 nm and less than 450 nm. The width L3 of the sidewall insulating film 246 in the Y direction is, for example, about 60 nm, but may also be greater than 50 nm and less than 70 nm. In addition, as Fig.14 As shown, the thickness T of the gate insulating film in the Z direction is, for example, approximately 42 nm, but may be greater than or equal to 35 nm and less than or equal to 50 nm.

[0181] In the high voltage transistor Tr NHIn the case where, for example, 20V is applied to the drain electrode, 0V is applied to the gate electrode, and the source electrode is not applied with a voltage and becomes floating, the off state is called the off state. In this state, if, for example, 25V is applied to the gate electrode, the high voltage transistor Tr NH The high voltage transistor Tr is turned on and the voltage applied to the drain region is transferred to the source region. NH In the instant when the OFF state is changed to the ON state, a large potential difference is generated between the drain region and the source region. Therefore, the electric field near the drain region at the position overlapping with the sidewall insulating film 246 when viewed from the Z direction becomes strong, and impact ionization occurs, thereby generating hot carriers (hot electrons).

[0182] In the high voltage transistor Tr NH In the process, hot carriers generated by impact ionization are captured by Fig.13 In the insulating film near the sidewall insulating film 246 included in the a region (in the gate insulating film 241, in the liner insulating layer 247, and in the liner insulating layer 248).

[0183] In addition, impurities can also be introduced into the high voltage transistor Tr NH For example, when you want to make the high voltage transistor Tr NH When the gate-source voltage that changes from the off state to the on state, i.e., the threshold voltage, is positive, a P-type impurity such as boron (B) may be introduced into the channel region 206. On the other hand, when the threshold voltage is to be negative, an N-type impurity such as arsenic may be introduced into the channel region 206. In this way, by introducing a P-type or N-type impurity into the high voltage transistor Tr NH The threshold voltage is adjusted in the channel region 206.

[0184] [P-type high voltage transistor Tr PH Structure of

[0185] Fig.16 Yes means Fig.10 The P-type high voltage transistor Tr shown PH A schematic cross-sectional view of the structure of. Fig.16 As shown, the P-type high voltage transistor Tr PH The N-type well region 311 is provided in the semiconductor substrate 200. The P-type high voltage transistor Tr PHIt includes a portion of an N-type well region 311, a gate insulating film 251 such as silicon oxide (SiO2) arranged on the front surface of the N-type well region 311 (semiconductor substrate 200), a gate electrode component 253 such as polysilicon (Si) arranged on the upper surface of the gate insulating film 251, a gate electrode component 254 such as tungsten (W) arranged on the upper surface of the gate electrode component 253, a covering insulating layer 255 such as silicon oxide (SiO2) or silicon nitride (Si3N4) arranged on the upper surface of the gate electrode component 254, and a sidewall insulating film 256 such as silicon oxide (SiO2) or silicon nitride (Si3N4) arranged on the side surfaces of the gate electrode component 253, the gate electrode component 254 and the covering insulating layer 255 in the X direction or Y direction. In addition, the gate electrode component 253 contains, for example, N-type impurities such as phosphorus (P) or arsenic (As) or P-type impurities such as boron (B). The gate electrode component 253 and the gate electrode component 254 are reference Figure 6 One of the plurality of electrodes gc described above functions as a gate electrode provided on the gate insulating film 251. The gate insulating film 251 is a Figure 6 The P-type high voltage transistor Tr is one of the plurality of insulating layers 200G described above. PH The length (thickness) of the gate insulating film 251 in the Z direction is similar to that of the N-type high voltage transistor Tr NH The length (thickness) of the gate insulating film in the Z direction is the same, for example, about 42 nm, but can also be greater than 35 nm and less than 50 nm.

[0186] For example, Fig.16 As shown, the P-type high voltage transistor Tr PH It has a liner insulating layer 257 such as silicon oxide (SiO2) and a liner insulating layer 258 such as silicon nitride (Si3N4) stacked on the front surface of the N-type well region 311, the side surface of the gate insulating film 251 in the X direction or Y direction, the side surface of the sidewall insulating film 256 in the X direction or Y direction, and the upper surface of the covering insulating layer 255.

[0187] In the P-type high voltage transistor Tr PH A through-hole contact electrode CS extending in the Z direction is connected. The through-hole contact electrode CS penetrates the liner insulating layer 257 and the liner insulating layer 258 and is connected to the front surface of the N-type well region 311, serving as a P-type high voltage transistor Tr PH In addition, the through-hole contact electrode CS not shown in the figure can also penetrate the liner insulating layer 258, the liner insulating layer 257 and the cover insulating layer 255 and be connected to the upper surface of the gate electrode part 244. The through-hole contact electrode CS not shown in the figure serves as a P-type high voltage transistor Tr PH A portion of the gate electrode functions.

[0188] P-type high voltage transistor Tr PH The front surface of the N-type well region 311 opposite to the gate electrode component 253 has a channel region. In other words, the channel region is a region included in the N-type well region 311 of the semiconductor substrate 200 and disposed at a position overlapping with the gate electrode when viewed from the Z direction. Fig.16 As shown in FIG. 1 , a P+ diffusion layer 213 is provided on the front surface of the N-type well region 311. Fig.16 In FIG. 1 , the P+ diffusion layer 213 located on the left side functions as a source region, and the P+ diffusion layer 213 located on the right side functions as a drain region.

[0189] The P+ diffusion layer 213 is a diffusion layer region included in the N-type well region 311 of the semiconductor substrate 200, connected to the through-hole contact electrode CS extending in the Z direction, and contains second conductivity type impurities. The second conductivity type impurities are, for example, P-type impurities such as boron (B).

[0190] In addition, the P-type high voltage transistor Tr PH With high voltage transistor Tr NH Different from this, there is no diffusion layer corresponding to the high-concentration N-diffusion layer 202 .

[0191] [N-type low voltage transistor Tr NL Structure of

[0192] Fig.17 Yes means Fig.10 The N-type low voltage transistor Tr shown NL A schematic cross-sectional view of the structure of. Fig.17 As shown, the N-type low voltage transistor Tr NL The P-type well region 310 is provided in the semiconductor substrate 200. The N-type low voltage transistor Tr NL It includes a portion of a P-type well region 310, a gate insulating film 341 such as silicon oxide (SiO2) provided on the front surface of the P-type well region 310 (semiconductor substrate 200), a gate electrode component 343 such as polysilicon (Si) provided on the upper surface of the gate insulating film 341, a gate electrode component 344 such as tungsten (W) provided on the upper surface of the gate electrode component 343, a covering insulating layer 345 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the upper surface of the gate electrode component 344, and a sidewall insulating film 346 such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on the side surfaces of the gate electrode component 343, the gate electrode component 344 and the covering insulating layer 345 in the X direction or Y direction. In addition, the gate electrode component 343 contains, for example, N-type impurities such as phosphorus (P) or arsenic (As) or P-type impurities such as boron (B). In addition, the gate electrode component 343 and the gate electrode component 344 are reference Figure 6 One of the plurality of electrodes gc described above functions as a gate electrode provided on the gate insulating film 341. The gate insulating film 341 is a Figure 6 One of the plurality of insulating layers 200G described in the above description. N-type low voltage transistor Tr NL The length (thickness) of the gate insulating film 341 in the Z direction is smaller than that of the N-type high voltage transistor Tr NH The length (thickness) of the gate insulating film in the Z direction can be, for example, greater than or equal to 6 nm and less than or equal to 8 nm.

[0193] N-type low voltage transistor Tr NL It has a liner insulating layer 347 such as silicon oxide (SiO2) and a liner insulating layer 348 such as silicon nitride (Si3N4) stacked on the front surface of the P-type well region 310, the side surface of the gate insulating film 341 in the X direction or Y direction, the side surface of the sidewall insulating film 346 in the X direction or Y direction, and the upper surface of the covering insulating layer 345.

[0194] In the N-type low voltage transistor Tr NL A through-hole contact electrode CS extending in the Z direction is connected. The through-hole contact electrode CS penetrates the liner insulating layer 347 and the liner insulating layer 348 and is connected to the front surface of the P-type well region 310, serving as an N-type low voltage transistor Tr. NL In addition, the through-hole contact electrode CS not shown in the figure can also penetrate the liner insulating layer 348, the liner insulating layer 347 and the cover insulating layer 345 and be connected to the upper surface of the gate electrode part 344. The through-hole contact electrode CS not shown in the figure serves as the N-type low voltage transistor Tr NL A portion of the gate electrode functions.

[0195] In addition, the N-type low voltage transistor Tr NL The front surface of the P-type well region 310 facing the gate electrode component 343 has a channel region. In other words, the channel region is a region included in the P-type well region 310 of the semiconductor substrate 200 and disposed at a position overlapping with the gate electrode when viewed from the Z direction. Fig.10 and Fig.17 As shown in FIG. 1 , an N+ diffusion layer 303 is provided on the front surface of the P-type well region 310. Fig.17 In FIG. 1 , the N+ diffusion layer 303 located on the left side functions as a source region, and the N+ diffusion layer 303 located on the right side functions as a drain region.

[0196] The N+ diffusion layer 303 is a diffusion layer region included in the P-type well region 310 of the semiconductor substrate 200, connected to the through-hole contact electrode CS extending in the Z direction, and contains impurities of the first conductivity type. NL The distance from the channel region to the through-hole contact electrode CS is smaller than the distance from the N-type high voltage transistor Tr NH The distance from the channel region 206 to the through-hole contact electrode CS.

[0197] In addition, the N-type low voltage transistor Tr NL With high voltage transistor Tr NH Different from this, there is no diffusion layer corresponding to the high-concentration N-diffusion layer 202 .

[0198] [P-type low voltage transistor Tr PL Structure of

[0199] Fig.18 Yes means Fig.10 The P-type low voltage transistor Tr shown PL A schematic cross-sectional view of the structure of. Fig.18 As shown, the P-type low voltage transistor Tr PL The N-type well region 311a is provided in the semiconductor substrate 200. The P-type low voltage transistor Tr PL It includes a portion of an N-type well region 311a, a gate insulating film 351 such as silicon oxide (SiO2) disposed on the front surface of the N-type well region 311a (semiconductor substrate 200), a gate electrode component 353 such as polysilicon (Si) disposed on the upper surface of the gate insulating film 351, a gate electrode component 354 such as tungsten (W) disposed on the upper surface of the gate electrode component 353, a covering insulating layer 355 such as silicon oxide (SiO2) or silicon nitride (Si3N4) disposed on the upper surface of the gate electrode component 354, and a sidewall insulating film 356 such as silicon oxide (SiO2) or silicon nitride (Si3N4) disposed on the side surfaces of the gate electrode component 353, the gate electrode component 354, and the covering insulating layer 355 in the X direction or Y direction. In addition, the gate electrode component 353 contains, for example, N-type impurities such as phosphorus (P) or arsenic (As) or P-type impurities such as boron (B). The gate electrode component 353 and the gate electrode component 354 are reference Figure 6 One of the plurality of electrodes gc described above functions as a gate electrode provided on the gate insulating film 351. The gate insulating film 351 is a Figure 6 One of the plurality of insulating layers 200G described in the above description. The P-type low voltage transistor Tr PL The length (thickness) of the gate insulating film 351 in the Z direction is smaller than that of the N-type high voltage transistor Tr NHThe length (thickness) of the gate insulating film in the Z direction can be, for example, greater than or equal to 6 nm and less than or equal to 8 nm.

[0200] P-type low voltage transistor Tr PL It has a liner insulating layer 357 such as silicon oxide (SiO2) and a liner insulating layer 358 such as silicon nitride (Si3N4) stacked on the front surface of the N-type well region 311a, the side surface of the gate insulating film 351 in the X direction or Y direction, the side surface of the sidewall insulating film 356 in the X direction or Y direction, and the upper surface of the covering insulating layer 355.

[0201] In the P-type low voltage transistor Tr PL A through-hole contact electrode CS extending in the Z direction is connected. The through-hole contact electrode CS penetrates the liner insulating layer 357 and the liner insulating layer 358 and is connected to the front surface of the N-type well region 311a, serving as a P-type low voltage transistor Tr PL In addition, the through-hole contact electrode CS not shown in the figure can also penetrate the liner insulating layer 358, the liner insulating layer 357 and the cover insulating layer 355 and be connected to the upper surface of the gate electrode part 354. The through-hole contact electrode CS not shown in the figure serves as a P-type low voltage transistor Tr PL A portion of the gate electrode functions.

[0202] P-type low voltage transistor Tr PL The front surface of the N-type well region 311a has a channel region on the surface opposite to the gate electrode component 353. In other words, the channel region is a region included in the N-type well region 311a of the semiconductor substrate 200 and provided at a position overlapping with the gate electrode when viewed from the Z direction. Fig.10 and Fig.18 As shown in FIG. 1 , a P+ diffusion layer 313 is provided on the front surface of the N-type well region 311a. Fig.18 In FIG. 1 , the P+ diffusion layer 313 located on the left side functions as a source region, and the P+ diffusion layer 313 located on the right side functions as a drain region.

[0203] The P+ diffusion layer 313 is a diffusion layer region included in the N-type well region 311a of the semiconductor substrate 200, connected to the through-hole contact electrode CS extending in the Z direction, and contains impurities of the second conductivity type. PL The distance from the channel region to the through-hole contact electrode CS is smaller than the distance from the N-type high voltage transistor Tr NH The distance from the channel region 206 to the through-hole contact electrode CS.

[0204] In addition, the P-type low voltage transistor Tr PL With high voltage transistor Tr NHDifferent from this, there is no diffusion layer corresponding to the high-concentration N-diffusion layer 202 .

[0205] [Effects of the First Embodiment]

[0206] In reference Fig.12 High voltage transistor Tr NH In the case where the high-concentration N-diffusion layer 202 is not provided, the upper surface side of the low-concentration N-diffusion layer 203 in the Z direction is easily depleted. That is, the liner insulating layer 248 such as silicon nitride (Si3N4) easily captures electrons, and therefore, the liner insulating layer 248 easily captures hot carriers generated by impact ionization to a position overlapping with the high-concentration N-diffusion layer 202 when viewed from the Z direction. Therefore, the position where the low-concentration N-diffusion layer 203 is provided in the front surface of the semiconductor substrate 200 is easily depleted. As a result, the high voltage transistor Tr NH When the high voltage transistor Tr is turned on, NH The current flowing in the device may decrease.

[0207] Therefore, in Fig.12 The high voltage transistor Tr shown in the figure NH If the high-concentration N-diffusion layer 202 is not provided and the impurity concentration of the low-concentration N-diffusion layer 203 is uniformly increased, the withstand voltage will deteriorate when a high voltage is applied to the drain region. Fig.13 To explain more specifically, when the high voltage transistor Tr NH When 0V is applied to the gate electrode and a higher voltage is applied to the drain electrode, the drain region ( Fig.13 A high voltage is applied to the N+ diffusion layer 204 (right side in the figure). At this time, the Y-direction region of the N+ diffusion layer 204 and the low-concentration N- diffusion layer 203 can simulate the series resistance connecting the node n1 and the node n2, and generate a voltage drop. Therefore, the potential of the node n2 when the electron is used as the reference is greater than the potential of the node n1 when the electron is used as the reference. In addition, when the impurity concentration of the low-concentration N- diffusion layer 203 is uniformly increased, the voltage drop at the node n2 will become smaller, and the voltage difference between the source and the drain will be concentrated in the channel region 206. Therefore, the high voltage transistor Tr NH The withstand voltage deteriorates.

[0208] In contrast, for example Fig.13 As shown in the figure, in this embodiment, the high voltage transistor Tr NH In the embodiment, a high concentration N-diffusion layer 202 is provided at the node n1. As a result, the impurity concentration of the low concentration N-diffusion layer 203 is maintained, and the potential at the node n2 is maintained, so that the high voltage transistor Tr can be avoided or suppressed. NH In addition, in the high voltage transistor Tr of this embodiment,NH In the embodiment, the impurity concentration at the node n2 can be increased by providing the high concentration N-diffusion layer 202. Thus, even when hot carriers are trapped in the liner insulating layer 248, etc., the high voltage transistor Tr can be prevented from being damaged. NH When the high voltage transistor Tr is turned on, NH The current flowing in the circuit decreases.

[0209] In addition, the high voltage transistor Tr NH The impact ionization occurs at a position about 250 nm away from the gate electrode 201 (channel region 206) in the channel direction (eg, Y direction). In this embodiment, a high concentration N-diffusion layer 202 is provided in a region including a position about 250 nm away from the gate electrode 201.

[0210] [Variations of the First Embodiment]

[0211] Fig.19 An N-type high voltage transistor Tr is shown as a modified example of the first embodiment. NHA A schematic cross-sectional view of the structure of Fig.12 The same components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0212] like Fig.19 As shown, the N-type high voltage transistor Tr of the modified example of the first embodiment NHA and Fig.12 The N-type high voltage transistor Tr of the first embodiment shown in FIG. NH The difference is that a P-diffusion layer 205 is further provided.

[0213] The P-diffusion layer 205 is provided at a position overlapping with the source region and the drain region when viewed from the Z direction and between the channel region 206 and the insulating region STI, and is a diffusion layer containing P-type impurities such as boron (B).

[0214] The P-diffusion layer 205 can suppress the N-type high voltage transistor Tr of the modified example. NHA N-type high voltage transistor Tr of variation example for suppressing leakage current between source region and drain region NHA leakage current between other adjacent transistors.

[0215] [N-type high voltage transistor Tr of the first embodiment NH etc.]

[0216] Next, refer to Figure 20 to Figure 37 , the N-type high voltage transistor Tr of the first embodiment NH The manufacturing method of the like is described. Figure 20 to Figure 27is a schematic cross-sectional view for explaining the manufacturing method, showing Fig.10 The corresponding cross section. Fig.28 , Fig.30 , Fig.32 , Fig.33 , Fig.35 and Fig.36 is a schematic cross-sectional view for explaining the manufacturing method, showing Fig.12 The corresponding cross section. Fig.29 , Fig.31 and Fig.34 is a schematic top view for explaining the manufacturing method, showing Fig.11 The corresponding plane. Fig.37 is a schematic cross-sectional view for explaining the manufacturing method, showing Fig.17 The corresponding cross section.

[0217] First, if Fig. 20 As shown, P-type impurities such as boron (B) and N-type impurities such as phosphorus (P) are implanted into the front surface of the semiconductor substrate 200 (semiconductor substrate region 200S) to form P-type well regions 310a, 310 and N-type well regions 311a, 311. This step is performed, for example, by ion implantation. Specifically, a resist layer with openings in regions corresponding to the P-type well regions 310a, 310 is formed on the front surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and P-type impurities such as boron (B) are introduced into the semiconductor substrate 200 (semiconductor substrate region 200S) by, for example, ion implantation. After the resist layer with openings in regions corresponding to the P-type well regions 310a, 310 is peeled off, a resist layer with openings in regions corresponding to the N-type well regions 311a, 311 is formed, and N-type impurities such as phosphorus (P) are introduced into the semiconductor substrate 200 (semiconductor substrate region 200S) by, for example, ion implantation. Then, the resist layer opened in the region corresponding to the N-type well regions 311a and 311 is stripped. In this way, the P-type well regions 310a and 310 and the N-type well regions 311a and 311 are formed. NH In order to increase the threshold voltage, P-type or N-type impurities may be introduced into a region corresponding to the channel region 206 in the semiconductor substrate 200 (semiconductor substrate region 200S).

[0218] Then, for example, Fig.21 As shown in FIG. 1 , an insulating film 241a such as silicon oxide is formed on the upper surface of the semiconductor substrate 200. This step is performed by, for example, thermal oxidation. In addition, the insulating film 241a is thinner than the gate insulating film 241 ( Fig.12) is formed with a thin thickness in the Z direction. Next, a portion of the insulating film 241a is removed. This step is performed, for example, by wet etching. In this step, the high voltage transistor Tr NH Tr PH The insulating film 241a remains in the corresponding region, and the low voltage transistor Tr NL Tr PL The insulating film 241a is removed in the corresponding region.

[0219] Then, for example, Fig. 22 As shown in FIG. 1 , an insulating film 341a such as silicon oxide is formed. This step is performed by, for example, thermal oxidation. In addition, the insulating film 341a is formed in a manner similar to the gate insulating film 341 ( Fig.17 ) is formed to have the same thickness in the Z direction as the thickness of the high voltage transistor Tr. NH Tr PH The insulating film 341a becomes thicker in the corresponding region and becomes thicker than the gate insulating film 241 ( Fig.12 ) has the same thickness in the Z direction.

[0220] Then, for example, Fig.23 As shown in FIG. 1 , a conductive layer gcA of polycrystalline silicon (Si) is formed. This step is performed by, for example, CVD (Chemical Vapor Deposition).

[0221] Then, for example, Fig.24 As shown in the figure, in the insulating region STI ( Fig.10 ) is formed at a position corresponding to the insulating region STI. In this step, for example, the conductive layer gcA and the insulating films 241a and 341a at the position corresponding to the insulating region STI are removed, and the semiconductor substrate 200 is anisotropically etched, for example, in the Z direction to a depth of about 0.4 μm. The opening STIA extends in the Z direction and the X direction or the Y direction, penetrates the conductive layer gcA and the insulating films 241a and 341a, and separates a portion of the front surface of the semiconductor substrate 200. This step is performed, for example, by a method such as RIE (Reactive Ion Etching).

[0222] Then, for example, Fig.25 As shown in FIG. 1 , an insulating region STI is formed in the semiconductor substrate 200. This step is performed, for example, by CVD or the like. In this step, the opening STIA is embedded by the insulating layer. Next, a portion of the formed insulating layer is removed, thereby, for example, Fig.25As shown in FIG. 1 , a plurality of insulating regions STI are formed. The step of removing a portion of the formed insulating layer is performed by, for example, CMP (Chemical Mechanical Polishing) or the like.

[0223] Then, for example, Fig.26 As shown, a gate electrode component 243A made of polysilicon (Si), a gate electrode component 244A made of tungsten (W), and a cover insulating layer 245A made of silicon oxide (SiO2) or silicon nitride (Si3N4) are sequentially stacked on the upper surface of the conductive layer gcA. This step is performed by, for example, CVD.

[0224] Then, for example, Fig. 27 As shown in FIG. 1 , in the region other than the region to be the gate electrode, the gate electrode component 243A, the gate electrode component 244A and the covering insulating layer are removed. This step is performed by, for example, RIE or the like. In this way, a high voltage transistor Tr is formed. NH The gate electrode component 243, the gate electrode component 244 and the cover insulating layer 245, the high voltage transistor Tr PH The gate electrode component 253, the gate electrode component 254 and the cover insulating layer 245, the low voltage transistor Tr NL The gate electrode component 343, the gate electrode component 344 and the cover insulating layer 345, and the low voltage transistor Tr PL The gate electrode component 353, the gate electrode component 354 and the covering insulating layer 355.

[0225] Then, for example, Fig.28 and Fig.29 As shown, the high voltage transistor Tr is formed NH The resist layer 245r with corresponding openings is opened, and phosphorus (P) is ion-implanted, for example, to form a low-concentration N-diffusion layer 203. In addition, for example, 5.3×10 12 atoms / cm 2 Phosphorus (P) is ion implanted in an amount of.

[0226] Then, for example, Fig.30 and Fig.31 As shown in FIG. 1 , a resist layer 202r is formed with openings in the regions corresponding to the high concentration N-diffusion layer 202 and the cover insulating layer 245, and phosphorus (P) is ion-implanted, for example. 12 atoms / cm 2 Phosphorus (P) is ion-implanted at a doping amount of 1000 ions. Thus, the region ( Fig.30The total area of ​​the region between the middle resist layer 202r and the cover insulating layer 245 is, for example, 6.3×10 12 atoms / cm 2 Phosphorus (P) is ion-implanted in an amount of 1000 Å, thereby forming a high-concentration N-diffusion layer 202.

[0227] Then, for example, Fig.32 As shown in the figure, after the resist layer 202r is stripped off, silicon oxide (SiO2) or silicon nitride (Si3N4) is deposited on the upper surface of the semiconductor substrate 200, the cover insulating layer 245, and the side surfaces of the gate electrode component 243, the gate electrode component 244 and the cover insulating layer 245 in the X direction or the Y direction, and anisotropic etching is performed to form a sidewall insulating film 246. At this time, the insulating film 241a is removed in the source region and the drain region (active region) at the same time, thereby forming a gate insulating film 241. By removing the insulating film 241a by anisotropic etching, the gate insulating film 241 is formed in a state where it does not protrude from the end of the sidewall insulating film 256 when viewed from the Z direction. As a result, the junction depth of the N+ diffusion layer 204 described below in the Z direction can be made shallower.

[0228] Then, for example, Fig.33 and Fig.34 As shown, a resist layer 204 r is formed with an opening in a region corresponding to the N+ diffusion layer 204 , and arsenic (As) is ion-implanted, for example, to form the N+ diffusion layer 204 .

[0229] Then, for example, Fig.35 As shown in the figure, after the resist layer 204r is peeled off, a liner insulating layer 247 such as silicon oxide (SiO2) is formed on the front surface of the semiconductor substrate 200, the side surface of the gate insulating film 241 in the X direction or the Y direction, the side surface of the sidewall insulating film 246 in the X direction or the Y direction, and the upper surface of the cover insulating layer 245. This step is performed by, for example, CVD.

[0230] Then, for example, Fig.36 As shown in the figure, a high voltage transistor Tr is formed by forming a liner insulating layer 248 such as silicon nitride (Si3N4) and a through hole contact electrode CS. NH .

[0231] In addition, for example, when the formation utilizes Fig.33 and Fig.34 When the resist layer 204r is opened in the region corresponding to the N+ diffusion layer 204, for example, Fig.37 As shown in FIG. 1 , at the same time, the upper surface of the P-type well region 310 when viewed from the Z direction is formed in the same direction as the entire low voltage transistor Tr. NLThe resist layer 303r is opened in the corresponding region. Then, for example, arsenic (As) is ion-implanted, thereby forming the N+ diffusion layer 303.

[0232] N-type low voltage transistor Tr NL By shortening the gate length, the current driving force is increased, thereby improving the speed performance. Therefore, it is important to maintain short channel effect tolerance. If the thickness of the insulating film 341a in the Z direction is large when arsenic (As) is ion-implanted, it is necessary to increase the energy of the ion implantation. In this case, the Z-direction bonding depth of the N+ diffusion layer 303 will become deeper, making the N-type low voltage transistor Tr NL On the other hand, if the insulating film 341a is removed when arsenic (As) is ion-implanted, the energy of ion implantation can be reduced. In this case, the Z-direction bonding depth of the N+ diffusion layer 303 can be made shallower, thereby improving the N-type low voltage transistor Tr. NL Short channel effect tolerance.

[0233] In this embodiment, although not shown in the figure, for example, by using Fig.32 When the sidewall insulating film 346 is formed in the same step as described above, the insulating film 341a is removed by anisotropic etching at the same time, and the gate insulating film 341 is formed in a state where it does not protrude from the end of the sidewall insulating film 346 when viewed from the Z direction. As a result, the bonding depth of the N+ diffusion layer 303 in the Z direction can be made shallow. In other words, it is possible to improve the connection with the N-type high voltage transistor Tr without increasing the number of manufacturing steps. NH The N-type low voltage transistor Tr formed on the same semiconductor substrate 200 NL Short channel effect tolerance.

[0234] In addition, although not shown in the figure, Fig.33 and Fig.34 After forming the N+ diffusion layer 204 and the N+ diffusion layer 303 in the steps shown in the figure, a Fig.16 The P+ diffusion layer 213 and the use of Fig.18 The resist layer with the region corresponding to the P+ diffusion layer 313 is opened, and boron (B) is ion-implanted, for example, thereby simultaneously forming the P+ diffusion layer 213 and the P+ diffusion layer 313. In addition, since the insulating film 341a is removed when the boron (B) is ion-implanted, the energy of the ion implantation can be reduced, so that the junction depth of the P+ diffusion layer 213 and the P+ diffusion layer 313 in the Z direction can be made shallow.

[0235] [N-type high voltage transistor Tr according to a variation of the first embodiment NHA etc.]

[0236] Next, use Fig.38and Fig.39 The N-type high voltage transistor Tr according to the modification of the first embodiment NHA The manufacturing method is described. Fig.38 and Fig.39 The N-type high voltage transistor Tr of the modification example of the first embodiment is used NHA A schematic cross-sectional view illustrating a manufacturing method of Fig.19 The corresponding cross section.

[0237] High voltage transistor Tr NHA Basically, the high voltage transistor Tr NH Likewise manufactured.

[0238] However, it is also possible to use Fig.35 After forming the liner insulating layer 247 as described above, the entire high voltage transistor Tr NH Then, for example, the resist layer 205r may be opened. Fig.38 As shown, the P-diffusion layer 205 is formed by implanting, for example, boron (B) ions into a region deeper than the regions of the high-concentration N-diffusion layer 202 and the low-concentration N-diffusion layer 203 in the Z direction.

[0239] Then, for example, like Fig.39 As shown in the figure, a high voltage transistor Tr is formed by forming a liner insulating layer 248 such as silicon nitride (Si3N4) and a through hole contact electrode CS. NHA .

[0240] In addition, in the use of Fig.30 and Fig.31 When the high concentration N-diffusion layer 202 is formed as described above, the high voltage transistor Tr NH The effective gate length may be reduced. Therefore, for example, it is also possible to use Fig.35 After forming the liner insulating layer 247 as described above, for example, Fig.40 As shown in the figure, a resist layer 205r is formed with an opening in the region corresponding to the high concentration N-diffusion layer 202 and the cover insulating layer 245, and phosphorus (P) is ion-implanted, for example. This can not only suppress the upper side depletion of the high concentration N-diffusion layer 202 in the Z direction due to hot carriers, but also suppress the high voltage transistor Tr NH The effective gate length is reduced.

[0241] [Second embodiment]

[0242] Next, refer to Fig.41 and Fig.42 The N-type high voltage transistor Tr of the second embodiment NH2 Provide explanation. Fig.41The N-type high voltage transistor Tr of the second embodiment is shown. NH2 A schematic cross-sectional view of the structure. Fig.42 The N-type high voltage transistor Tr constituting the second embodiment is shown. NH2 Schematic top view of the well formation region. Fig.12 The same components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0243] Like reference Figure 11 to Figure 14 As described in the above description, the high voltage transistor Tr in the first embodiment NH The N-type high voltage transistor Tr according to the modification of the first embodiment is provided in the semiconductor substrate region 200S. NHA The N-type high voltage transistor Tr is also provided in the semiconductor substrate region 200S. However, this configuration is only an example. NH Or N-type high voltage transistor Tr NHA It may also be provided in a region other than the semiconductor substrate region 200S.

[0244] For example, the peripheral circuit PC of the semiconductor storage device of the second embodiment is basically configured in the same manner as the peripheral circuit PC of the semiconductor storage device of the first embodiment. However, the peripheral circuit PC of the semiconductor storage device of the second embodiment includes a plurality of N-type high voltage transistors Tr NH2 ( Fig.41 ) to replace multiple N-type high voltage transistors Tr NH ( Fig.12 etc.) or N-type high voltage transistor Tr NHA ( Fig.19 wait).

[0245] N-type high voltage transistor Tr according to the second embodiment NH2 ( Fig.41 ) is basically the same as the N-type high voltage transistor Tr of the first embodiment. NH ( Fig.12 etc.) or N-type high voltage transistor Tr NHA ( Fig.19 However, the N-type high voltage transistor Tr of the second embodiment NH2 The high voltage transistor Tr is not provided in the semiconductor substrate region 200S but in the P-type well region 263p. NH2 The P-type well region 263p is electrically separated from the semiconductor substrate region 200S via the N-type well region 274n. Fig.41 and Fig.42 The N-type high voltage transistor Tr of this embodiment is provided NH2 The well region will be described in detail.

[0246] N-type high voltage transistor Tr NH2 The channel region 206, N+ diffusion layer 204, high concentration N- diffusion layer 202 and low concentration N- diffusion layer 203 are arranged in the P-type well region 263p. As described above, the semiconductor substrate 200 (semiconductor substrate region 200S) is provided with an isolation N-type well region 274n for electrically isolating the P-type well region 263p from the semiconductor substrate region 200S. Since the P-type well region 263p is electrically isolated from the semiconductor substrate region 200S, a negative bias can be applied.

[0247] The isolation N-type well region 274n includes three regions, namely, an N-type well region 271n, an N-type well region 272n, and an N-type well region 273n. In addition, in the region surrounded by the isolation N-type well region 274n in the semiconductor substrate 200 (semiconductor substrate region 200S), in addition to the P-type well region 263p, a P-type well region 261p and a P-type well region 262p are also provided.

[0248] The P-type well region 261p is provided below the P-type well region 263p. The P-type well region 262p is provided so as to surround the side surface (XY direction) of the P-type well region 263p when viewed from the Z direction.

[0249] The N-type well region 271n is disposed below the P-type well region 261p. The N-type well region 272n is disposed so as to surround the P-type well region 261p when viewed from the Z direction, and connects the N-type well region 271n and the N-type well region 273n. The N-type well region 273n is disposed so as to surround the P-type well region 262p when viewed from the Z direction.

[0250] Fig.43 It conceptually means along Fig.41 The N-type high voltage transistor Tr of the dotted line BB' NH2 A graph of the impurity concentration in the depth direction (Z direction) of the substrate. Fig.43 The impurity concentrations shown are expressed in Fig.41 The high voltage transistor Tr shown NH2 The impurity concentration when a P-diffusion layer 205 (not shown) is provided.

[0251] like Fig.41 As shown in FIG. 2 , a low-concentration N-diffusion layer 203 is provided on the front surface of the P-type well region 263p, and a P-diffusion layer 205 (not shown) is provided below the low-concentration N-diffusion layer 203. Fig.43 In the example shown, the solid line having a peak near the front surface of the P-type well region 263p represents the impurity concentration of the low-concentration N-diffusion layer 203. The peak value of the impurity concentration is, for example, 3 to 11×10 17 atoms / cm 3In addition, the dotted line having a peak value at a depth of about 0.2 μm from the front surface of the P-type well region 263p represents the impurity concentration of the P-diffusion layer 205. In addition, in a region at a depth of about 0.5 μm to about 1.1 μm from the front surface of the P-type well region 263p, the same as that of the semiconductor substrate region 200S, for example, 10 15 atoms / cm 3 The following P-type impurity concentration.

[0252] exist Fig.43 In the example shown, the impurity concentration of the P-type impurity increases monotonically in a region with a depth of about 1.1 μm to about 1.8 μm from the front surface of the P-type well region 263p, and decreases monotonically in a region with a depth of about 1.8 μm to about 2.4 μm. In addition, the impurity concentration of the N-type impurity increases monotonically in a region with a depth of about 1.4 μm to about 2.4 μm from the front surface of the P-type well region 263p.

[0253] In addition, Fig.43 The impurity concentration distribution except for the impurity concentration of the P-type well region 261p and the N-type well region 271n is similar to that of the N-type high voltage transistor Tr in the variation of the first embodiment. NHA The impurity concentration distribution is the same.

[0254] [Manufacturing method]

[0255] Next, refer to Figures 44 to 49 The N-type high voltage transistor Tr of the second embodiment NH2 The manufacturing method of the like is described.

[0256] First, if Fig.44 As shown, a resist layer 271r having openings in regions corresponding to the P-type well region 261p and the N-type well region 271n is formed on the front surface of the semiconductor substrate 200 (semiconductor substrate region 200S). The N-type well region 271n is formed by, for example, ion implantation of N-type impurities such as phosphorus (P), and then, the P-type well region 261p is formed by, for example, ion implantation of P-type impurities such as boron (B).

[0257] Then, if Fig.45 As shown, a resist layer 272r having an opening in a region corresponding to the N-type well region 272n is formed on the front surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and N-type impurities such as phosphorus (P) are ion-implanted to form the N-type well region 272n.

[0258] Then, if Fig.46As shown, a resist layer 262r having an opening in a region corresponding to the P-type well region 262p is formed on the front surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and P-type impurities such as boron (B) are ion-implanted to form the P-type well region 262p.

[0259] Then, if Fig.47 As shown, a resist layer 273r having an opening in a region corresponding to the N-type well region 273n is formed on the front surface of the semiconductor substrate 200 (semiconductor substrate region 200S), and N-type impurities such as phosphorus (P) are ion-implanted to form the N-type well region 273n. The resist layer 273r is peeled off.

[0260] Then, for example, Fig.48 As shown in FIG. 1 , an insulating film 241a made of silicon oxide or the like is formed on the upper surface of the semiconductor substrate 200. This step is performed by, for example, thermal oxidation or the like.

[0261] Then, for example, Fig.49 As shown in FIG. 1 , an insulating region STI is formed in the semiconductor substrate 200 to form a stacked structure corresponding to the gate electrode. This step is performed, for example, by referring to FIG. Fig.21 Steps to refer to Fig. 27 Then, by executing the reference Fig.28 The high voltage transistor Tr of the second embodiment is manufactured by the steps described above and the steps thereafter. NH2 .

[0262] [Effects of the Second Embodiment, etc.]

[0263] In the N-type high voltage transistor Tr disposed in the P-type well region 263p electrically isolated from the semiconductor substrate 200 NH2 In the absence of the high-concentration N-diffusion layer 202, if the potential of the source region and the drain region is increased relative to the potential of the P-type well region 263p, there is a problem that the current driving force is likely to deteriorate.

[0264] The reason can be considered as follows. That is, the formation of the P-type well region 261p in the semiconductor substrate 200 leads to an increase in the number of P-type impurities contained in the depletion layer when a high potential is given to the source region. Therefore, the reason is that the lower region of the low-concentration N-diffusion layer 203 in the Z direction and the region where the channel region 206 and the low-concentration N-diffusion layer 203 overlap in the Y direction, that is, the overlapping region, are depleted, and the parasitic resistance increases. In particular, the overlapping region is two-dimensionally depleted in the YZ plane, and therefore, the increase in the parasitic resistance of the overlapping region is the main reason for the deterioration of the current driving force.

[0265] In contrast, in this embodiment, the N-type high voltage transistor Tr provided in the P-type well region 263pNH2 Since the high-concentration N-diffusion layer 202 is provided, even if the potential of the source region and the drain region is increased, depletion of the overlapping region can be suppressed, thereby suppressing degradation of the current driving force.

[0266] Furthermore, since the N-type high voltage transistor Tr NH2 Since the high-concentration N-diffusion layer 202 is provided, even if the low-concentration N-diffusion layer 203 is uniformly highly concentrated, degradation of the withstand voltage can be suppressed. NH2 Since the high-concentration N-diffusion layer 202 is provided, it is possible to suppress the situation where the upper region of the low-concentration N-diffusion layer 203 in the Z direction is depleted due to the capture of hot carriers (hot electrons) generated by impact ionization, as in the first embodiment. NH2 Not only is the degradation of withstand voltage alleviated, but also the increase in resistance caused by the formation of a depletion layer by trapped hot carriers (hot electrons) is alleviated.

[0267] [Other embodiments]

[0268] In the above embodiments, the technology applicable to NAND (Not AND) flash memory is described. However, the technology described in this specification can also be applied to structures other than semiconductor storage devices, such as three-dimensional NOR (Not OR) flash memory. In addition, the technology described in this specification can also be applied to the structure of semiconductor devices other than semiconductor storage devices.

[0269] [other]

[0270] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments or their variations are included in the scope or spirit of the invention and are included in the invention described in the claims and their equivalents.

[0271] [Explanation of Symbols]

[0272] 200:Semiconductor substrate

[0273] 200N, 271n, 272n, 273n, 311, 311a: N-type well area

[0274] 200P, 261p, 262p, 263p, 310, 310a: P-type well area

[0275] 200S: semiconductor substrate area

[0276] 201: Gate electrode

[0277] 202: High concentration N-diffusion layer

[0278] 203: Low concentration N-diffusion layer

[0279] 204,303:N+ diffusion layer

[0280] 205:P-diffusion layer

[0281] 206: Channel area

[0282] 213,313:P+ diffusion layer

[0283] 241a,341a: Insulation film

[0284] 246,256,346,356: Side wall insulation film

[0285] 247,248,257,258,347,348,357,358: liner insulation layer

[0286] 274n: N-type well area for isolation

[0287] 303: N+ diffusion layer

[0288] CC: Through-hole contact electrode

[0289] CS: through-hole contact electrode.

Claims

1. A semiconductor storage device comprising: Semiconductor substrates; and A plurality of transistors are arranged on the semiconductor substrate; A first transistor among the plurality of transistors comprises: A first gate insulating film is provided on the semiconductor substrate; a first gate electrode, disposed on the first gate insulating film; A sidewall insulating film is provided on both sides of the first gate electrode; a first region included in the semiconductor substrate and provided at a position overlapping with the first gate electrode when viewed from a first direction intersecting the surface of the semiconductor substrate; a first diffusion layer included in the semiconductor substrate, connected to a first contact electrode extending in the first direction, and containing impurities of a first conductivity type; a second diffusion layer included in the semiconductor substrate, provided between the first region and the first diffusion layer, and containing impurities of the first conductivity type; and a third diffusion layer included in the semiconductor substrate, provided between the second diffusion layer and the first diffusion layer, connected to the second diffusion layer, and containing impurities of the first conductivity type; and The concentration of the first conductivity type impurity in the second diffusion layer is higher than the concentration of the first conductivity type impurity in the third diffusion layer.

2. The semiconductor memory device according to claim 1, wherein The first transistor is an N-channel transistor.

3. The semiconductor memory device according to claim 1, wherein The first conductivity type impurity is an N-type impurity.

4. The semiconductor memory device according to claim 1, wherein At least a portion of the second diffusion layer is provided at a position overlapping with the sidewall insulating film when viewed from the first direction.

5. The semiconductor memory device according to claim 1, wherein The concentration of the first conductivity type impurity in the second diffusion layer is less than 10 times the concentration of the first conductivity type impurity in the third diffusion layer.

6. The semiconductor memory device according to claim 1, wherein The concentration of the first conductivity type impurity in the first diffusion layer is 10 times or more the concentration of the first conductivity type impurity in the second diffusion layer.

7. The semiconductor memory device according to claim 1, comprising: a first insulating layer provided on both side surfaces of the first gate electrode via the sidewall insulating film and containing silicon (Si) and oxygen (O); and The second insulating layer is provided on both side surfaces of the first gate electrode via the first insulating layer, and contains silicon (Si) and nitrogen (N).

8. The semiconductor memory device according to claim 1, comprising a fourth diffusion layer, The fourth diffusion layer is included in the semiconductor substrate, is arranged at a position overlapping with the third diffusion layer when viewed from the first direction, is located on the opposite side of the first gate electrode in the first direction relative to the third diffusion layer, and contains impurities of a second conductivity type different from the first conductivity type.

9. The semiconductor memory device according to claim 1, wherein The semiconductor substrate includes impurities of a second conductivity type different from the first conductivity type, and comprises: a first well containing impurities of the second conductivity type; and a second well disposed so as to surround the first well when viewed from the first direction and containing impurities of the first conductivity type; and The first region, the first diffusion layer, the second diffusion layer, and the third diffusion layer are provided in the first well.

10. The semiconductor memory device according to claim 1, wherein A voltage greater than 10 V is supplied to the first transistor.

11. The semiconductor memory device according to claim 1, wherein A second transistor among the plurality of transistors comprises: a second gate insulating film provided on the semiconductor substrate; and a second gate electrode disposed on the second gate insulating film; and A length of the first gate insulating film in the first direction is greater than a length of the second gate insulating film in the first direction.

12. The semiconductor memory device according to claim 1, wherein A second transistor among the plurality of transistors comprises: A second gate insulating film is provided on the semiconductor substrate; a second gate electrode disposed on the second gate insulating film; a second region included in the semiconductor substrate and overlapping with the second gate electrode when viewed from the first direction; and a fifth diffusion layer included in the semiconductor substrate, connected to the second contact electrode extending in the first direction, and containing impurities of the first conductivity type; and A distance from the first region to the first contact electrode is greater than a distance from the second region to the second contact electrode.

13. The semiconductor memory device according to claim 1, comprising: A plurality of conductive layers are arranged along the first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; a charge storage film disposed between the plurality of conductive layers and the semiconductor layer; and a current generating circuit electrically connected to the plurality of conductive layers; and The first transistor is provided in a current path between the plurality of conductive layers and the current generating circuit.

14. A semiconductor storage device comprising: Semiconductor substrates; and A plurality of transistors are arranged on the semiconductor substrate; A first transistor among the plurality of transistors comprises: A first gate insulating film is provided on the semiconductor substrate; a first gate electrode, disposed on the first gate insulating film; A sidewall insulating film is provided on both sides of the first gate electrode; a first region included in the semiconductor substrate and provided at a position overlapping with the first gate electrode when viewed from a first direction intersecting the surface of the semiconductor substrate; a diffusion layer included in the semiconductor substrate, provided at a position overlapping with the sidewall insulating film when viewed from the first direction, and containing impurities of the first conductivity type; and another diffusion layer, which is provided on the opposite side of the first region in a second direction intersecting the first direction with respect to the first diffusion layer, is connected to the first diffusion layer, and contains impurities of the first conductivity type; and The concentration of the first conductivity type impurity in the one diffusion layer is higher than the concentration of the first conductivity type impurity in the other diffusion layer.

15. The semiconductor memory device according to claim 14, wherein The first transistor is an N-channel transistor.

16. The semiconductor memory device according to claim 14, wherein The first conductivity type impurity is an N-type impurity.

17. The semiconductor memory device according to claim 14, wherein The concentration of the first conductivity type impurity in the one diffusion layer is less than 10 times the concentration of the first conductivity type impurity in the other diffusion layer.

18. The semiconductor memory device according to claim 14, comprising: a first insulating layer provided on both side surfaces of the first gate electrode via the sidewall insulating film and containing silicon (Si) and oxygen (O); and The second insulating layer is provided on both side surfaces of the first gate electrode via the first insulating layer, and contains silicon (Si) and nitrogen (N).

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