Tool for supporting use of regulative network topologies

Abstract

A tool for using custom sub-network descriptions during the generation and synthesis of a network, such as a network-on-chip (NoC). The tool allows for incremental synthesis and conversion of deadlock-free NoCs. The NoC topology is converted into an existing segment; existing segments are reused in a new route and a deadlock-free NoC topology is generated. The tools include a machine learning model trained for synthesis and generation of NoC and capable of providing incremental synthesis. The model can also receive past or previously synthesized feedback for further training of the model.

Description

Technical Field

[0001] The present invention belongs to the field of system design, and more particularly, to topology generation of a network on chip (NoC). Background Art

[0002] Multiprocessor systems have been implemented in systems on chips (SoCs) that communicate through networks on chips (NoCs). NoCs are examples of scalable communication architectures for designing SoCs. It is more desirable to eliminate conditions that lead to deadlocks in the network when using NoCs in designing applications. It is currently known to route messages through arrays of data processing nodes to facilitate multiple paths to a destination without messages being delayed due to routing deadlocks. When designing an application-specific NoC, an important aspect is more desirable deadlock-free operation with minimal power and area overhead. There are two main types of deadlocks that are known to occur in NoCs. The first type of deadlock is a routing-related deadlock. The second type of deadlock is a message-related deadlock.

[0003] The SoC includes an initiator intellectual property (IP) and a target IP. Transactions in the form of data packets are sent from a master to one or more slaves using industry standard protocols. A master connected to the NoC sends a request transaction to a slave using the address of the selected slave. The NoC decodes the address and transmits the request from the master to the slave. The slave processes the transaction and sends a response transaction, which is transmitted back to the master through the NoC.

[0004] For a given set of performance requirements, such as connectivity and latency between sources and destinations, frequencies of various components, maximum area available for NoC logic, minimum throughput between sources and destinations, and locations of components attached to the NoC on a floor plan, creating an optimal NoC that meets all requirements with a minimum amount of logic and wires is a complex task. Creating an optimal NoC is typically the job of a chip architect or chip designer, and it is a difficult and time-consuming task. Not only is this a difficult task, but the design of the NoC is also modified every time the requirements change, such as a modification of the chip floor plan or a modification of the expected performance. Therefore, this task needs to be frequently redone during the design time of the chip. This process is time-consuming, which can lead to production delays. Therefore, systems and methods are needed to efficiently generate a NoC from a set of constraints (which are listed as requirements) and a set of inputs. The system needs to generate a NoC in which all components are placed on the floor plan of the chip.

[0005] When performing NoC synthesis, there is currently a problem of supporting conventional network topologies, especially when introducing new connections in an existing NoC. Therefore, there is a need to be able to support conventional network topologies while allowing synthesis of NoC topologies to avoid both routing-related and message-related deadlocks and to integrate with the topology synthesis phase of the NoC design flow. Considering the deadlock avoidance problem during topology synthesis, a more desirable NoC design can be achieved compared to traditional approaches, where the deadlock avoidance problem is managed separately. Furthermore, there is a need to add new connections without overwriting previous results. Summary of the invention

[0006] According to various embodiments and aspects of the present invention, a tool is disclosed that uses a set of constraints and a set of steps with inputs to generate a network on chip (NoC) to generate or generate a NoC with all its elements while supporting conventional network topologies. The elements of the NoC are placed on a floor plan of the chip. The advantage of the present invention is that the design process and the work of chip architects or designers are simplified. The NoC generation or synthesis method has an incremental design, whereby the NoC is generated or synthesized one connection at a time. In particular, a set of nodes of a source-destination pair and each new connection are synthesized by treating a set of existing connections as input. When synthesizing a new connection to define a network route from a source to a destination, a new component including but not limited to a switch and / or a link can be generated. Within the scope of the present invention, the destination includes but is not limited to a list of components to be traversed. In addition, when synthesizing a new connection, configuring the newly created component including but not limited to clock and / or data width is an important aspect.

[0007] According to various embodiments and aspects of the present invention, the tool is able to reuse existing fragments of the generated topology, even though the topology may be highly irregular and tree-like. Therefore, in some designs, such as for a subsystem of a design with complex connectivity, it is preferable to choose a known conventional topology, such as a mesh network, because it is simple and efficient in terms of implementation cost and bandwidth distribution. Therefore, the tool can take advantage of the common form and add seamless support for conventional topologies.

[0008] In an embodiment, the set of existing connections may be empty. Thus, the NoC will be synthesized from the beginning of the process without existing connections.

[0009] The order in which the connections are implemented affects the quality of the topology. In an embodiment, the order may be determined based on a number of mathematical optimization techniques and / or heuristics. For example, the order may be determined by the area of ​​the floor plan spanned by the connections. In another example, the order may be a latency-based communication strategy that is configured to measure the delay for packets to reach the destination and implement more sensitive connections with higher priority. Within the scope of the present invention, the synthesis order is an input to a method for deterministic and incremental physical-aware NoC topology synthesis.

[0010] A system configured to automatically generate or synthesize a deadlock-free NoC from a specification includes: a floor plan, which is the physical layout of a chip; technical parameters, including but not limited to line delays and / or logic density; floor plan areas, including but not limited to module and / or clock constraints; clock domain crossing (CDC), which is the traversal of a signal in a synchronous digital circuit from a first clock domain to a second clock domain; performance requirements; and components, which have a configuration and location on the floor plan, connectivity requirements between the first component and the second component, and a communication strategy between the first component and the second component.

[0011] A method of transforming an existing deadlock-free network-on-chip (NoC) configuration, the existing deadlock-free network-on-chip configuration comprising a plurality of existing physical segments and a set of existing turns allowed between the segments, the plurality of existing physical segments and the set of existing turns forming a plurality of existing routes. The method comprises generating a new NoC configuration by generating and / or synthesizing at least a first new connection into the existing deadlock-free network-on-chip configuration, the first new connection having a source and a destination, the generating creating a first new deadlock-free route from the source to the destination, whereby the new network-on-chip configuration is deadlock-free, and wherein generating the first new deadlock-free route from the source to the destination maintains the existing route.

[0012] The generating includes: for each existing route, converting the route into segments and turns; identifying one or more new connections to be synthesized, each of the plurality of new connections having an undefined route, a source, and a destination associated therewith, the one or more new connections being identified along with a synthesis order; for each of the one or more new connections and in accordance with the ordering, identifying a plurality of possible routes for the new connection from the source to the destination.

[0013] Possible routes include one or more of the following: a new entry fragment connecting the source to an existing deadlock-free NoC configuration; a new exit fragment connecting the existing deadlock-free on-chip network configuration to the destination; one or more new internal fragments connecting existing fragments of the existing deadlock-free on-chip network configuration, whereby the one or more new internal fragments connect the source to the destination, wherein if the new internal fragment would create a circular dependency among the fragments, thereby causing a deadlock, then the new internal fragment is not considered; and existing fragments alone.

[0014] A plurality of possible routes are filtered based on one or more criteria, including: a communication policy criterion based on an allowed latency for a route from a source to a newly connected destination; any of a plurality of user-defined criteria; selecting one of a plurality of possible routes for synthesis; and / or synthesizing the selected possible route into an existing deadlock-free on-chip network configuration.

[0015] According to one or more embodiments of the present invention, the first new deadlock-free route includes at least one of an existing physical segment and a new physical segment.

[0016] According to one or more embodiments of the invention, a first new deadlock-free route is generated from a source to a destination maintaining all existing routes.

[0017] According to one or more embodiments of the present invention, the generation of new deadlock-free routes is repeated step by step.

[0018] According to one or more embodiments of the invention, identifying the composition order includes ordering the one or more new connections according to a heuristic.

[0019] According to one or more embodiments of the invention, at least a portion of an existing segment is physically immutable.

[0020] According to one or more embodiments of the present invention, the endpoints of at least a portion of the existing segments are switches. The switches are physically immutable.

[0021] According to one or more embodiments of the invention, any component is logically changeable such that at least one existing component is reconfigured in response to a new resulting topology.

[0022] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes usage of an existing deadlock-free network-on-chip configuration, wherein the existing segments are manufactured to be physically immutable except for an ingress segment and an egress segment, the switches are manufactured to be physically immutable, and at least one network element is manufactured to be logically immutable.

[0023] According to one or more embodiments of the invention, selecting one of the plurality of possible routes for synthesis includes selecting a possible route that minimizes a latency of the route.

[0024] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes selecting a possible route that maximizes usage of an existing deadlock-free on-chip network configuration, where existing segments are not made physically immutable, switches are allowed to have new connections, and existing network elements are made logically immutable, which includes keeping clock frequency and other properties unchanged.

[0025] According to one or more embodiments of the invention, selecting one of a plurality of possible routes for synthesis includes making the selection while existing segments are not made physically immutable, switches are allowed to have new connections, and existing network elements are reconfigurable.

[0026] A method for incremental synthesis and transformation of a deadlock-free on-chip network topology includes receiving an input as a network topology. The network topology is converted into an existing segment; reusing the existing segment in a new route, the existing segment being formed by a path between a first node and a second node; recursively splitting the existing segment at any geographic point along the path between the first node and the second node to form a split segment; synthesizing a new route by adding the new segment and a new turn to the split segment in response to the split; and generating a deadlock-free on-chip network topology by routing packets from turns of the existing segment to the new segment to avoid deadlocks in the network.

[0027] According to one or more embodiments of the invention, identifying the composition order includes ordering the one or more new connections according to a heuristic.

[0028] According to one or more embodiments of the invention, at least a portion of an existing segment is physically immutable.

[0029] According to one or more embodiments of the present invention, the endpoints of at least a portion of the existing segments are switches. The switches are physically immutable.

[0030] According to one or more embodiments of the invention, any component is logically changeable such that at least one existing component is reconfigured in response to a new resulting topology.

[0031] A non-transitory computer-readable medium for storing code, which, when executed by one or more processors, causes the processors to: receive an input topology of a network on chip (NoC) to determine a source-destination pair to be selected for synthesis and at least one existing connection; transcribe the source-destination pair into a pair of segments; transcribe at least one existing connection into a pair of existing segments; determine whether the NoC is deadlock-free; in response to determining whether the NoC is deadlock-free, extract the pair of segments that do not have a defined route and order them using a heuristic method; input the pair of segments and the pair of existing segments into a configuration resource manager, the configuration resource manager using a communication A communication strategy is used to determine a configuration for routing from a source of a source-destination pair to a destination, the communication strategy is configured to receive user-defined parameters associated with the source-destination pair, the communication strategy is in communication with a configuration filtering module, and the configuration filtering module is configured to output qualified configurations; using a configuration selection module to select a final configuration to be implemented for connecting the source-destination pair; separating the pair of existing segments that need to be connected to the pair of segments at a point specified by the final configuration; creating a new segment specified by the final configuration; activating a corresponding turn connecting the pair of existing segments with the pair of segments; and calculating a route from the source of the source-destination pair to the destination. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1A Shows a logical view of a Network on Chip (NoC), which includes the various elements that make up the NoC;

[0033] Figure 1B showing a NoC with components placed on a floor plan of the network;

[0034] Figure 2A A method for generating a NoC description based on a set of constraints according to various aspects and embodiments of the present invention is presented;

[0035] Figure 2B A block diagram showing a NoC synthesis tool according to various aspects and embodiments of the present invention;

[0036] Figure 3 a diagrammatic view showing a floor plan of a chip with blocked areas and locations of interfaces to a NoC according to various aspects and embodiments of the present invention;

[0037] Figure 4 A connectivity table showing a NoC according to various aspects and embodiments of the present invention;

[0038] Figure 5 presenting a scenario table with throughput definitions for read and write transactions according to various aspects and embodiments of the present invention;

[0039] Figure 6 Demonstrating the creation of a network with three traffic classes according to various aspects and embodiments of the present invention;

[0040] Figure 7 A schematic diagram showing a device having a combiner and a splitter according to various aspects and embodiments of the present invention. Figure 6 Decomposition of the network;

[0041] Figure 8 Demonstrate various aspects and embodiments of the present invention for Figure 6 A route map of a floor plan of a master control device of a network;

[0042] Fig. 9 Demonstrate various aspects and embodiments of the present invention for Figure 6 A route map of a floor plan of a slave device of a network;

[0043] Fig.10 The main node splitter is decomposed into Figure 8 A route map of physically distributed cascades of separators;

[0044] Fig.11 The main node merger is decomposed into Fig. 9 A cascade of physically distributed combiners;

[0045] Fig.12 An example showing two nodes being shut down and merged according to various aspects and embodiments of the present invention;

[0046] Fig.13 Shown is a NoC topology above a floorplan with deadlock-free segments and turn networks according to various aspects and embodiments of the present invention;

[0047] Fig.14A Shown is a NoC topology above a floorplan with separated segments S to D according to various aspects and embodiments of the present invention;

[0048] Fig. 14B Showing the NoC topology above the floorplan with the split segment S to D updated to use two new sub-segments S to N and N to D according to various aspects and embodiments of the present invention;

[0049] Fig. 14C Shown is a NoC topology above a floorplan with sub-segments N and S merged into separate segments according to various aspects and embodiments of the present invention;

[0050] Fig.14DShown is a NoC topology above a floorplan with sub-segments represented by channels between nodes N and S bifurcating into separate segments according to various aspects and embodiments of the present invention;

[0051] Fig.15 is a flow chart illustrating a method for single connection NoC topology synthesis processing according to various aspects and embodiments of the present invention;

[0052] Fig.16A Shown is a NoC topology above a floorplan with a request to connect node S to node D according to various aspects and embodiments of the present invention;

[0053] Fig. 16B shows a NoC topology above a floorplan with incremental synthesis results of a routing configuration from S to D with a new ingress segment, a new internal segment, and an existing egress segment according to various aspects and embodiments of the present invention;

[0054] Fig.17A Shown is a NoC topology above a floorplan with a communication strategy 1700 to optimize wire length on a best effort basis, according to various aspects and embodiments of the present invention;

[0055] Fig. 17B Shown is a NoC topology above a floorplan with a communication strategy 1710 being low-latency communication according to various aspects and embodiments of the present invention;

[0056] Fig.18A shows an incremental composition mode 1800 for an initial setup of a segment connecting from node S to node D according to various aspects and embodiments of the present invention;

[0057] Fig.18B An incremental synthesis mode 1810 is shown for physical invariance of segments with minimally varying parameters in accordance with various aspects and embodiments of the present invention;

[0058] Fig. 18C shows an incremental synthesis mode 1820 for logical invariance of fragments with optimized topology and preserved configured parameters according to various aspects and embodiments of the present invention;

[0059] Fig.18D An incremental synthesis mode 1830 illustrating variability for network elements with optimized topology and adapted configured parameters according to various aspects and embodiments of the present invention; and

[0060] Fig.19 The process of NoC synthesis based on mesh custom subnetwork description according to various aspects and embodiments of the present invention is shown.

[0061] Fig. 20A A floor plan is shown in which a tool may use a custom subnetwork description according to various aspects and embodiments of the present invention.

[0062] Fig. 20B Demonstrating the use of custom subnetwork descriptions according to various aspects and embodiments of the present invention Fig. 20A Floor plan of the building.

[0063] Fig.21 A process of incremental generation and synthesis of NoCs using custom subnetwork descriptions according to various aspects and embodiments of the present invention is shown. DETAILED DESCRIPTION

[0064] Various examples of the present invention technology illustrating various aspects and embodiments of the present invention are described below. In general, examples can use the described aspects in any combination. All statements of narration principles, aspects and embodiments and their specific examples herein are intended to cover both their structural and functional equivalents. In addition, it is hoped that such equivalents include both currently known equivalents and equivalents developed in the future, that is, any element that performs the same function developed, without considering structure.

[0065] It should be noted that as used herein, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. References throughout this specification to "one aspect," "an aspect," "certain aspects," "various aspects," or similar language mean that a particular aspect, feature, structure, or characteristic described in connection with any embodiment is included in at least one embodiment of the present invention.

[0066] The appearance of the phrases "according to one or more embodiments," "in one embodiment," "in at least one embodiment," "in embodiments," "in certain embodiments," and similar language throughout this specification may, but do not necessarily, refer to the same embodiment or similar embodiments. In addition, the aspects and embodiments of the invention described herein are merely exemplary and should not be construed as limiting the scope or spirit of the invention as understood by those of ordinary skill in the art. The disclosed invention is effectively made or used in any embodiment that includes any novel aspect described herein. All statements describing the principles, aspects, and embodiments of the invention herein are intended to cover both structural and functional equivalents thereof. It is intended that such equivalents include both currently known equivalents and equivalents developed in the future.

[0067] As used herein, "master" and "initiator" refer to similar intellectual property (IP) modules or units, and these terms can be used interchangeably within the scope and embodiments of the present invention. As used herein, "slave" and "target" refer to similar IP modules or units, and these terms can be used interchangeably within the scope and embodiments of the present invention. As used herein, a transaction can be a request transaction or a response transaction. Examples of request transactions include write requests and read requests.

[0068] As used herein, a node is defined as a distribution point and / or communication endpoint capable of creating, receiving and / or transmitting information on a communication path or channel. A node may refer to any of the following: a switch, a splitter, a combiner, a buffer, and an adapter. As used herein, splitters and combiners are switches; not all switches are splitters or combiners. As used herein and in accordance with various aspects and embodiments of the present invention, the term "splitter" describes a switch having a single ingress port and multiple egress ports. As used herein and in accordance with various aspects and embodiments of the present invention, the term "combiner" describes a switch having a single egress port and multiple ingress ports.

[0069] Reference now Figure 1A , a network on chip (NoC) 100 is shown according to various aspects and embodiments of the present invention. NoC 100 is an example of a network. According to various aspects and embodiments of the present invention, the network includes a set of nodes and a set of edges, each of which has a model and can be used at the core of the synthesis to perform and implement transformations through the network and converge to an optimal solution that meets specified requirements. NoC 100 includes nodes and endpoints and uses assembled basic network functions, such as: network interface units (NIUs) 102, 104, 106, 108, 110, 112, 130, 132 and 134; nodes / switches 114, 116, 118, 120 and 122; adapters, such as adapter 126; and buffers, such as buffer 124. NoC basic network functions typically use an internal transmission protocol specific to NoC 100 to communicate with each other based on the transmission of data packets. NIU converts the protocol used by the attached system on chip (SoC) unit (not shown) to the transmission protocol used inside NoC 100. Switches route traffic flows between sources and destinations. Buffers 124 are used to insert pipeline elements to span long distances, or to store data packets to handle rate adaptation between fast senders and slow receivers, or vice versa. Adapters 126 handle various conversions between data width, clock, and power domains.

[0070] Reference now Figure 1B, NoC 150 is shown in a floor plan with various elements, such as NIUs, switches, and blocking areas. NoC 150 includes various connectivity elements through various switches. According to one aspect of the invention, a set of constraints is used as input to the tool, which is discussed in more detail below. According to some aspects of the invention, the tool performs a set of sub-steps and generates a description (synthesis) of the resulting NoC (e.g., NoC 150) having its configured elements and the location of each element on the floor plan. The generated description is used to provide guidance to the back-end implementation process using the generated physical information to actually implement the NoC hardware.

[0071] Reference now Figure 2A According to some aspects of the present invention, a set of constraints (210, 212, 214, 216 and scenarios) are provided to a synthesis tool 220. According to some embodiments and aspects of the present invention, the performance and functionality of tool 220 may include third-party ASIC implementation tools, such as logic synthesis, placement and routing back-end tools, etc. According to some aspects and embodiments of the present invention, tool 220 includes a machine learning model to help design and automate the synthesis or generation process. A designer or user builds a set of constraints that are provided to tool 220. The constraints are captured in a machine-readable form, such as a computer file that captures information in a defined format that is understood and processed by the tool. According to one aspect of the present invention, the format is XML. According to another aspect of the present invention, the format is JSON. The scope of the present invention is not limited by the specific format used.

[0072] Reference now Figure 2B , the tool reads a file containing a description of the constraints and performs the synthesis process. According to some aspects of the invention, the synthesis process is broken down into multiple steps. Sequencer 250 is responsible for executing each step of the process. According to some aspects of the invention, a set of steps is executed by sequencer 250 of tool 220 according to the constraints formulated by the user / designer. The scope of the invention is not limited by the number and type of steps that sequencer 250 can call and execute.

[0073] Reference again Figure 2A Together with Figure 2BAccording to various aspects of the invention, a designer of a network provides and defines a set of constraints, such as constraints 210, 212, 214, and 216. Sequencer 250 receives various inputs, including: input 251, which includes a global integrated roadmap with connectivity between initiators and targets, including roadmap creation and information between each master and slave; input 252, which includes service classification and master switch creation; input 254, which includes decomposing the master switch into mergers and splitters; input 258, which includes information about the physical distribution of splitters and mergers in the roadmap; input 259, which includes information about edge clusters; and input 260, which includes information about performance-aware node clusters. According to one aspect of the invention, sequencer 250 also receives input 262, which includes information about optimization and network reconstruction. According to one aspect of the invention, sequencer 250 receives 264, which includes information about routing and legalization. According to various aspects and embodiments of the invention, sequencer 250 uses all of inputs 251 to 264 to generate a network. According to various aspects and embodiments of the present invention, sequencer 250 uses a combination of inputs 251 to 264 to generate a network.

[0074] According to various aspects of the invention, input 251 includes input regarding a global integration roadmap. The global integration roadmap includes an integration model that captures the connectivity of the free space of the floor plan and a global physical view of the connectivity across / between initiators and targets. The global integration roadmap is modeled by a graph of physical nodes and specification fragments for locating nodes (splitters, mergers, switches, adapters) of the network under construction. The global integration roadmap is used to accelerate computation. According to various aspects of the invention, the global integration roadmap is persistent, meaning that it is data that the system exports and re-consumes in incremental synthesis and subsequent runs.

[0075] According to some aspects of the invention, input 259 contains information about edge clusters. Edge clusters are intended to minimize resources and enhance performance goals through appropriate algorithms and techniques. According to some aspects of the invention, edge clusters are combined and applied in conjunction with input 260, i.e., node clusters. Edge clusters and node clusters can be used in combination by mixing, by simultaneous application, or by sequential application. The advantages and goals are to expand the scope of synthesis and provide a larger solution space for the network.

[0076] According to various aspects of the invention, input 262 includes information about the reconstruction. Reconstruction includes a variety of transformations and capabilities. According to some aspects of the invention, the transformation is logical because the structure of the network has changed. According to some aspects of the invention, the transformation is physical because there are physical changes in the network, such as moving a node to a new location. Other examples of reconstruction include: splitting a node into smaller nodes; reordering roots between nodes; duplicating subsections of the network to avoid deadlock and handle congestion; and physically rerouting links to avoid congested areas or to meet timing constraints.

[0077] Reference now Figure 3 , according to various aspects of the invention, a floor plan 300 of a chip on which a NoC is implemented is shown, with locations for various initiator interfaces and target interfaces. Physical constraints 210 provide physical information about the design, including: the size of the chip on which the NoC will be implemented; various congestion areas on the floor plan, which are rectangles representing areas of the chip on which NoC logic cannot exist or be placed; free space, which is an area of ​​the chip in which NoC logic can exist and is defined by the area not covered by congestion; and the locations of interfaces between SoC units and the NoC, which are the locations of initiator interfaces and target interfaces, such as NIUs.

[0078] According to various aspects of the invention, another constraint includes an extension of a clock domain, and a power domain constraint 212 may also be provided. A domain constraint 212 includes areas of the chip where logic belonging to a particular domain is allowed to be placed.

[0079] According to various aspects of the present invention, the capabilities of a logic library to be used to implement a NoC are provided. The information includes the size of a reference logic gate, and the time it takes for a signal to cover a distance of 1 mm.

[0080] Reference again Figure 2A According to various aspects of the invention, a SoC includes multiple clock domains and multiple power domains. A clock domain is defined by all logic fed by a given clock input. The clock input is characterized by the frequency of the clock, which is its most important parameter. A power domain is defined by all logic that obtains power supply from the same power supply. According to various aspects of the invention, the power supply is gated, so a power domain can be turned on or off or isolated from other power domains. Thus, the designer provides a set of clock domain and power domain constraints 212 as part of the initial design.

[0081] According to various aspects of the present invention, initiators and targets are connected to the NoC in a communicative manner. An initiator is a unit that sends requests (usually read and write commands). A target is a unit that serves or responds to requests (usually read and write commands). Each initiator is attached to or connected to the NoC through an NIU. The NIU attached to the initiator is called an initiator network interface unit (INIU). In addition, each target is attached to the NoC through an NIU. The NIU attached to the target is called a target network interface unit (TNIU). The main functionality of the NoC is to carry each request from the initiator to the desired destination target, and if the request requires or requires a response, the NoC carries the response of each target to the corresponding request initiator. The initiator and the target have many different parameters that characterize them. According to various aspects of the present invention, for each initiator and target, the clock domain and power domain to which it belongs are defined. The width of the data bus used to send write and receive read payloads is multiple bits. According to various aspects of the present invention, the width of the data bus used to send write requests and receive write responses (communication path with the target) is also defined. Additionally, the clock and power domain definitions are references to previously described clock and power domains present in a SoC, as described herein.

[0082] continue Figure 2A and Figure 2B Also refer to Figure 4 , showing a connectivity table 400. According to various aspects of the present invention, table 400 allows for limiting services by classification. The tool permits the use of service class tags for each connection between an initiator and a target. As shown in table 400, there are three service classes: L1, L2, and L3. Service class tags are arbitrary tags selected by a user or designer. Any number of tags may be defined, and the scope of the present invention is not limited by the number of tags. Each tag represents a need for independent network resources. The present invention will assign different subnetworks to each tag, which may be physically different or may use virtual networks (if supported by the underlying NoC technology).

[0083] According to various aspects of the present invention, it is not necessary for the initiator to be able to send requests to all targets or slaves connected to the NoC. The precise definition of the targets that can receive requests from the initiator is summarized or set forth in a connectivity table such as table 400. Connectivity and service class tag information can be represented as a matrix. Each master has a row and each slave has a column. If the master must be able to send services to the slave, the service class tag must be present at the intersection between the master row and the slave column. If there is no tag at the intersection, the tool does not require connectivity between the master and the slave. For example, master 1 (M1) communicates with slave 1 (S1) connectivity using a defined tag 1 (L1), while M1 does not communicate with S2, and therefore there is no tag at the intersection of M1 and S2. According to various aspects of the present invention, the actual format used to represent connectivity can be different, as long as each pair of master-slave combinations has a precise definition of its service class, or if there is no connection, there is no classification tag.

[0084] Reference now Figure 5 , according to various aspects of the present invention, a table 500 is shown, which includes various scenarios (shown in Figure 2A ) for read (RD) and write (WR) transactions. Table 500 contains information defining various throughput rates provided to the tool. A scenario defines the expected performance in terms of data throughput between a master device and a slave device. Each scenario describes the expected required read bandwidth and the expected required write bandwidth between each initiator and each target. Throughput is defined in bytes per second (B / s). A typical SoC will have multiple operating modes. As an example, a SoC for a smartphone may have a gaming operating mode, an audio call operating mode, an idle operating mode, and so on. These define scenarios that depend on different throughput rates. Therefore, a set of scenarios represents different operating modes supported by the SoC, and accordingly represents the expected NoC minimum performance in terms of throughput between the master device and the slave device.

[0085] The scenario can be represented as 2 matrices, one defining the read throughput and one defining the write throughput. According to various aspects of the invention, the read throughput requirement will be used to set the size of the response network, which handles the data returned from the slave to the master. According to various aspects of the invention, the write throughput requirement will be used to set the size of the request network, which is the data from the master to the slave. According to various aspects of the invention, examples of throughput requirements for various scenarios are shown in Table 500. The actual format used to represent the scenario can be different, as long as each pair (master, slave) has an accurate definition of the minimum required throughput for reading and writing. In Table 500, a read transaction from M1 to S1 has a minimum performance throughput of 100MB / s. In Table 500, a write transaction from M1 to S1 has a minimum throughput of 50MB / s.

[0086] According to some aspects of the invention, the scenario is not limited to a tool, in which case the tool optimizes the NoC synthesis process for physical cost, such as lowest gate cost and / or lowest wire cost.

[0087] Reference now Figure 6 Together with Figure 2B , an initial network 600 is created according to various aspects of the present invention. The network 600 implements a connectivity matrix having the following defined parameters or components:

[0088] One network interface unit per master device,

[0089] One network interface unit per slave device,

[0090] One switch is created for each defined service class, called the primary switch for that class,

[0091] A switch after distributing traffic to each initiator / master NIU of a different master switch that this master needs to reach,

[0092] A switch before each target / slave NIU that merges traffic from different master switches that send traffic to the target

[0093] The data width of each switch and the clock domain it belongs to are calculated using the data width of each attached interface and its clock domain as input to the tool. According to various aspects of the invention, each step of transforming a network that is part of a NoC also performs calculations of the data width and clock domain of the newly created network elements.

[0094] Reference now Figure 7 and Figure 2B , showing Figure 6A network 600 is provided, wherein the network 600 is transformed by a tool process according to various aspects of the present invention. The sequencer 250 has an input 254 representing the decomposition of a main switch into a combiner and a splitter. The tool decomposes each main switch of the network 600 into its equivalent implementation with a splitter and a combiner. According to various aspects of the present invention, some switches have a single ingress port and multiple egress ports. According to various aspects of the present invention, some switches have multiple ingress ports and a single egress port. Each main switch ingress port is connected to a splitter, and each main switch egress port is connected to a combiner. For the main switches, the splitters and combiners are connected together according to a connectivity table.

[0095] Reference now Figure 8 , a floor plan 800 is shown according to various aspects of the invention. The sequencer 250 has an input 256 representing the creation of a roadmap between each master and slave. The floor plan 800 includes physical paths 802 calculated between a master interface (M0) on the floor plan and each of its connected slaves (e.g., slave S0, slave S1, slave S2, and slave S3). The paths 802 are referred to as the splitter roadmap for the master M0; although not shown, each master will have a splitter roadmap. The tool uses any algorithm suitable for finding a path between a source point and multiple destination points, including an algorithm that minimizes the path length.

[0096] Reference now Fig. 9 , the floor plan 800 has a calculated physical path 902 between the slave interface of the slave device S0 on the floor plan and each of the masters to which it is connected. Path 902 is the merger roadmap of the slave device S0. As will be apparent, each slave device will have a merger roadmap. The tool uses any algorithm suitable for finding paths between multiple source points and destination points, including algorithms that minimize path length. According to various aspects of the present invention, the tool transforms the network in a manner that maintains its functionality and adds location information to network elements.

[0097] Reference now Fig.10 , shows a floor plan 800 with paths 1002 according to various aspects of the present invention. The sequencer 250 has an input 258 that provides the physical distribution of splitters and mergers on the roadmap. Using the tool, each switch is decomposed into mergers and splitters. Using the tool, each splitter in the main switch is further decomposed into a cascade of splitters, and each splitter of the cascade is placed at a branch point of the splitter roadmap of the attached master device. The branch point of the roadmap is defined by the fact that the path splits into two or more branches.

[0098] Reference now Fig.11 , showing a floor plan 800 with a path 1102 according to various aspects of the present invention. Using the tool, each switch is used for each of the combiners in the master switch, the combiners are further decomposed into a cascade of combiners, and each combiner of the cascade is placed at a branch point of the combiner roadmap of the attached slave device. The branch point of the roadmap is defined by the fact that the path is divided into two or more branches. The process of decomposing a splitter in a cascade of splitters maintains the original splitter functionality because the number of inputs to the cascade is still one, and the number of outputs of the cascade is the same as the number of outputs of the original splitter. The process of decomposing a splitter in a cascade of splitters maintains the original splitter functionality because the number of outputs of the cascade is still one, and the number of inputs to the cascade is the same as the number of inputs to the original combiner. According to various aspects of the present invention, the effect of the process is to obtain a set of basic switches represented by combiners and splitters, and the basic switches are physically placed near the locations where the actual connections between the switches need to be located.

[0099] According to various aspects of the invention, the tool transforms the network to reduce the number of wires used between switches that can be realized while maintaining the performance defined in the scenario, which is a set of required minimum throughputs between the master and slaves. According to various aspects of the invention, the switches are clustered for performance-aware switching, treating mergers and splitters that have been distributed on the roadmap like ordinary switches.

[0100] According to one aspect of the invention, the tool uses an iterative process and will merge switches while still satisfying performance until no further switch merging can occur. The tool uses the process described below:

[0101] 1) Although no switch fusion is possible anymore, the following operations are performed:

[0102] a) Select a candidate switch for merging with one of its neighbors. The selection process ensures that all switches in the network are ultimately candidates.

[0103] b) When selecting a candidate, search for neighbors to merge. The neighbor criteria is based on an evaluation of a cost function. The cost function should return the switch that is "best" to merge with the candidate. The definition of "best" depends on the implementation, but the cost function should be such that the potential fusion of two switches maximizes the gain in at least one metric, including: wire length; logic area; power; and performance, etc.

[0104] c) In the event that convergence occurs, test whether the performance scenarios will still all meet the minimum throughput requirements. If not, then the two switches cannot be merged. The process performed by the tool searches for another neighbor until no more neighbors can be found, in which case all switches remain intact, or until one neighbor is found that can be merged with the candidate without violating the minimum throughput requirements for all scenarios, in which case the network is modified by merging the candidate switch with the neighbor.

[0105] According to various aspects of the invention, it is possible that the process ensures that the switch does not grow beyond a certain size (maximum number of ingress ports, maximum number of egress ports). If the combined switch is above a set threshold, then merging is prevented.

[0106] Reference now Fig.12 , according to various aspects of the invention, candidate switch SW3 is shown next to switch SW4 for the combiner. Sequencer 250 has an input 260 that provides a performance-aware switch cluster. The tool performs a process for merging two switches. When switches are merged, wires from different switches are simplified to one wire from each connecting switch to the combined switch. According to various aspects of the invention, switches SW3 and SW4 are merged. The connections between SW1 and SW4 and SW3 are combined and replaced by a single connection between SW1 and SW3_4. Thus, long connections between distant switches are removed and reduced to a minimum, while connections between close switches are removed and completed within the switches themselves.

[0107] Reference again Figure 2B , input 262 to sequencer 250 includes various optimizations that may be performed to further reduce the number of wires used by the network, the area of ​​the network elements, and the power consumed by the network elements. Examples of such optimizations include: detecting links that may be removed due to non-use or their traffic may be rerouted; reducing the width of a link if it is wider than required by the scenario; and performing wire length optimization by finding the optimal placement of all switch elements that minimizes the bus length of the network, where the bus length of the network is the sum of the distance spanned by each connection between network elements multiplied by the width of the connection.

[0108] continue Figure 2B, the input 264 to the sequencer 250 includes generating a legal NoC by modifying the position of the network elements so that the network elements fit in the allocated free space and do not overlap and they exist within the corresponding clock and power domain constraints. According to various aspects of the present invention, the area occupied by each network element on the die is calculated using the information provided about the technology capabilities (e.g., the area of ​​the reference logic gates). The correctness of the placement of each element is then tested (there is enough free space for the element, no other elements overlap). If the test fails, the element is moved until a suitable position is found where the test passes.

[0109] form

[0110] Reference now Fig.13 , floor plan 1300 shows a deadlock-free NoC that can be represented in terms of multiple segments and turns. A segment represents a guiding path between two components, such as "A" 1311 and "B" 1301, "B" 1301 and "C" 1302, "C" 1302 and "D" 1303, and / or "D" 1303 and "A" 1311. A first segment 1304 maintains a physical path between "A" 1311 and "B" 1301 in the floor plan, a second segment 1305 maintains a physical path between "B" 1301 and "C" 1302 in the floor plan, a third segment 1306 maintains a physical path between "C" 1302 and "D" 1303 in the floor plan, and a fourth segment 1307 maintains a physical path between "D" 1303 and "A" 1311 in the floor plan, which is a physical coordinate (x i ,y i ). Within the scope of the present invention, a fragment has one or more associated cost metrics that can be utilized during synthesis and / or generation to track the cost of certain routines.

[0111] Turns as a pair of segments can be utilized in a way that deadlocks in the network are avoided. Considering the allowed turns 1308, turns 1309, and turns 1310, as long as there is no loop between the segments, the network remains deadlock-free. According to another aspect or embodiment of the present invention, loops may exist between nodes. Turns have dependencies between segments, which are the basic mechanisms to ensure that the network is deadlock-free. Within the scope of the present invention, there are loops between nodes to reuse wires without causing deadlocks so that only necessary channels are allocated to prevent node loops. Therefore, this eliminates unnecessary channels and reduces the associated wire costs associated therewith.

[0112] Reference again Fig.13, the presence of a first turn 1308 from the first segment 1304 to the second segment 1305 indicates that the data packet can be routed from the first segment 1304 to the second segment 1305. The presence of a second turn 1309 from the second segment 1305 to the third segment 1306 indicates that the data packet can be routed from the second segment 1305 to the third segment 1306. The presence of a third turn 1310 from the third segment 1306 to the fourth segment 1307 indicates that the data packet can be routed from the third segment 1306 to the fourth segment 1307. With respect to segment separation, the segments "S1" to "S2" can be routed at any point (x) in their physical route. i ,y i ), resulting in two new segments. This network is deadlock-free because there is no turn where (D, A) approaches (A, B).

[0113] Reference now Figures 14A to 14D , showing an embodiment of fragment separation on NoC 1400. Fragment 1403 ( Fig.14A ) is defined by node "A" 1401 to node "B" 1402. A segment 1403 can be separated 1404 at any point (xi, yi) along its physical route ( Fig.14A ) into the new first segment 1409A ( Figures 14B to 14D ) and the new second segment 1409B ( Figures 14B to 14D ). Figures 14B to 14D This separation is best depicted by 1404 ( Fig.14A ) results in a newly created node S1408 ( Figures 14B to 14D ). The first turn 1405 and the second turn 1406 are shown. Figures 14B to 14D ) and the third turn 1407.

[0114] Fig. 14B Segment splitting of a NoC topology is shown with a split segment "A" 1401 to "B" 1402 which is updated to use two new sub-segments "A" 1401 to S 1408 and S 1408 to "B" 1402. The newly created node "S" 1408 is a new switch in the NoC. The set of turns involving the split segment is updated to use the two new sub-segments. A new turn 1406 is added while turn 1407 is maintained.

[0115] A segment that has been separated is no longer considered "as is" because the separation has produced sub-segments with variable routes. This recursive representation is essential for incrementality because it ensures that segments that are part of an existing route and may need to be separated can still be recovered as a series of sub-segments when reconstructing the existing route. Separating a segment allows the segment to be connected to a new segment. This produces a new set of turns.

[0116] Fig. 14CDepicted is the new segment 1411 represented by the channel between node N 1410 and node S 1408 merging into the separated segment, resulting in a new turn 1412 .

[0117] Fig.14D A new segment 1413 represented by the channel between node N 1410 and node S 1408 is depicted bifurcating into a separate segment, resulting in a new turn 1414. The added node N 1410 may include, but is not limited to, an IP block and / or an initiator.

[0118] process

[0119] According to one aspect and embodiment of the present invention, the system performs a generation and synthesis process, and all existing network routes are converted into segments and turns. In an embodiment, for example, the entire NoC is described as a set of at least one segment defined by a physical path between two nodes (S, D). According to various aspects and embodiments of the present invention, if the network is not deadlock-free, the system provides a "failure" notification and returns it to the user, because according to one or more aspects of the present invention, the network or NoC must be initially deadlock-free. The system also extracts a collection of connections that do not have defined routes and / or connections that need to be synthesized. The extracted connection sets are sorted in view of the heuristics. According to various aspects and embodiments of the present invention, for each connection source S to the destination D, a single connection synthesis process involves the use of a configuration resource manager, a configuration filtering module, a configuration selection module, separation, creation, and route calculation. Each of the newly created components, switches, and links is configured by allocating clock domains and data width settings so that bandwidth requirements are met.

[0120] Fig.15 1 is a flow chart illustrating a method 1500 for a NoC generator using a topology synthesis process. The input 1503A to be synthesized may be a new connection 1501 and / or the input 1503B may be an existing segment 1502. The new connection 1501 includes creating new components, such as switches and / or links, thereby defining a network route from S to D. The existing segment 1502 may be re-represented as at least one segment and / or a pair of segments with at least one turn. The existing network has an unchangeable set of turns. When a new segment is added, the turns associated with the newly added segment are also added to complete the route from S to D. The added turns do not create loops and / or deadlocks with existing turns.

[0121] The configuration resource manager 1504 receives input 1503A as a new connection 1501 and input 1503B as an existing fragment 1502. Since there are multiple ways to connect to the fragment S to D, the configuration resource manager 1504 is based on each fragment being assigned a communication strategy 1506 to influence the best configuration. The configuration resource manager 1504 uses the exploration of legal configurations 1505 to explore different ways to connect S to D. Legal configurations 1505 are lists of described parameters. The configuration resource manager 1504 is configured to explore and / or review and analyze at least one possible configuration, and the at least one possible configuration indicates a location, traverses the fragments, and separates the fragments from the list of meaningful configurations stored in the memory. The configuration resource manager 1504 may have a configuration with a new entry fragment for connecting S to a certain fragment of the NoC. If S is already connected, it already has an entry fragment. The configuration resource manager 1504 may have a configuration with a new exit fragment for connection.

[0122] The cost of a given path is updated at each step according to the communication strategy 1506. In an example, moving within an existing segment far from the destination may have more or less cost than creating a new segment that goes directly to the destination, depending on whether the communication strategy 1506 favors wire length and / or latency. Within the scope of the present invention, the perfect shortest path algorithm uses cost updates as a way to efficiently implement several communication strategies to explore two specific segments and identify potential future segments.

[0123] The main configuration exploration process (configuration explorer 1504) can be designed as a specialized version of a common shortest path algorithm including but not limited to A* and / or Dijkstra. A given step in the shortest path algorithm considers different points that can be reached from the current point. The current point is at least one point along the physical path of the existing segment. Paths from the current point to subsequent points in the current segment need to be considered.

[0124] In an embodiment, the path may advance one step along the path of the current segment. In an embodiment, if the end of the path of a segment has been reached, the path may advance to the first point in the path of any of the next segments, such as segments directly connected to the current segment and segments that the current segment can "turn around" to.

[0125] In an embodiment, if the destination is not connected, for example if there is no exit segment, the path may jump directly to the destination point. This corresponds to creating a new exit segment. New and / or future exit segments are then added to the configuration.

[0126] In yet another embodiment, the path may jump to any point in any fragment as long as no circular dependency is created, the two fragments have compatible communication strategies, and the communication strategies allow merging. This corresponds to creating a new internal fragment, which is added to the configuration.

[0127] Reference again Fig.15 , the configuration filtering module 1507 has a predetermined list containing data, the data including but not limited to which configurations are legal, which configurations produce deadlocks, and which configurations are not optimal. The configuration filtering module 1507 filters the configurations taking into account multiple criteria and retains only a subset, the criteria including but not limited to the criteria based on the communication strategy 1506 and / or any custom criteria. In the example of custom criteria, users such as programmers can base parameters on low latency defined by the shorter length between the routes from S to D. The user can define the maximum length of the path. If the length of the path exceeds a user-defined threshold, the configuration filtering module 1507 of the communication strategy 1506 will remove the route. In another example, the parameters can be based on the use of the minimum number of additional wires. In another example, the parameters can be based on a cost function that favors the route with the lowest cost from S to D. The configuration filtering module 1507 can be customized according to user predefined parameters. Users can set their own filters and discard certain types of configurations.

[0128] The first criterion is based on the communication strategy 1506. The user can control the way to create a new segment. The communication strategy 1506 is a set of parameters that can be associated with any given connection in the network. The system can have multiple communication strategies defined, and each connection can be associated with a communication strategy 1506. The communication strategy 1506 has parameters and flags. In the example of the flag, low latency means that the connection should be implemented in a way that minimizes the total path length from the source to the destination. In another example of the flag, enabling serialization means allowing the links involved in the path from the source to the destination to adopt serialization to save wires. Some configurations for a given connection may not be legal relative to the communication strategy 1506 that manages the connection. Qualified configuration 1508 is a filtered version of a legal configuration. In an example, if the connection S to D is set to have a low latency communication strategy, then the total length of the route and the number of hops or traversal components must be applied, and configuration candidates that do not belong to these restrictions are discarded.

[0129] Reference again Fig.15, after filtering, the configuration filtering module 1507 outputs a qualified configuration 1508. It is desirable to select a qualified configuration executed by the configuration selection module 1509. Selecting the best configuration is implemented using the configuration selection module 1509, which retains only a final configuration to be implemented as the final synthesis of connecting S to D. The metric for selecting the best configuration is configurable, and several parameters can be considered based on the communication strategy 1506. In an embodiment, the communication strategy parameter is the overall additional wire length. The length of the additionally created fragment produces the wire required to traverse the route. There is a cost associated with the wire. It is more desirable that the parameter is intended to minimize the total wire length to reduce the topological cost. In an embodiment, the communication strategy parameter is the total route length. The total length of the route is the sum of the existing fragments plus the combination of the newly added fragments. This parameter focuses on minimizing the delay. In another embodiment, the communication strategy parameter is based on bandwidth distribution. This parameter optimizes performance by focusing on the associated congestion level on the business distribution and the fragment.

[0130] Once the best configuration 1510 is selected, the system implements 1511 the best configuration 1510 and applies it to the network by separating the involved segments and creating 1512 new segments and turns. Within the scope of the present invention, the best configuration is the final configuration. When a segment is separated, it is separated at all existing segments that need to be connected to the new segment at the point specified by the selected configuration. Regarding optimization, if the separation point is within a certain distance from one of the segment endpoints and the endpoint is a switch, the endpoint should be reused for connection instead of creating a new switch. This can reduce the number of switches created. Create 1512 the required new segments specified by the selected configuration and activate the corresponding turns. The newly created 1512 segments and turns are combined with the existing segments 1502 and turns and are input into the routing tool 1513 that generates the final route 1514. The route from S to D is calculated taking into account the newly created segment. The route is stored in the memory. The routing tool 1513 is a routing connection on a geographic floor plan because the segment is defined according to the geographic path it follows the floor plan.

[0131] Fig.16A A NoC topology 1600 is shown above a floorplan with source (S) 1601 to destination (D) 1602. If an existing network exists and a change is requested, such as a request to add a new connection from a node at S 1601 to a node at D 1602, then incremental synthesis will need to be performed. IP blocks are examples of constraints on the floorplan that routes need to be navigated in. Existing nodes are connected to each other. It is desirable to create routes for new connections in the existing network without having to make changes to the existing structure.

[0132] Fig. 16B1 shows a NoC topology 1600 above a floorplan with incremental synthesis results of a routing configuration from S 1601 to D 1602 with a new ingress segment 1603 having a node at S 1601 and a node 1606 with a new internal segment 1604 nearby, and an egress segment with a node 1605 close to D 1602, according to various aspects and embodiments of the present invention. Fig. 16B The exploration of legal configurations 1505 is shown in the configuration shown in , where if the node is not already connected to the NoC, then an ingress fragment 1603 is added. In an embodiment, the new ingress fragment 1603 can connect S1601 to the fragment of the NoC. If S1601 is already connected to the fragment of the NoC, then it already has an ingress fragment.

[0133] exist Fig. 16B In the illustration of , there is an egress segment 1605 because D 1602 is already connected to another node. Therefore, if D 1602 is already connected, it already has an egress segment. A new egress segment may be a configuration option for connecting a segment of the NoC to D 1602.

[0134] Reference again Fig. 16B , there are any number of internal fragments 1604 within the scope of the present invention. According to some aspects and embodiments of the present invention, the tool includes a machine learning model that is capable of suggesting and generating new fragments based on the training of the model (including feedback generated by previous designs). At least one and / or more new internal fragments can connect existing fragments so that the entry fragment reaches the exit fragment. The connection between two existing fragments is only considered if it does not create a circular dependency between the fragments, thereby ensuring that only deadlock-free configurations are considered. The synthesis may include calculating the network route without generating any new switches and / or fragments. This situation may occur when both S and D are connected to the network or NoC, and the entry fragment may have reached the exit fragment only in the case of an existing turn. An important aspect of the present invention is that the configuration can define future fragments, including using a machine learning model with feedback capabilities for further training the model, without generating specific fragments in the topology during the exploration phase.

[0135] In an embodiment, the system may pre-set multiple common communication strategies to make it easier for the user to make a selection. It is more desirable for the user to select from a pre-set list rather than requiring the user to create a communication strategy. Connections associated with different communication strategies will have physically separate synthesis routes. During synthesis, the configuration filter module 1507 ( Fig.15 ) and configuration selection module 1509 ( Fig.15 ) depends on communication policy 1506 ( Fig.15 ) to output an optimal configuration 1510 for implementing the 1511 route.

[0136] Fig.17A Shown above is a NoC topology with a floorplan having a communication strategy 1700 to optimize wire length on a best effort basis, in accordance with various aspects and embodiments of the present invention. Fig.17A and 17B Shows how the same connection can result in different implementations based on the communication strategy selected. Fig.17A In the illustration, according to various aspects and embodiments of the present invention, the focus is on connecting node S to node D, and the parameter of wire length is the main criterion for optimization. The configuration selection module (which can be controlled by a machine learning model) selects the implementation scheme that produces the minimum additional wire. It is shown that a turn 1704 with a short entrance segment 1703 and activation will meet the parameter requirements.

[0137] Fig. 17B 1 shows a NoC topology above the floor plan with a communication strategy 1710 as low latency communication, according to various aspects and embodiments of the present invention. In this example, there is a preference for a direct connection 1713 between node S 1711 and node D 1712, rather than traversing several switches. One turn 1714 activated is near D. Although this configuration creates more additional wire and is more costly, it is the path with the shortest length from S to D that the user chooses.

[0138] The basic method for incrementally synthesizing new connections while reusing existing fragments is described in Figures 1A to 20B This embodiment relies on splitting existing segments to fork out new segments. At the end of the process, only the newly created components are configured, such as clock and / or data width, and the existing components remain unchanged. Fig.15 , according to various aspects and embodiments of the present invention, existing segments 1502 and turns are altered at incremental levels by user control. According to some aspects and embodiments of the present invention, existing segments and turns are altered by a machine learning model that is trained for generating on-chip networks. The user (with or without input from the model) utilizes communication policies 1506 to control not only the creation and selection of new segments in the network, but also to modify existing topologies or segments. In an instance, it may be undesirable to reuse existing segments in new routes due to performance considerations or due to previous optimizations that the user may have implemented and that depend on segments remaining unchanged. When segments are separated, hops may be added to traverse multiple routes, which may not be the desired result. Therefore, the system defines a number of incremental levels or modes that are based on the physical variability of the segments, the physical variability of the switches, and the logical variability of the network elements. It is more desirable to capture the user's intent when synthesizing a new set of connections in the presence of an existing NoC topology.

[0139] In an alternative embodiment, incremental synthesis mode allows the user to customize how the existing topology is changed.

[0140] Regarding the physical mutability of segments, segments are mutable by default. A segment can be detached to fork off a new segment. If, for example, a switch does not need to be added to an existing route, the user can make a segment immutable.

[0141] Referring to the physical mutability of a switch, if the endpoint is a switch, a new segment can be connected to an existing endpoint of an immutable segment. If the physical size of the switch does not need to be modified, the switch can be immutable so that no new segment can be connected to the immutable switch.

[0142] Referring now to the logical variability of network elements, by default, existing network elements including but not limited to data width and / or assigned clocks are not reconfigured through the incremental synthesis process. Only newly created switches and adapters are configured. This may result in inefficient configurations, such as insufficient bandwidth and / or excessive clock domain crossings. Any component may be marked as logically variable to allow reconfiguration of existing components taking into account new resulting topologies. In an example of how pre-set incremental synthesis modes may be defined in a system based on the aforementioned concepts, three pre-set modes are discussed.

[0143] Fig.18A An incremental synthesis mode 1800 is shown for initial setup of a segment connecting from node S 1801 to node D 1802. According to various aspects and embodiments of the present invention, a high bandwidth segment 1803 and a low bandwidth segment 1804 traverse an existing NoC topology route. During initial setup, user parameters will determine how to change the existing topology to connect S 1801 to D 1802.

[0144] Fig.18B An incremental synthesis pattern 1810 for physical invariance of a segment with minimally changed parameters is shown according to various aspects and embodiments of the present invention. The segment splits at node 1811 to fork 1812 a new segment and creates a U-turn in a deadlock-free network to connect S 1801 to D 1802 with minimal changes. The high bandwidth segment 1803 is not changed to prevent splitting and the route traversed by the low bandwidth segment 1804 is routed around the existing NoC topology route.

[0145] It is more desirable to maintain the maximum amount of existing topology. All segments are made physically immutable, except for the ingress and egress segments, because the ingress and egress segments are needed to implement new connections. All switches are physically immutable, and all network elements are logically immutable. In an example, if a segment from S 1801 to D 1802 is marked as immutable, it will prevent the separation of segments and promote routing around existing segments. Therefore, existing segments remain unchanged.

[0146] Fig. 18C An incremental synthesis pattern 1820 for logical invariance of segments with parameters identified as optimized topology and saved configuration is shown. The low bandwidth 1804 segment is separated at 1821 and a new segment 1822 is forked, and a new turn is created to connect S 1801 to D 1802. According to various aspects and embodiments of the present invention, the high bandwidth is not fully utilized because it is connected to a lower bandwidth and the switch is not changeable. It would be more desirable for some switches to be changed to adapt. This pre-setting allows existing segments to separate and allows switches to have new connections for a more optimized topology. Therefore, better costs (in terms of resources and wire utilization) can be achieved through the reuse of existing elements. According to various aspects and embodiments of the present invention, existing network elements can be made to be logically immutable so that, for example, clock frequency, clocks assigned to switches, and / or other properties remain unchanged.

[0147] Fig.18D An incremental synthesis pattern 1830 for variability of network elements with optimized topology and adapted configured parameters is shown. A high bandwidth 1803 segment is split at node 1831 and a new segment 1832 is forked, and a new turn is created to connect S 1801 to D 1802. According to various aspects and embodiments of the present invention, the high bandwidth is fully utilized because it is connected to a higher bandwidth because the switch is changed. Greater flexibility is achieved in the synthesis process when all segments can be split, switches can be connected to new segments, and / or components can be reconfigured if reconfiguring the components will improve the results, such as when changing clocks to improve performance.

[0148] Fig.19The process of NoC 1900 synthesis based on mesh custom subnetwork description is shown according to various aspects and embodiments of the present invention. First, mesh fragments are generated and physically optimally placed in the requested space, which can be achieved using a machine learning model that is trained by network topology synthesis and generation with feedback for further training. Second, the new mesh fragments, now treated as pre-existing fragments by the incremental synthesis process, have the opportunity to be used to generate the final route when appropriate. The result is a topology that mixes the automatically generated conventional mesh topology with the new optimally generated or synthesized fragments. In a fully connected system, the network on chip (NoC) 1900 has each node 1901 connected to every other node. In various aspects and embodiments of the present invention, the XY routing algorithm is used to specify regions 1902 for the 3×3 mesh. This enables the identification and selection of regions in the floor plan for the placement of the 3×3 mesh. As a result of the synthesis process 1903, the NoC 1905 uses the requested mesh fragments and the newly synthesized fragments. In various aspects and embodiments of the present invention, an automatically synthesized local tree 1904 is shown, which can be completed using a machine learning model. The grid is generated and optimally placed within the designated area 1906, representing a 3x3 grid.

[0149] According to other aspects of the invention, an extension of the clock and power domains on the floor plan is provided, and each component is tested to ensure that it is within the boundaries of the specified clock and power domains. If the test fails, the component is moved until a suitable position is found that passes the test. Once the appropriate placement of each component has been found, each connection between the components is routed. The routing process will find a suitable path for the wire set connecting between the components. After routing, based on the time it takes for the signal to cover a distance of 1mm, the information provided about the technical capabilities is used to insert the pipeline elements that span the distance on the link when needed.

[0150] According to some aspects and embodiments of the invention, a tool generates one or more computer files describing the generated NoC, the computer files comprising:

[0151] List of network elements with their configuration: data width, clock domain.

[0152] The location of each generated network element on the floor plan.

[0153] A collection of routes through network elements that implement connectivity.

[0154] According to aspects of the invention, a route is an ordered list of network elements, one for each pair (initiator, target) and one for each pair (target, initiator). A route represents how traffic between the pairs will flow and through which elements.

[0155] According to various aspects of the invention, tools are used to generate metrics about the generated NoC, such as: histogram of wire length distribution, number of switches, histogram of switches by size.

[0156] According to another aspect of the invention, the tool automatically inserts various adapters and buffers in the network. The tool inserts adapters based on the adaptation required between two elements with different data widths, different clock and power domains. The tool inserts buffers based on scenarios and detected rate mismatches.

[0157] Fig. 20A and Fig. 20B A floor plan for using a custom subnetwork description is shown. According to various embodiments and aspects of the invention, the tool may accept new input as part of the synthesis process, such as a custom subnetwork description. According to various embodiments and aspects of the invention, the machine learning model of the tool analyzes the description to provide the generation of the NoC. The custom subnetwork description describes the subnetwork that will be generated before the synthesis process begins. The custom subnetwork description includes the following:

[0158] -Geographic Boundary: A rectangular area used to place this network within the floor plan.

[0159] - Sub-network type: can be one of several predefined general network types (Mesh, Torus, etc.).

[0160] - Configuration: Specific to each sub-network type. For example, for a mesh network, it is defined by the number of rows, columns, and routing algorithm (e.g., XY, North-Last, etc.).

[0161] Once the custom subnetwork descriptions are created, the process involves performing the following analysis or processing of each custom subnetwork description before starting the synthesis process:

[0162] 1) According to various embodiments and aspects of the present invention, from the geographic boundaries and sub-network types, use the sub-network placement module to generate optimal node locations so that: (e.g., for a grid)

[0163] - the entire subnetwork occupies the largest possible area within the boundaries;

[0164] - the straight segment does not physically conflict with floor plan obstacles; and

[0165] - Fragment sizes are as uniform as possible

[0166] 2) According to various embodiments and aspects of the present invention, given a subnetwork type, configuration, and previously generated node locations, a tool that can be trained using a machine learning model for network generation (using, for example, a conventional topology generator) creates:

[0167] a.Switch;

[0168] b. Immutable internal fragments;

[0169] c. Corresponding to the turns of the routing algorithm; and

[0170] d. Variable entry and exit fragments to enter and exit the regular subnetwork respectively.

[0171] In the case where new fragments of a subnetwork are registered, an incremental synthesis process may be invoked to implement the new connections, while using the regular subnetwork when possible.

[0172] Reference again Fig.21 , a process is shown that illustrates how a NoC is synthesized based on a mesh custom subnetwork description according to various aspects and embodiments of the present invention. In step 2110, mesh fragments are generated and physically optimally placed on the requested space. In step 2112, the new mesh fragments, now treated as pre-existing fragments by the incremental synthesis process, are given the opportunity to be used when appropriate. In step 2114, using the pre-existing fragments, the tool generates the final route. The result is a topology that blends the automatically generated conventional mesh topology with the new optimally synthesized fragments.

[0173] According to some aspects and embodiments, a tool may be used to ensure that multiple iterations of synthesis are performed for incremental optimization of the NoC, including when one constraint provided to the tool is information about a previous run.

[0174] After the synthesis process is performed by the software, the result is produced in a machine-readable form, such as a computer file that captures the information using a well-defined format. An example of such a format is XML, and another example of such a format is JSON. The scope of the present invention is not limited by the specific format.

[0175] Some aspects of the present invention adopt an incremental approach to network synthesis. This incremental approach is applicable to many scenarios. For example, in some embodiments, the incremental process starts with a standard and clean floor plan. In these and other embodiments, some embodiments are discussed above.

[0176] According to some aspects and embodiments, a connection may have a communication policy that specifies, for example, the sensitivity of the connection to latency.

[0177] Certain methods according to various aspects of the present invention may be performed by instructions stored on a non-transitory computer-readable medium. A non-transitory computer-readable medium stores code containing instructions that, when executed by one or more processors, will cause a system or computer to perform the steps of the methods described herein. Non-transitory computer-readable media include: rotating magnetic disks, rotating optical disks, flash random access memory (RAM) chips, and other mechanically moving or solid-state storage media. According to various examples, any type of computer-readable medium is suitable for storing code containing instructions.

[0178] Certain examples have been described herein, and it will be noted that different combinations of different components from different examples may be possible. Prominent features are presented to better illustrate the examples; however, it is apparent that certain features may be added, modified, and / or omitted without modifying the functional aspects of these examples as described.

[0179] Various instances are methods of behavior using any one or combination of machines. Method instances are complete no matter where in the world most of the constituent steps occur. For example, and in accordance with various aspects and embodiments of the present invention, IP elements or units include: a processor (e.g., a CPU or GPU), a random access memory (RAM, such as off-chip dynamic RAM or DRAM), a network interface for wired or wireless connections, such as Ethernet, WIFI, 3G, 4G Long Term Evolution (LTE), 5G and other wireless interface standard radios. The IP may also include various I / O interface devices, optionally for different peripheral devices, such as touch screen sensors, geolocation receivers, microphones, speakers, Bluetooth peripherals, and USB devices, such as keyboards and mice, etc. By executing instructions stored in RAM devices, the processor performs the steps of the methods described herein.

[0180] Some examples are one or more non-transitory computer-readable media arranged to store such instructions of the methods described herein. Any machine holding a non-transitory computer-readable medium containing one of the necessary codes can implement an example. Some examples can be implemented as: a physical device such as a semiconductor chip; a hardware description language representation of the logical or functional behavior of such a device; and one or more non-transitory computer-readable media arranged to store such hardware description language representations. The description of the principles, aspects, and embodiments described herein covers both their structural and functional equivalents. The elements described herein as coupled have an effective relationship that can be achieved by direct connection or indirectly with one or more other intervening elements.

[0181] A skilled practitioner in the art will recognize many modifications and variations. The modifications and variations include any relevant combination of the disclosed features. The description of the principles, aspects, and embodiments described herein encompasses both their structural and functional equivalents. Elements described herein as "coupled" or "coupled in a communicative manner" have an effective relationship that can be achieved by direct connection or indirect connection (which uses one or more other intervening elements). Embodiments described herein as "communicating" or "in communication" with another device, module, or element include any form of communication or link and include an effective relationship. For example, a wired connection, wireless protocol, near field protocol, or RFID can be used to establish a communication link.

[0182] To the extent that the terms "including," "includes," "having," "has," "with" or variations thereof are used in the detailed description and claims, such terms are intended to be inclusive in a manner similar to the term "comprising."

[0183] Therefore, the scope of the present invention is not intended to be limited to the exemplary embodiments shown and described herein. Rather, the scope and spirit of the present invention is embodied by the following claims.

Claims

1. A tool for generating a deadlock-free network-on-chip (NoC) using a custom subnetwork description, the tool comprising a non-transitory computer-readable medium for storing code that, when executed by one or more processors of the tool, causes the tool to: identifying a region within a floorplan of the NoC; generating a subnetwork optimally placed within the zone; generating a configuration to a new NoC by synthesizing the NoC including the subnetwork; and A configuration selection module is used to select a final configuration to be implemented for the new NoC.

2. The tool of claim 1 , comprising a machine learning model trained to generate the final configuration.

3. The tool of claim 2, wherein the machine learning model receives feedback for further training. The tool of claim 1 , wherein the subnetwork is a mesh network segment.

5. The tool of claim 4, wherein the mesh network segments are optimally placed within identified spaces in the zone.

6. The tool of claim 1, wherein the zone is selected based on the subnetwork size. The tool of claim 6 , wherein the sub-network is a mesh network segment.

8. The tool of claim 1, wherein the tool is further caused to check the location of the subnet within the region to ensure that the subnet is within the boundaries of a specified clock domain.

9. The tool of claim 1, wherein the tool is further caused to check the location of the sub-network within the zone to ensure that the sub-network is within the boundaries of a power domain.

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