Method for reducing measurement error of key pattern size of polycrystalline layer
By classifying the polycrystalline layer patterns and combining automatic and manual measurement, the problem of large measurement errors and low accuracy of key graphics in polycrystalline layers is solved, and the accuracy of efficient measurement results is improved, and the error rate is reduced from 5% to 0.1%.
Patent Information
- Application Number
- CN202310749893.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-21
- Publication Date
- 2024-12-24
AI Technical Summary
During the integrated circuit manufacturing process, the measurement error of the key pattern size of the polycrystalline layer is large and the accuracy of the measurement results is low, resulting in low efficiency. Especially at technical nodes of 28nm and below, customer design data and wafer graphics are not easy to align, resulting in measurement The result is wrong and it takes a lot of time to check and filter.
Classify the graphics into two categories: easy to measure and difficult to measure. Use high-end electron beam linewidth defect scanning machines to perform automatic measurement and manual alignment measurement. By calculating the scanning range of the electron beam linewidth defect scanning machine Half the width is the standard deviation of the angle and line width of the figure within the radius range to classify it, and automatic and manual measurements are performed to check the measurement results, re-measure the wrong graphics, and improve the accuracy of the final measurement results.
The accuracy of measurement results has been significantly improved, and the error rate has been reduced from 5% to 0.1%, while improving the efficiency of measurement results checking.
Smart Images
Figure CN119181653A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for reducing measurement errors of key graphic dimensions of a polycrystalline layer. Background Art
[0002] Currently, CD SEM is the most commonly used instrument for measuring feature dimensions, but for the collection of tens of thousands of points, it will take more than 150 hours or even more to collect data using CDSEM. The new high-end electron beam line width defect scanning machine EP5 has a large-scale data measurement function, which can quickly and accurately measure tens of thousands of points.
[0003] The polycrystalline layer is one of the most important layers in integrated circuit manufacturing. However, when using EP5 to measure the wafer graphics before etching at technology nodes of 28nm and below, it was found that the customer's design data and the wafer graphics were difficult to align, resulting in erroneous measurement results. As a result, engineers had to spend nearly a week checking and screening tens of thousands of measurement results, which was inefficient. Summary of the invention
[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing the measurement error of the key pattern size of the polycrystalline layer, so as to solve the problem of large measurement error of the key pattern size of the polycrystalline layer and low accuracy of the measurement result in the prior art.
[0005] To achieve the above-mentioned and other related purposes, the present invention provides a method for reducing the measurement error of key pattern dimensions of a polycrystalline layer, which at least comprises:
[0006] Step 1: providing a pattern to be measured, wherein the pattern to be measured is a wafer pattern;
[0007] Step 2: Write rules to classify the graphics to be measured into first-category graphics and second-category graphics. The first-category graphics are easy-to-measure graphics for electron beam line width defect scanning machines; the second-category graphics are difficult-to-measure graphics for electron beam line width defect scanning machines.
[0008] Step 3: For the first type of graphics, the electron beam line width defect scanning machine is used to automatically measure them; for the second type of graphics, the customer design graphics are manually aligned with the second type of graphics, and then the electron beam line width defect scanning machine is used to measure the second type of graphics; and two measurement results are obtained;
[0009] Step 4, check whether there is a measurement error pattern in the two measurement results; if there is a measurement error pattern, repeat step 3 for the measurement error pattern; if there is no measurement error pattern, proceed to step 5;
[0010] Step 5: Analyze the measurement results.
[0011] Preferably, the electron beam line width defect scanning machine in step 2 can easily measure a pattern that is a customer-designed pattern and is easily aligned with a wafer pattern.
[0012] Preferably, in step 2, the electron beam line width defect scanning machine is difficult to measure the pattern that is difficult to align with the customer's designed pattern and the wafer pattern.
[0013] Preferably, the writing rule in step 2 includes calculating the number of corners of the graphics within a radius with half the width of the scanning range of the electron beam line width defect scanning machine and the standard deviation Std_Width of the line width.
[0014] Preferably, the pattern to be measured in step 1 is a pattern of a polysilicon layer.
[0015] Preferably, the first type of graphics in step 2 includes three types, the first type is that the number of corners of the graphics within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is greater than 0; the second type is that the number of corners of the graphics within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0, and the line width standard deviation Std Width =0; the third type is that half the width of the scanning range of the electron beam line width defect scanning machine is the number of corners of the graphics within the radius range is 0, and the line width standard deviation Std_Width≥0.006.
[0016] Preferably, the second type of graphics in step 2 includes: the half width of the scanning range of the electron beam line width defect scanning machine is the number of corners of the graphics within the radius is 0 and the line width standard deviation is 0 <Std_Width<0.006。
[0017] Preferably, the step 5 of analyzing the measurement results without measurement errors is to analyze the graphs of measurement errors in the measurement results and perform measurement again, so as to improve the accuracy of the final measurement results.
[0018] As described above, the method of reducing the measurement error of the key graphic size of the polycrystalline layer of the present invention has the following beneficial effects: the method of the present invention improves the accuracy of the measurement result, so that the measurement error rate is reduced from 5% to 0.1%, and at the same time improves the efficiency of checking the measurement result. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is greater than 0 in the present invention;
[0020] Figure 2It is a schematic diagram showing that the number of corners of the pattern within the radius of the electron beam line width defect scanning machine recording scanning range is 0;
[0021] Figure 3 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is greater than 0 in the present invention;
[0022] Figure 4 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0 and the line width standard deviation is 0 in the present invention;
[0023] Figure 5 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0, and the line width standard deviation is greater than 0.006 in the present invention;
[0024] Figure 6 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0, and the line width standard deviation is greater than 0 and less than 0.006 in the present invention;
[0025] Figure 7 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0 and the line width standard deviation is 0.003 in the present invention;
[0026] Figure 8 It is a schematic diagram showing that the number of corners of the pattern within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0 and the line width standard deviation is 0.005 in the present invention;
[0027] Fig. 9 It is a flow chart of the method for reducing the measurement error of key pattern size of polycrystalline layer according to the present invention. DETAILED DESCRIPTION
[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] See also Figures 1 to 9It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0030] The present invention provides a method for reducing the measurement error of key pattern dimensions of a polycrystalline layer, such as Fig. 9 As shown, Fig. 9 The flowchart of the method for reducing the measurement error of the key pattern size of the polycrystalline layer according to the present invention is shown. The method at least comprises:
[0031] Step 1: providing a pattern to be measured, wherein the pattern to be measured is a wafer pattern;
[0032] Furthermore, in the present invention, the pattern to be measured in step 1 of this embodiment is a pattern of a polysilicon layer.
[0033] Step 2: Write rules to classify the graphics to be measured into first-category graphics and second-category graphics. The first-category graphics are easy-to-measure graphics for electron beam line width defect scanning machines; the second-category graphics are difficult-to-measure graphics for electron beam line width defect scanning machines.
[0034] The present invention further provides that the electron beam line width defect scanning machine in step 2 of this embodiment can easily measure a pattern designed by a customer and can be easily aligned with a wafer pattern.
[0035] The present invention further provides that the electron beam line width defect scanning machine in step 2 of this embodiment is difficult to measure the pattern that is difficult to align with the customer's designed pattern and the wafer pattern.
[0036] The present invention further comprises: the writing rule in step 2 of the present embodiment comprises calculating the number of corners of the graphics within a radius of half the width of the scanning range of the electron beam line width defect scanning machine and the standard deviation Std_Width of the line width.
[0037] The present invention further comprises three types of the first type of graphics in step 2 of this embodiment. The first type is that the number of corners of the graphics within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is greater than 0; Figure 1 As shown, the first type is that the half width R of the scanning range of the electron beam line width defect scanning machine is within the radius range ( Figure 1 The number of angles of the figure (in the range of the dashed box) is greater than 0. Figure 1 The circled ones are the corners in the figure, i.e., the turning points. Figure 1 The number of corners described in is greater than 0. Figure 3 As shown, Figure 3The number of angles is also greater than 0.
[0038] The second type is that the number of angles of the pattern within the range of the radius equal to half of the recording scan range of the electron beam line width defect scanner is 0, and the line width standard deviation Std Width = 0; as Figure 2 shown, Figure 2 in the range within the radius equal to half of the recording scan range of the electron beam line width defect scanner described in Figure 2 (within the dashed box range in Width ) the number of angles of the pattern is 0, that is, the number of corners is 0, and the line width standard deviation Std where Xi is the line width of the i-th pattern within the dashed box range, Figure 2 and the line widths of the first to sixth patterns from left to right in Figure 4 are W1, W2, W3, W4, W5, and W6 in sequence. The n in the formula is the number of patterns for which the line width is calculated within the scan range. Another example is as Figure 4 shown, Width in which the number of angles is 0, and the line width standard deviation Std
[0039] The third type is that the number of angles of the pattern within the range of the radius equal to half of the recording scan range of the electron beam line width defect scanner is 0, and the line width standard deviation Std_Width ≥ 0.006. As Figure 5 shown, Figure 5 in which the number of angles is 0, and the line width standard deviation Std_Width ≥ 0.006.
[0040] Furthermore, in the present invention, the second type of pattern in step two of this embodiment includes: the number of angles of the pattern within the range of the radius equal to half of the recording scan range of the electron beam line width defect scanner is 0 and the line width standard deviation 0 < Std_Width < 0.006. As Figure 6 shown, Figure 6 represents the second type of pattern, the number of angles of the pattern is 0 and the line width standard deviation Std Width = 0.001, Figure 7 represents the second type of pattern, the number of angles of the pattern is 0 and the line width standard deviation Std Width = 0.003, Figure 8 represents the second type of pattern, the number of angles of the pattern is 0 and the line width standard deviation Std Width = 0.005.
[0041] Step 3: For the first type of graphics, the electron beam line width defect scanning machine is used to automatically measure them; for the second type of graphics, the customer design graphics are manually aligned with the second type of graphics, and then the electron beam line width defect scanning machine is used to measure the second type of graphics; and two measurement results are obtained;
[0042] Step 4, check whether there is a measurement error pattern in the two measurement results; if there is a measurement error pattern, repeat step 3 for the measurement error pattern; if there is no measurement error pattern, proceed to step 5;
[0043] Step 5: Analyze the measurement results.
[0044] Furthermore, in the present invention, the step 5 of analyzing the measurement results without measurement errors in this embodiment is to analyze the graphs of measurement errors in the measurement results and measure again, so as to improve the accuracy of the final measurement results.
[0045] In summary, the method of the present invention improves the accuracy of the measurement results, reduces the measurement error rate from 5% to 0.1%, and improves the efficiency of checking the measurement results. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.
[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for reducing the measurement error of key pattern dimensions of a polycrystalline layer, characterized in that: At least: Step 1: providing a pattern to be measured, wherein the pattern to be measured is a wafer pattern; Step 2: Write rules to classify the graphics to be measured into first-category graphics and second-category graphics. The first-category graphics are easy-to-measure graphics for electron beam line width defect scanning machines; the second-category graphics are difficult-to-measure graphics for electron beam line width defect scanning machines. Step 3: For the first type of graphics, the electron beam line width defect scanning machine is used to automatically measure them; for the second type of graphics, the customer design graphics are manually aligned with the second type of graphics, and then the electron beam line width defect scanning machine is used to measure the second type of graphics; and two measurement results are obtained; Step 4, check whether there is a measurement error pattern in the two measurement results; if there is a measurement error pattern, repeat step 3 for the measurement error pattern; if there is no measurement error pattern, proceed to step 5; Step 5: Analyze the measurement results.
2. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 1, characterized in that: The electron beam line width defect scanning machine described in step 2 can easily measure the pattern so that the customer's designed pattern and the wafer pattern can be easily aligned.
3. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 1, characterized in that: The electron beam line width defect scanning machine described in step 2 is not easy to measure the pattern because the customer's designed pattern is not easy to align with the wafer pattern.
4. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 1, characterized in that: The writing rule in step 2 includes calculating the number of corners of the graphics within a radius of half the width of the scanning range of the electron beam line width defect scanning machine and the standard deviation Std_Width of the line width.
5. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 4, characterized in that: The pattern to be measured in step 1 is a pattern of a polysilicon layer.
6. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 5, characterized in that: The first type of graphics in step 2 includes three types. The first type is that the number of corners of the graphics within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is greater than 0; the second type is that the number of corners of the graphics within the radius of half the width of the scanning range of the electron beam line width defect scanning machine is 0, and the line width standard deviation Std Width =0; the third type is that half the width of the scanning range of the electron beam line width defect scanning machine is the number of corners of the graphics within the radius range is 0, and the line width standard deviation Std_Width≥0.
006.
7. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 5, characterized in that: The second type of graphics in step 2 includes: the half width of the scanning range of the electron beam line width defect scanning machine is the number of corners of the graphics within the radius is 0 and the line width standard deviation is 0 <Std_Width<0.006。 8. The method for reducing the measurement error of key pattern dimensions of a polycrystalline layer according to claim 1, characterized in that: In step 5, analyzing the measurement results without measurement errors is to analyze the graphs of measurement errors in the measurement results and measure again to improve the accuracy of the final measurement results.