Semiconductor packaging structure

Abstract

The invention provides a semiconductor packaging structure. The semiconductor packaging structure comprises a driving module which comprises a printed circuit board and a driving circuit, and the driving circuit is located on the printed circuit board; the power module comprises a power semiconductor chip and a substrate, the power semiconductor chip is located on the substrate, and the printed circuit board is located on the side, away from the substrate, of the power semiconductor chip; and the conductive connecting layer is positioned between the printed circuit board and the power semiconductor chip and is respectively connected with the printed circuit board and the power semiconductor chip. In the invention, the conductive connection layer between the power semiconductor chip and the printed circuit board is used as a buffer layer, so that the power semiconductor chip and the printed circuit board can be prevented from being directly connected through salient points in a flip-chip process, and therefore, a copper layer on the surface of the printed circuit board is not easy to damage; therefore, the problem that the current-carrying capacity of a copper layer on the surface of the PCB is reduced due to flip-chip welding of the chip and the PCB in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a semiconductor packaging structure. Background Art

[0002] With the development of semiconductor technology, the characteristic size of chips is constantly shrinking, the integration is constantly improving, the number of terminals is constantly increasing, and the spacing between terminals is constantly shrinking. Therefore, in order to meet the requirement of smaller spacing between terminals, the traditional wire bonding is gradually eliminated in the chip packaging process, and flip chip bonding technology is used instead.

[0003] In the existing chip packaging process, copper pillar bumps or tin-based solder bumps are usually used to directly flip-chip solder the chip and the printed circuit board (PCB). Therefore, the flatness of the stud bumps between the chip and the PCB is difficult to ensure. As a result, there is a phenomenon that the stud bumps damage the copper layer on the surface of the PCB, which causes the current carrying capacity of the copper layer on the surface of the PCB to decrease.

[0004] Therefore, a new semiconductor packaging structure is urgently needed to at least solve the above technical problems. Summary of the invention

[0005] The main purpose of the present invention is to provide a semiconductor packaging structure to solve the problem of reduced current carrying capacity of the copper layer on the surface of the PCB caused by flip-chip welding of the chip and the PCB board in the prior art.

[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, a semiconductor packaging structure is provided, comprising: a driving module, comprising a printed circuit board and a driving circuit, the driving circuit being located on the printed circuit board; a power module, comprising a power semiconductor chip and a substrate, the power semiconductor chip being located on the substrate, and the printed circuit board being located on a side of the power semiconductor chip away from the substrate; a conductive connecting layer, being located between the printed circuit board and the power semiconductor chip, and being connected to the printed circuit board and the power semiconductor chip respectively.

[0007] Furthermore, the power semiconductor chip has a first pad, the conductive connection layer has a second pad, and the semiconductor packaging structure further includes: a metal solder ball located between the first pad and the second pad for bonding the power semiconductor chip to the conductive connection layer.

[0008] Furthermore, the semiconductor packaging structure further includes: a rewiring layer located between the first pad and the metal solder ball.

[0009] Furthermore, the semiconductor packaging structure also includes: a first supporting component, located between the printed circuit board and the substrate, and spaced apart from the power semiconductor chip and the conductive connection layer respectively; and / or a second supporting component, located between the printed circuit board and the substrate, and spaced apart from the power semiconductor chip and in contact with the conductive connection layer.

[0010] Furthermore, the driving circuit, the printed circuit board, the conductive connection layer, the power semiconductor chip and the substrate are stacked in sequence.

[0011] Furthermore, the power module includes a plurality of power semiconductor chips spaced in pairs on a substrate, the printed circuit board and the substrate have at least a hollow area except for the power semiconductor chips and the conductive connection layer, and the semiconductor packaging structure also includes: an insulating medium layer, which fills the hollow area.

[0012] Furthermore, the semiconductor packaging structure also includes: a metal sintering layer located between the power semiconductor chip and the substrate.

[0013] Further, the power semiconductor chip includes a silicon carbide substrate.

[0014] Furthermore, the substrate is a silicon carbide substrate.

[0015] Furthermore, liquid metal is embedded in the silicon carbide substrate.

[0016] By applying the technical solution of the present invention, a semiconductor packaging structure is provided, which includes a driving module, a power module and a conductive connection layer, wherein the printed circuit board in the driving module is located on a side of the power semiconductor chip in the power module away from the substrate, the conductive connection layer is located between the printed circuit board (PCB board) of the driving module and the power semiconductor chip of the power module, and the conductive connection layer is respectively connected to the printed circuit board and the power semiconductor chip. Therefore, compared with the flip-chip welding of the power semiconductor chip directly to the printed circuit board in the prior art, the conductive connection layer between the power semiconductor chip and the printed circuit board serves as a buffer layer, which can avoid the direct connection between the power semiconductor chip and the printed circuit board through the bumps in the flip-chip process, so that the copper layer on the surface of the printed circuit board is not easily damaged, thereby solving the problem of decreased current carrying capacity of the copper layer on the surface of the PCB caused by the flip-chip welding of the chip and the PCB in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0018] Figure 1A schematic cross-sectional structure diagram of an embodiment of a semiconductor packaging structure according to the present invention is shown;

[0019] Figure 2 A schematic cross-sectional structure diagram of another embodiment of a semiconductor packaging structure according to the present invention is shown;

[0020] Figure 3 A cross-sectional structural schematic diagram of another embodiment of a semiconductor packaging structure according to the present invention is shown.

[0021] The above drawings include the following reference numerals:

[0022] 10. substrate; 20. power semiconductor chip; 30. conductive connection layer; 40. printed circuit board; 50. drive circuit; 60. metal solder balls; 70. rewiring layer; 80. first supporting component; 90. second supporting component; 100. first metal sintering layer; 110. second metal sintering layer; 120. copper pad layer. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] As mentioned in the background technology, in the existing chip packaging process, copper pillar bumps or tin-based solder bumps are usually used to directly flip-chip solder the chip and the PCB. Therefore, the flatness of the stud bumps between the chip and the PCB is difficult to ensure, so there is a phenomenon that the stud bumps damage the copper layer on the surface of the PCB, which will cause the current carrying capacity of the copper layer on the surface of the PCB to decrease. In order to solve the above technical problems, the inventors of this application provide a semiconductor packaging structure.

[0027] In some optional embodiments, a semiconductor packaging structure is provided, which includes a driving module, a power module and a conductive connection layer, wherein the driving module includes a printed circuit board and a driving circuit, and the driving circuit is located on the printed circuit board; the power module includes a power semiconductor chip and a substrate, the power semiconductor chip is located on the substrate, and the printed circuit board is located on a side of the power semiconductor chip away from the substrate; the conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected to the printed circuit board and the power semiconductor chip respectively.

[0028] Specifically, the driving module includes a printed circuit board and a driving circuit, wherein the printed circuit board has a first surface and a second surface relative to each other. In an exemplary embodiment, the driving circuit is located on the first surface of the printed circuit board. In another exemplary embodiment, the driving circuit is located on the second surface of the printed circuit board.

[0029] Specifically, since the power semiconductor chip in the above-mentioned power module is located on the substrate, and the printed circuit board is located on the side of the power semiconductor chip away from the substrate, in an exemplary embodiment, the above-mentioned drive circuit and the power semiconductor chip can be located between the printed circuit board and the substrate respectively, or in another exemplary embodiment, the above-mentioned drive circuit is located on the side of the printed circuit board away from the power semiconductor chip, and the substrate is located on the side of the power semiconductor chip away from the printed circuit board.

[0030] Specifically, since the conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected to the printed circuit board and the power semiconductor chip respectively, in an exemplary embodiment, the positional relationship of the printed circuit board, the drive circuit, the power semiconductor chip, the substrate and the conductive connection layer may include: the drive circuit is located on the printed circuit board, the power semiconductor chip is located on the substrate, the drive circuit is located on the side of the printed circuit board away from the power semiconductor chip, and the conductive connection layer is located between the printed circuit board and the power semiconductor chip; or the drive circuit is located on the printed circuit board, the power semiconductor chip is located on the substrate, the drive circuit is located on the side of the printed circuit board close to the power semiconductor chip, the conductive connection layer is located between the printed circuit board and the power semiconductor chip, and the drive circuit and the conductive connection layer are arranged at intervals. Optionally, the material of the conductive connection layer may be a metal material, and further, the conductive connection layer may be a metal molybdenum layer.

[0031] In the above embodiment, the semiconductor packaging structure includes a driving module, a power module and a conductive connection layer, wherein the printed circuit board in the driving module is located on a side of the power semiconductor chip in the power module away from the substrate, and the conductive connection layer is located between the printed circuit board (PCB board) of the driving module and the power semiconductor chip of the power module, and the conductive connection layer is respectively connected to the printed circuit board and the power semiconductor chip. Therefore, compared with the flip-chip welding of the power semiconductor chip directly to the printed circuit board in the prior art, the conductive connection layer between the power semiconductor chip and the printed circuit board serves as a buffer layer, which can avoid the direct connection between the power semiconductor chip and the printed circuit board through the bumps in the flip-chip process, so that the copper layer on the surface of the printed circuit board is not easily damaged, thereby solving the problem of decreased current-carrying capacity of the copper layer on the surface of the PCB caused by flip-chip welding of the chip and the PCB in the prior art.

[0032] In some optional embodiments, the power semiconductor chip has a first solder pad, specifically, the first solder pad is located on a side surface of the power semiconductor chip close to the conductive connection layer, the conductive connection layer has a second solder pad, specifically, the second solder pad is located on a side surface of the conductive connection layer close to the power semiconductor chip, and the semiconductor packaging structure may further include a metal solder ball, which is located between the first solder pad and the second solder pad and is used to bond the power semiconductor chip and the conductive connection layer.

[0033] Furthermore, the first pad and / or the second pad may be a micro-bump pad.

[0034] Specifically, the metal solder ball is located between the first solder pad and the second solder pad, and is used to electrically connect the first solder pad and the second solder pad. Optionally, the metal solder of the metal solder ball can be any one of electronic packaging solders such as Au, In, Sn, Sn-Sp, Sn-Ag, Sn-Cu, Bi-Sb, etc. Optionally, the metal solder ball used in this application can be a gold solder ball.

[0035] Since the prior art only uses the first solder pad (micro-bump) located on the power semiconductor chip to perform flip-chip bonding with the printed circuit board, and the bumps of the above-mentioned first solder pad (micro-bump) formed in the conventional process are usually uneven, when the power semiconductor chip and the above-mentioned printed circuit board are bonded, the stress at the above-mentioned bumps is relatively large, which usually damages the copper-clad film on the printed circuit board, thereby causing the current-carrying capacity of the copper layer on the surface of the PCB to decrease. Therefore, based on the above-mentioned problem, in this embodiment, in order to prevent the bumps from damaging the printed circuit board, the above-mentioned conductive connecting layer is arranged between the power semiconductor chip and the printed circuit board, and a second solder pad for welding to the power semiconductor chip is arranged on the conductive connecting layer, so that the power semiconductor chip is directly bonded to the conductive connecting layer, avoiding direct contact between the bumps of the power semiconductor chip and the printed circuit board, and the conductive connecting layer can also relieve the stress of the bumps, and can prevent the surface copper layer on the printed circuit board from being damaged, thereby solving the problem of decreased current-carrying capacity of the copper layer on the surface of the PCB caused by flip-chip welding of the chip and the PCB board in the prior art.

[0036] In order to align and mount the first pad on the power semiconductor chip with the second pad on the conductive connection layer, in some optional embodiments, the semiconductor package structure may further include a rewiring layer, which may be located between the first pad and the metal solder ball, so as to redistribute the first pad connected to the metal solder ball. Optionally, the material of the rewiring layer may be electroplated copper, supplemented by a base layer of titanium, copper sputtering, etc.

[0037] In some optional embodiments, the semiconductor packaging structure may further include a first supporting component, which may be located between a printed circuit board and a substrate, and is spaced apart from the power semiconductor chip and the conductive connection layer, respectively; and / or a second supporting component, which may be located between a printed circuit board and a substrate, and is spaced apart from the power semiconductor chip, and further, is also arranged in contact with the conductive connection layer.

[0038] Among them, the material of the first support component and / or the second support component can be the same as or different from the material of the conductive connection layer. In the same case, the materials of the first support component, the second support component and the conductive connection layer can all be metal materials. In different cases, the first support component and / or the second support component can be insulating materials, and the conductive connection layer can be metal materials. Further, the materials of the first support component, the second support component and the conductive connection layer can be metal molybdenum, so that the first support component and the second support component can not only play a role in supporting and reducing stress, but also can improve the carrier capacity and increase the insulation capacity, thereby increasing the stability of the packaging structure. In this embodiment, since the printed circuit board and the substrate are arranged in a longitudinally stacked manner, in order to make the printed circuit board and the substrate have strong stability in the longitudinal direction, a support component is arranged between the printed circuit board and the substrate, so that one section of the support component in the longitudinal direction is located on the substrate, and the other end is located on the printed circuit board. Further, the support component located on the printed circuit board can include a first support component and a second support component, and the first support component and the second support component can each include one or more, so that the force between the printed circuit board and the substrate is more balanced.

[0039] Since stacking the other multi-layer structures on the same printed circuit board in sequence is conducive to reducing the occupied area of ​​the printed circuit board, it is possible to achieve three-dimensional high-density packaging of semiconductor packaging structures, improve the integration of devices, and reduce the area of ​​packaging structures, so in some optional implementations, the drive circuit, printed circuit board, conductive connection layer, power semiconductor chip and substrate are stacked in sequence. Furthermore, since the drive circuit, printed circuit board, conductive connection layer and power semiconductor chip are stacked in sequence in this structure, the electronic circuit between the drive circuit and the power semiconductor chip is shortened.

[0040] In some optional embodiments, the power module includes a plurality of power semiconductor chips spaced apart in pairs on a substrate, and the printed circuit board and the substrate have at least a hollow area other than the power semiconductor chip and the conductive connection layer. In order for the hollow area to serve as a heat-insulating layer, the semiconductor packaging structure may further include an insulating medium layer, and the insulating medium layer fills the hollow area.

[0041] Specifically, the material of the insulating dielectric layer can be insulating glue. By filling the hollow area with the insulating dielectric layer (insulating glue), any two adjacent power semiconductor chips between the printed circuit board and the substrate are separated by the insulating dielectric layer (insulating glue), thereby isolating the heat transfer between the power devices. Furthermore, the printed circuit board and the substrate have at least a hollow area other than the power semiconductor chip and the conductive connection layer separated by the insulating dielectric layer (insulating glue), thereby forming a thermal gradient between the printed circuit board and the substrate (i.e., the temperature of the substrate is lower than the temperature of the printed circuit board, so that the heat of the semiconductor packaging structure can be extracted from the substrate), ensuring the normal operation of the device. Optionally, the insulating glue can be epoxy resin.

[0042] In order to strengthen the connection between the power semiconductor chip and the substrate, and the connection between the conductive connection layer and the printed circuit board, in some optional embodiments, the semiconductor packaging structure further includes: a metal sintering layer, located between the power semiconductor chip and the substrate. Further, the metal sintering layer may include a first metal sintering layer and a second metal sintering layer, and the semiconductor packaging structure may further include a copper gasket layer, which is located between the first metal sintering layer and the second metal sintering layer, and the first metal sintering layer is located between the copper gasket and the power semiconductor chip, and the second metal sintering layer is located between the copper gasket and the substrate.

[0043] Optionally, the material of the metal sintering layer may be metallic silver.

[0044] In some optional embodiments, the power semiconductor chip includes a silicon carbide substrate. Further, the substrate is a silicon carbide substrate.

[0045] In the above embodiment, the silicon carbide substrate has a higher heat dissipation coefficient, and the main heat in the power module is extracted through the silicon carbide substrate, thereby improving the heat dissipation efficiency of the power module. Since the base materials of the silicon carbide substrate and the silicon carbide substrate are consistent, the thermal expansion coefficients of the two are consistent, thereby reducing the thermal mechanical stress between the two, avoiding problems such as warping of the power semiconductor chip due to mechanical stress when the two are connected and fixed, thereby further ensuring the reliability of the connection of the semiconductor packaging structure.

[0046] Furthermore, in order to make the substrate have a better heat dissipation effect, in some optional embodiments, liquid metal is embedded in the silicon carbide substrate.

[0047] Specifically, in an exemplary embodiment, the semiconductor package structure includes a driving module, a power module, a conductive connection layer and a first supporting component, wherein Figure 1As shown, the driving module includes a printed circuit board 40 and a driving circuit 50, and the driving circuit 50 is located on the printed circuit board 40. The power module includes a power semiconductor chip 20 and a substrate 10, and the power semiconductor chip 20 is located on the substrate 10. The printed circuit board 40 is located on the side of the power semiconductor chip 20 away from the substrate 10. The conductive connection layer 30 is located between the printed circuit board 40 and the power semiconductor chip 20, and is respectively connected to the printed circuit board 40 and the power semiconductor chip 20. The first supporting component 80 is located between the printed circuit board 40 and the substrate 10, and is respectively spaced from the power semiconductor chip 20 and the conductive connection layer 30. Further, the semiconductor package structure may further include a metal solder ball 60. Specifically, the power semiconductor chip 20 has a first solder pad, and the conductive connection layer 30 has a second solder pad. The metal solder ball 60 is located between the first solder pad and the second solder pad, and is used to bond the power semiconductor chip 20 to the conductive connection layer 30. Further, the semiconductor package structure may further include a rewiring layer 70, specifically, the rewiring layer 70 is located between the first pad and the metal solder ball 60. Further, the semiconductor package structure may further include a first support component 80, wherein the first support component 80 is located between the printed circuit board 40 and the substrate 10, and is spaced from the power semiconductor chip 20 and the conductive connection layer 30, respectively. Further, the semiconductor package structure also includes an insulating dielectric layer, which fills the hollow area of ​​the printed circuit board 40 and the substrate 10 with at least the power semiconductor chip 20 and the conductive connection layer 30. Furthermore, the semiconductor packaging structure also includes a metal sintering layer, which is located between the power semiconductor chip 20 and the substrate 10, and the above-mentioned metal sintering layer may include a first metal sintering layer 100 and a second metal sintering layer 110. The above-mentioned semiconductor packaging structure may also include a copper gasket layer 120, which is located between the first metal sintering layer 100 and the second metal sintering layer 110, and the first metal sintering layer 100 is located between the copper gasket and the power semiconductor chip 20, and the second metal sintering layer 110 is located between the copper gasket and the substrate 10.

[0048] Specifically, in another exemplary embodiment, the semiconductor package structure includes a driving module, a power module, a conductive connection layer and a second supporting component, wherein: Figure 2As shown, the driving module includes a printed circuit board 40 and a driving circuit 50, and the driving circuit 50 is located on the printed circuit board 40. The power module includes a power semiconductor chip 20 and a substrate 10, and the power semiconductor chip 20 is located on the substrate 10. The printed circuit board 40 is located on the side of the power semiconductor chip 20 away from the substrate 10. The conductive connection layer 30 is located between the printed circuit board 40 and the power semiconductor chip 20, and is connected to the printed circuit board 40 and the power semiconductor chip 20 respectively. The second supporting component 90 is located between the printed circuit board 40 and the substrate 10, and is spaced from the power semiconductor chip 20 and is in contact with the conductive connection layer 30. Further, the semiconductor package structure may further include a metal solder ball 60. Specifically, the power semiconductor chip 20 has a first solder pad, and the conductive connection layer 30 has a second solder pad. The metal solder ball 60 is located between the first solder pad and the second solder pad, and is used to bond the power semiconductor chip 20 to the conductive connection layer 30. Further, the semiconductor package structure may further include a rewiring layer 70, specifically, the rewiring layer 70 is located between the first pad and the metal solder ball 60. Further, the semiconductor package structure may further include a second support component 90, wherein the second support component 90 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20 and is in contact with the conductive connection layer 30. Further, the semiconductor package structure further includes an insulating dielectric layer, which fills the hollow area of ​​the printed circuit board 40 and the substrate 10 with at least the power semiconductor chip 20 and the conductive connection layer 30. Furthermore, the semiconductor packaging structure also includes a metal sintering layer, which is located between the power semiconductor chip 20 and the substrate 10, and the above-mentioned metal sintering layer may include a first metal sintering layer 100 and a second metal sintering layer 110. The above-mentioned semiconductor packaging structure may also include a copper gasket layer 120, which is located between the first metal sintering layer 100 and the second metal sintering layer 110, and the first metal sintering layer 100 is located between the copper gasket and the power semiconductor chip 20, and the second metal sintering layer 110 is located between the copper gasket and the substrate 10.

[0049] Specifically, in another exemplary embodiment, the semiconductor package structure includes a driving module, a power module, a conductive connection layer, a first supporting component and a second supporting component, wherein Figure 3As shown, the driving module includes a printed circuit board 40 and a driving circuit 50, and the driving circuit 50 is located on the printed circuit board 40. The power module includes a power semiconductor chip 20 and a substrate 10, and the power semiconductor chip 20 is located on the substrate 10, and the printed circuit board 40 is located on the side of the power semiconductor chip 20 away from the substrate 10. The conductive connection layer 30 is located between the printed circuit board 40 and the power semiconductor chip 20, and is respectively connected to the printed circuit board 40 and the power semiconductor chip 20. The first supporting component 80 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20 and the conductive connection layer 30, respectively. The second supporting component 90 is located between the printed circuit board 40 and the substrate 10, and is spaced apart from the power semiconductor chip 20, and is in contact with the conductive connection layer 30. Further, the semiconductor package structure may further include a metal solder ball 60. Specifically, the power semiconductor chip 20 has a first solder pad, and the conductive connection layer 30 has a second solder pad. The metal solder ball 60 is located between the first solder pad and the second solder pad, and is used to bond the power semiconductor chip 20 to the conductive connection layer 30. Further, the semiconductor package structure may further include a rewiring layer 70. Specifically, the rewiring layer 70 is located between the first solder pad and the metal solder ball 60. Further, the semiconductor package structure may further include a first support member 80 and a second support member 90. The first support member 80 is located between the printed circuit board 40 and the substrate 10, and is spaced from the power semiconductor chip 20 and the conductive connection layer 30, respectively. The second support member 90 is located between the printed circuit board 40 and the substrate 10, and is spaced from the power semiconductor chip 20, and is in contact with the conductive connection layer 30. Further, the semiconductor package structure further includes an insulating dielectric layer, which fills the printed circuit board 40 and the substrate 10 with at least a hollow area except for the power semiconductor chip 20 and the conductive connection layer 30. Further, the semiconductor package structure further includes a metal sintering layer, which is located between the power semiconductor chip 20 and the substrate 10, and the metal sintering layer may include a first metal sintering layer 100 and a second metal sintering layer 110. The semiconductor package structure may further include a copper gasket layer 120, which is located between the first metal sintering layer 100 and the second metal sintering layer 110, and the first metal sintering layer 100 is located between the copper gasket and the power semiconductor chip 20, and the second metal sintering layer 110 is located between the copper gasket and the substrate 10.

[0050] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0051] The semiconductor packaging structure of the present application includes a driving module, a power module and a conductive connection layer, wherein the printed circuit board in the driving module is located on a side of the power semiconductor chip in the power module away from the substrate, the conductive connection layer is located between the printed circuit board (PCB board) of the driving module and the power semiconductor chip of the power module, and the conductive connection layer connects the printed circuit board and the power semiconductor chip respectively. Therefore, compared with the flip-chip welding of the power semiconductor chip directly to the printed circuit board in the prior art, the conductive connection layer between the power semiconductor chip and the printed circuit board serves as a buffer layer, which can avoid the direct connection between the power semiconductor chip and the printed circuit board through the bumps in the flip-chip process, so that the copper layer on the surface of the printed circuit board is not easily damaged, thereby solving the problem of decreased current-carrying capacity of the copper layer on the surface of the PCB caused by flip-chip welding of the chip and the PCB in the prior art.

[0052] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A driving module, comprising a printed circuit board and a driving circuit, wherein the driving circuit is located on the printed circuit board; A power module, comprising a power semiconductor chip and a substrate, wherein the power semiconductor chip is located on the substrate, and the printed circuit board is located on a side of the power semiconductor chip away from the substrate; The conductive connection layer is located between the printed circuit board and the power semiconductor chip, and is connected to the printed circuit board and the power semiconductor chip respectively.

2. The semiconductor package structure according to claim 1, wherein: The power semiconductor chip has a first pad, the conductive connection layer has a second pad, and the semiconductor package structure further includes: A metal solder ball is located between the first solder pad and the second solder pad and is used to bond the power semiconductor chip to the conductive connection layer.

3. The semiconductor package structure according to claim 2, characterized in that: The semiconductor packaging structure further includes: The rewiring layer is located between the first pad and the metal solder ball.

4. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The semiconductor packaging structure further includes: a first supporting member, located between the printed circuit board and the substrate, and spaced apart from the power semiconductor chip and the conductive connection layer respectively; and / or The second supporting component is located between the printed circuit board and the substrate, is spaced apart from the power semiconductor chip, and is in contact with the conductive connection layer.

5. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The driving circuit, the printed circuit board, the conductive connection layer, the power semiconductor chip and the substrate are stacked in sequence.

6. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The power module includes a plurality of power semiconductor chips spaced in pairs on the substrate, the printed circuit board and the substrate have a hollow area at least except for the power semiconductor chips and the conductive connection layer, and the semiconductor packaging structure further includes: An insulating dielectric layer fills the hollow area.

7. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The semiconductor packaging structure further includes: The metal sintering layer is located between the power semiconductor chip and the substrate.

8. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The power semiconductor chip includes a silicon carbide substrate.

9. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The substrate is a silicon carbide substrate.

10. The semiconductor package structure according to any one of claims 9, characterized in that: Liquid metal is embedded in the silicon carbide substrate.

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