Semiconductor die with vertical transistor device
By simultaneously integrating vertical and lateral transistors in the semiconductor die and forming well regions with differences in doping types to achieve junction isolation, the problems of integration complexity and operating performance are solved, and efficient breakdown voltage and low switch-on are achieved resistance.
Patent Information
- Application Number
- CN202410809150.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-21
- Filing Date
- 2024-06-21
- Publication Date
- 2024-12-24
AI Technical Summary
When existing semiconductor dies integrate vertical transistors and lateral transistors, it is difficult to achieve effective junction isolation and optimized operating performance, and the process is complex and difficult to simplify in standard processes.
The vertical transistor and the lateral transistor are simultaneously integrated in the semiconductor body, the source and drain regions of the lateral transistor are made of doping type opposite to the vertical device and are embedded in the well region, which is the source of the vertical device, and are provided with the vertical device. Made of a second doping type opposite to drain doping, junction isolation is achieved through the well region and allows the gate electrode of the lateral device to be simultaneously etched with the gate trenches of the vertical device to simplify the process.
The operational performance optimization of the vertical transistor device is achieved, the integration process is simplified, the process complexity is reduced, and the breakdown voltage is increased and the on-resistance is reduced by embedding the lateral device in the well region.
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Figure CN119181721A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor die including a vertical transistor arrangement. Background Art
[0002] The vertical transistor device has source and drain regions, both made of a first doping type. The source and drain regions are arranged on opposite sides of a semiconductor body, and the vertical current flow is controlled, for example, by a gate region, which is laterally located next to the body region, which is placed in the middle. Summary of the invention
[0003] The object of the present application is to provide an advantageous semiconductor die having a vertical transistor arrangement.
[0004] In addition to the vertical transistor device, the semiconductor die as claimed in claim 1 also comprises a lateral transistor device, which has its source and drain regions on the same side of the semiconductor body. The body region of the lateral device is arranged in the middle in the laterally direction, wherein its gate electrode is placed in the gate trench next to the body region. In other words, although the channel of the lateral device extends in the laterally direction, its gate electrode is formed in the vertical trench. For junction isolation, the lateral device is embedded in a well region, which is made of a second doping type opposite to the source and drain doping of the vertical device.
[0005] Junction isolation can, for example, allow simplified integration in standard processes, e.g. compared to deep trench isolation between vertical and lateral devices. Depending on the detailed implementation, the well region can, for example, require only an additional implant, or can even be formed in the same process step as the region of the vertical device, e.g. simultaneously with the body region of the vertical device. Similar considerations can apply to the gate electrode or gate region of the lateral device, the gate trench can, for example, be etched simultaneously with the gate trench of the vertical device, see below for details, e.g. requiring only an additional gate recess.
[0006] Throughout the present disclosure and in the dependent claims, specific embodiments and features are presented. Thus, independent of the specific claim category, individual features will be disclosed, the present disclosure relates to equipment and device aspects, but also to method and use aspects. If, for example, a tube core manufactured in a specific way is described, this is also a disclosure of the corresponding manufacturing process, and vice versa. In general, the scheme of the present application is to provide a vertical device (in particular, a vertical transistor device) and a further device in the same semiconductor body, wherein the further device is embedded in a well region forming a junction isolation, and the further device is in particular a lateral device, such as a lateral transistor device.
[0007] The lateral device can, for example, allow additional functionalities, for example be used to optimize the operating performance of the vertical device. With reference to the vertical device having its source region on a first side and its drain region on a second side of the semiconductor body, the lateral device can in particular also be arranged on the first side, allowing, for example, wiring with source and / or gate contacts of the vertical device. In other words, the source and drain regions of the lateral device and the source region of the vertical device are arranged on the first side of the semiconductor body, while the drain region of the vertical device is arranged on its second side. Typically, the first side is the front side of the semiconductor body and the second side is the back side thereof.
[0008] "Vertical" or "in a vertical direction" refers to a vertical direction, which is, for example, perpendicular to a surface of a die (e.g., a surface of a substrate or an epitaxial layer formed on a substrate). "Above" means aligned with and closer to a first side or front side of a die in the vertical direction, and "below" means aligned with and closer to a second side or back side in the vertical direction. "Lateral" or "in a lateral direction" refers to a lateral direction perpendicular to the vertical direction, in which, for example, a die area is taken.
[0009] The lateral device is placed in the well region, for example, embedded downward in the lateral direction and in the vertical direction. In the vertical section, the boundary of the well region can, for example, surround (embrace) the lateral device on two lateral sides and toward a portion of the semiconductor body below. With reference to the vertical distance obtained from the first side of the semiconductor body, in particular, if manufactured simultaneously with the main area of the vertical device, the well region can, for example, even have a depth of only less than 1 μm. For illustration, the lateral transistor device in the corresponding shallow well region can, for example, have a breakdown voltage of less than 20V, in particular less than 10V. However, in other embodiments, the well region can have a vertical depth of 1-2 μm, which can achieve a breakdown voltage of, for example, 25V or more. Of course, other breakdown voltages (and p-well depths) are possible according to other circumstances, and the present disclosure contemplates other breakdown voltages.
[0010] The source and drain regions of a vertical device are made of a first doping type, and its body region is made of a second, opposite doping type. The source regions of the vertical and lateral devices can be at the same common potential, see Figure 1or 4 for illustration, or also at different potentials. The vertical device can further comprise a drift region located in the vertical direction between the main region and the drain region, said drift region being made of a first doping type but having a lower doping concentration compared to its drain region. A well region, such as a "first well region", is made of a second doping type opposite to the source and drain regions of the vertical device. It can form a junction isolation in particular towards the drift region of the vertical device, for example adjacent to such a drift region. As described above, the well region can be made simultaneously with the main region of the vertical device (re-use of existing process steps). Alternatively, it can be made, for example, in a separate implantation step, the area of the well region being defined, for example, by an implantation mask. In addition, alternatively, it can be made, for example, by in-situ doping epitaxial deposition after silicon etching in the corresponding area.
[0011] The source and drain regions of the lateral device can be made of the first or second doping type, as described below. For example, the first doping type is n-type and the second doping type is p-type. In other words, the vertical device can in particular be an NMOS, which can be combined with a lateral NMOS or PMOS, wherein the well region is p-doped (and for a lateral PMOS, an additional n-doped well region is required). In an embodiment, the source and drain regions of the lateral device are made of the same doping type as the source and drain regions of the vertical device, the lateral and vertical devices being in particular NMOS devices. In the case where the source and drain regions of the lateral device are made of the first doping type, the well region made of the second doping type can in particular be the only well region required for junction isolation.
[0012] In an embodiment, a portion of the well region forms the body region of the lateral device. In other words, the well region not only provides junction insulation, but also extends between the source and drain regions of the lateral device. However, alternatively, the body region of the lateral device can be made in a further implantation step, which can, for example, allow tuning of the threshold voltage of the lateral device. The body region of the lateral device can also be a combination, such as an implantation on top of a well region implantation, wherein the implantation on top can in particular be a body implantation of a vertical device (same implantation step). The body region can also be a combination of a well of a second doping type (e.g., a well region implantation) and an implantation of a first doping type, which reduces the well doping, for example to reduce the threshold voltage of the lateral device (or, for example, for a depletion mode FET, such as a JFET, even to achieve a negative threshold voltage).
[0013] In a particular embodiment, a second well region made of a first doping type is embedded in a well region made of a second doping type, wherein the lateral device is embedded in the second well region. In other words, the lateral device can be embedded in multiple well regions nested in each other. Generally, in the present disclosure, when a "well region" is mentioned without further explanation, this refers to the first well region made of the second doping type. The second well region can, for example, expand the possibilities of lateral device integration, for example, enabling lateral PMOS.
[0014] The second well region can be manufactured in different ways and with reference to the possibilities discussed above for the first well region, this can also be applied to the second well region. In particular, a nested well region can be obtained by making a first well region of a buried implant that does not reach upwards to the first side (in particular, a buried p-well) in combination with a deep region or a sinker implant extending downwards from the first side to the buried implant. The buried implant forms a lower part defining the well region downwards and the deep or sinker implant forms a border part defining the well region laterally. With the buried implant, the upper second well region can in particular be identical to the drift region of the vertical device, for example by obtaining the second well region by in-situ doping epitaxial deposition, for example by obtaining the second well region without a separate implantation step.
[0015] Typically, a "gate region" can include a gate electrode and a gate dielectric, which applies to both lateral and vertical devices. Likewise, a "field electrode region" includes a field electrode and a field dielectric. While a planar gate is typically envisioned, a gate region for a vertical device can in particular be placed in a gate trench, for example extending from a first side into the semiconductor body.
[0016] In a particular embodiment, the gate electrode of the vertical device disposed in the gate trench extends deeper into the semiconductor body than the gate electrode of the lateral transistor device. In other words, the lower end of the gate electrode of the vertical device is spaced a greater distance from the first side of the semiconductor body than the lower end of the gate electrode of the lateral device. The corresponding shallow lateral gate electrode can, for example, interrupt the vertical current flow and prevent leakage current between the lateral and vertical devices.
[0017] Typically, the gate electrodes of the vertical and lateral devices can be placed in different grooves. However, these different grooves can be arranged into a common primitive pattern, for example, translationally symmetrical relative to each other. However, in a particular embodiment, the gate electrodes of the vertical and lateral devices are placed in different parts of a common continuous groove, for example isolated from each other by an insulating material (e.g., silicon oxide). Integration in a common groove can, for example, allow area optimization.
[0018] In an embodiment, the lateral transistor device comprises a drift region, which can be made of the same doping type but with a lower doping concentration compared to a drain region of the lateral device. Such a drift region is arranged laterally between a body region and a drain region of the lateral device, in particular such a drift region can be provided in combination with a lateral device having a field electrode for field shaping in the drift region. In a particular embodiment, the gate electrode and the field electrode of the lateral device are arranged in the same gate trench, that is to say laterally next to each other in different parts of the gate trench, for example electrically isolated by an intermediate insulating material (e.g. silicon oxide).
[0019] In general, the drift region and the field electrode can increase the breakdown voltage, and / or reduce the on-resistance of the lateral device. The doping, length and thickness of the drift region can be selected to maintain a required breakdown voltage, such as the voltage between the gate and source of a vertical device in the case of a pull-down application discussed below. In this case, as an example, the lateral device can have a breakdown voltage between 25-35V, although lower breakdown voltages can generally be sufficient. Independently of these details, the field electrode of the lateral device can be connected to the gate potential or in particular to the source potential, for example to the source region of the lateral device (e.g., isolated from the vertical source) or in particular to the source region of the vertical device.
[0020] The vertical device can in particular comprise a field electrode extending into a trench in the drift region. Typically, the gate electrode and the field electrode of the vertical device can be arranged in different trenches, for example longitudinal trenches located beside each other, or in particular, a thorn-shaped trench for the field electrode surrounded by a longitudinal trench for the gate electrode. In some embodiments, the field electrode is arranged below the gate electrode of the vertical device in a longitudinal gate trench, the field electrode and the gate electrode being isolated from each other, for example, by an insulating material, for example silicon oxide.
[0021] In an embodiment, the field electrodes of the vertical and lateral devices are arranged in the same trench, that is to say in different parts of the same continuous trench. The field electrode of the vertical device can be arranged below the gate electrode of the vertical device in a first part of the trench, wherein the gate electrode and the field electrode of the lateral device are arranged laterally beside each other in a second part of the trench. In a particular embodiment, the field electrodes of the vertical and lateral devices are made of the same continuous field electrode material, which extends, for example, from the first part to the second part of the trench. For example, over the entire lateral extension of the gate trench, for example in the first and second parts and in between, the lower part of the gate trench can be filled with the same continuous field electrode material.
[0022] The field electrode material may form a field electrode for a vertical device in a first portion of the trench and a field electrode for a lateral device in a second portion of the trench. In an embodiment, the field plate material may reach up to the front side in the second portion. In another embodiment, the field electrode material may not reach all the way up to the front side in the second portion, but may, for example, reach only a bottom portion of the gate trench for the lateral device, while the remaining portion of the gate trench above the field plate material in the second portion may be filled with oxide.
[0023] In case the field electrode material reaches the front side (i.e. extends upwards), it can, for example, be used to form a field electrode connection or to form a field electrode for a lateral device next to its drift region. In a particular embodiment, the field electrode material extends upwards (to reach the front side) in a common trench at a position laterally located between the gate electrodes of the vertical and lateral transistor devices.
[0024] In an embodiment, the buried doped layer is placed below the well region. The buried doped layer is not necessarily directly adjacent to the well region, and there can be a certain vertical distance in between. It can, for example, be formed above the substrate or formed adjacent to the substrate, for example adjacent to the drain region of a vertical device extending as a common drain backside below the lateral device.
[0025] The buried doped layer can in particular be made of the same doping type as the drift region of the vertical device (e.g. a first doping type, in particular an n-type). However, it can have a lower doping concentration than the drift region. In the case where the drift region has a doping profile (e.g. the doping concentration varies over the vertical depth), the doping concentrations are compared at the same vertical height (same distance from the first side). Independently of these details, the buried doped layer can, for example, increase the vertical breakdown voltage maintained below the well region to a value higher than the drain-to-source breakdown voltage of the vertical device, preventing, for example, a pre-major vertical breakdown.
[0026] A buried doped layer can for example be obtained by an implantation of a second doping type which results in a reduction of the concentration of the first doping type (but not inverting it). Such an implantation of a second doping type can for example be a p-implantation introduced into a lightly doped n-layer (e.g. a lightly n-doped epitaxial layer) forming a drift zone in the region of the vertical device. The implantation of the second doping type can for example be a shallow implantation before the growth of one or more epitaxial layers, e.g. in combination with an annealing which results in upward diffusion. Alternatively, the buried doped layer, in particular the implantation of the second doping type, can be implanted before the electrode is formed, through the trench (e.g. obliquely through the gate trench).
[0027] In particular, if the buried doped layer extends below the body region of the vertical device, the body region of the vertical device can be directly adjacent to the well region. However, alternatively, the body region and the well region of the vertical device can be separated by an intermediate gap (e.g., an n-doped region). This can, for example, allow separation of the source regions of the vertical device and the lateral device, for example allowing different source potentials. The size of the gap can depend on the difference in source potentials, for example being larger in the case of a larger potential difference (to avoid breakdown through the gap). Typically, the breakdown voltage of the lateral device can be smaller than the breakdown voltage of the vertical device, which can, for example, be an advantage in high voltage applications, for example allowing the lateral device (or in particular, the pull-down device) to have a lower on-resistance or a smaller area.
[0028] In an embodiment, the lateral device is connected as a pull-down device between the gate electrode of the vertical device and the source region of the vertical device. At a first side of the semiconductor body, the drain region of the lateral pull-down device is connected to the gate electrode of the vertical device, for example, via a metal line / route / interconnect (we will not make such connection directly at the pad). In addition, the vertical device and the lateral pull-down device share a common source connection, and their source regions are connected, for example, via a metal pad or an internal metal interconnect.
[0029] In the event that the gate-to-source voltage of a vertical transistor device increases above a threshold voltage, an induced turn-on can result, while the device should actually be in an off state. This can be prevented by a lateral pull-down device that can be in an on state when the vertical device is off or can be triggered during a fast switching transient that would turn on the vertical device (causing, for example, losses and potential device failure). In such an event, the lateral pull-down device connects the gate electrode of the vertical device to the source region. For this purpose, the lateral pull-down device can typically be controlled externally, for example by connecting its gate electrode via an additional terminal. Alternatively, it can be self-driven, as described below.
[0030] In an embodiment, the gate electrode of the lateral transistor device is connected to a field electrode placed in the trench, for example locally at one end of the field electrode. At its lateral opposite end, the field electrode can, for example, be connected to the source domain. Thus, that is to say, the gate electrode can be connected to the source domain of the vertical device via the resistance of the field electrode, and it can also be connected to the body region of the vertical device. By connecting the open end of the field electrode to the gate electrode, the field electrode can be used to detect changes in the back potential, which are used, for example, to drive the gate of the pull-down transistor. This can in particular allow sensing transients of the back drain potential (for example, due to capacitive coupling between the open end of the field electrode and the back of the common drain). The field electrode used to sense transients can be a field electrode of a vertical or lateral device, in particular, a field electrode material extending in the lower part over the entire length of the gate trench can be used for sensing.
[0031] In an embodiment, the field electrode used for sensing is arranged in a separate field electrode trench which is laterally located next to the gate trench. This can, for example, increase the junction capacitance between the drain region of the vertical device and the lateral gate electrode, for example since the gate of the lateral device is not only connected to this field electrode but also to the body region next to the separate field electrode trench, increasing, for example, the drive strength, since such capacitance is more non-linear (for the same voltage variation, it can carry more current).
[0032] In an embodiment, the well region has a vertical doping profile, e.g., a doping concentration that depends on the vertical depth. In particular, the doping concentration can be higher in the lower portion of the well region than in the upper portion of the well region. The higher doping concentration in the lower portion (e.g., a buried p-well) can, for example, mitigate snapback behavior of parasitic bipolar (in particular, npn) between the drain region of the vertical device and the drain region of the lateral device.
[0033] In an embodiment, a plurality of vertical transistor device cells are formed in a die. Seen in a vertical top view, the device cells can, for example, have a polygonal shape, such as a rectangular or quadratic shape, for example with a needle-shaped field electrode in each cell. Alternatively, the device cells can have a stripe shape, the stripes having, for example, an elongated extension in the longitudinal direction and being arranged in the lateral direction with translational symmetry. Independently of these details, each vertical transistor device cell can in particular have a corresponding lateral device associated therewith, in particular, the corresponding lateral device being placed in the same common trench. Providing each device cell with a corresponding lateral device can, for example, allow consistent switching behavior.
[0034] The present application also relates to a method for manufacturing a semiconductor die disclosed herein, the method comprising the steps of forming vertical and lateral devices and well regions. For further details, reference is made to the above description. The drain and / or particularly the source region of the lateral device can, for example, be made of the same doping type, distribution and / or depth as the source region of the vertical device, and each region can, in particular, be made simultaneously in the same process step. Alternatively, the drain and / or particularly the source region of the lateral device can, for example, extend deeper than the source region of the vertical device and be manufactured using a separate mask.
[0035] As mentioned above, the solution of the present application is to integrate additional devices with the vertical devices in the same die and place the additional devices in the well region. In addition to the lateral transistor device, or in particular as an alternative thereto, a diode can be placed in the well region, such as a lateral diode, whose anode and cathode regions are placed laterally next to each other. The diode can, for example, be used for temperature sensing.
[0036] In summary, a semiconductor die having a semiconductor body will also be disclosed, the semiconductor die including: a vertical transistor device having: a source region and a drain region, located on opposite sides of the semiconductor body; the source region and the drain region are made of a first doping type; the semiconductor die also includes: a diode, the diode having: an anode contact and a cathode contact, located on the same side (front side) of the semiconductor body; wherein the diode is placed in a well region, the well region is made of a second doping type opposite to the first doping type and forms an anode region of the diode.
[0037] The anode contact can for example be connected to a metal pad via a p+ implant.The cathode contact can for example be an n+ implant and can for example be connected via a shallow contact without a recess or just a shallow recess, wherein through such a shallow contact an n+ implant can be done. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In the following, a semiconductor die with vertical and lateral arrangements and production are explained in more detail with the aid of exemplary embodiments, wherein individual features can also be relevant in different combinations.
[0039] Figure 1 A portion of a semiconductor die is shown in a top view with lateral and vertical devices;
[0040] Figure 2 The vertical device is shown in cross-section;
[0041] Figure 3a showing vertical and lateral transistor arrangements sharing a common trench;
[0042] Figure 3b Shown along Figure 3a The profile of the groove;
[0043] Figure 3c Shown is located laterally Figure 3a The section next to the common trench;
[0044] Figure 4 A circuit diagram is shown having a vertical device and a lateral pull-down device connected to the vertical device;
[0045] Figure 5 shows a portion of a die with vertical and lateral devices and illustrates another layout option;
[0046] Figure 6 Another injection option is shown;
[0047] Figure 7 showing a cross section of a lateral device embedded in a second well region;
[0048] Figure 8 The diagram shows the integration of the diode;
[0049] Fig. 9 Summarize some of the manufacturing steps in a flow chart. DETAILED DESCRIPTION
[0050] Figure 1 A portion of a semiconductor die 1 is shown having a vertical transistor arrangement 10 and a lateral transistor arrangement 50. Figure 2 As explained in more detail, the vertical device 10 has its source region 11 on the front side of the semiconductor body, wherein the drain region is arranged Figure 1 In the case of the side device 50, its source region 51 and drain region 52 are both arranged on the front side, see Figure 3a / c. The gate electrode 56 of the lateral device 50 is disposed in the gate trench 59, that is, in the main region 53 ( Figure 3c Although the gate electrode 56 is disposed in the gate trench 59, the channel extends laterally.
[0051] The gate electrode 26 of the vertical device 10 is also disposed in the gate trench 25, wherein the gate trench 59 of the lateral device 50 and the gate trench 25 of the vertical device 10 are different parts of a common continuous trench 69. The vertical device 10 includes a field electrode 27 ( Figure 2 ), where the field electrode material 127 may extend up to the front side locally, that is, between the gate electrodes 26, 56 and at laterally opposite ends of the common trench 69. At one end, it is connected to the source domain, that is, to the source metal pad 75 via a vertical interconnect 227. As discussed above, in some examples, the field electrode material 127 may also not extend up to the front side, but it may be covered by an oxide.
[0052] The source regions of both the vertical device 10 and the lateral device 50 are connected to the same source metal pad 75 via respective interconnects 211, 251. The gate electrode 56 of the lateral device 10 is connected to the field electrode material 127 for capacitively sensing backside transients via interconnects 256, 257 and the lateral gate metal pad 76, as described below. When the lateral device 50 is triggered, it connects the gate electrode 26 of the vertical device 10 to the drain domain of the lateral device 50 via interconnects 226, 252 and the metal plate 77. Figure 4 The circuit diagram discusses the function of this wiring in more detail.
[0053] Figure 2A cross-sectional view of a vertical device 10 is shown, the cross-sectional plane being perpendicular to the longitudinal direction of the gate trench 25. In general, in the present disclosure, similar reference numerals are used for similar elements or elements having similar functions, and in addition, reference is also made to the description of the corresponding other figures. Below the source region 11, the body region 13 is arranged. Laterally beside, a gate electrode 26 is arranged in the gate trench 25 and is capacitively coupled to the body region 13 via a gate dielectric 36 to form a channel 13.1. The channel 13.1 extends in a vertical direction beside the gate trench 25, and the drift region 14 and the drain region 12 are arranged below. In the example shown, the source region, the drain region and the drift region 11, 14, 12 are n-doped, while the body region 13 is p-doped.
[0054] The gate trench 25 extends from the first side 15.1 of the semiconductor body 15 downward into the drift region 14. Below the gate electrode 26, a field electrode 27 is arranged in the gate trench 25, isolated from the drift region 14 and the gate electrode 26 by an insulating material 37. On the front side 15.1, a source metal pad 75 is arranged, electrically isolated from the semiconductor body 15 by an insulating layer 38. The source metal pad 75 is formed in the metallization layer 71, Figure 1 Other metal pads shown in FIG. 7 are also formed in the metallization layer 71. Although only a single metallization layer is shown in this exemplary embodiment, a stack having more than one metallization layer can also be provided.
[0055] Figure 3a -c Figure 3a In the top view and in Figure 3b The lateral means 50 are particularly illustrated in the cross-sectional view in FIG. 6A . The top view illustrates the common continuous groove 69 in which the lateral means 50 are arranged in the first part 69.1 thereof ( Figure 3b ), the first portion 69.1 is also referred to as the gate trench 59 of the lateral device 50. Next to the gate trench 59, the source region 51, the body region 53 and the drain region 52 are arranged, and the drift region 54 is located between the body region 53 and the drain region 52. In the example shown, the body region 53 is p-doped and the other regions are n-doped. Although the gate electrode 56 is arranged in the gate trench 59, the channel region 53.1 formed in the body region 53 next to it extends laterally.
[0056] In the same gate trench 59, a field electrode 57 is arranged laterally beside and isolated from the gate electrode 56, capacitively coupled to the drift region 54. In a second portion 69.2 of the common continuous trench 69, the gate electrode 26 of the vertical device 10 is arranged, with the source region 11 formed laterally beside.
[0057] Figure 3bA cross section through a common continuous trench 69 is shown, in which the gate electrodes 26, 56 are arranged. They are electrically isolated from each other by an insulating material 47, in the example shown, silicon oxide. The gate electrode 26 extends deeper than the gate electrode 56. Below the gate electrode 26, a field electrode 27 made of a field electrode material 127 is arranged. In the lower part of the common continuous trench 69, for example below the gate electrode 56 and laterally beside, the field electrode material 127 extends continuously. Between the gate electrodes 26, 56, the field electrode material 127 can reach up to the first side 15.1 of the semiconductor body 15. This also applies to the other side of the gate electrode 56, at which the field electrode material 127 forms the field electrode 57 of the lateral device 50. In the example shown, the field electrode material 127 is polysilicon.
[0058] Figure 3c The section plane is parallel to Figure 3b , but next to the trench in the semiconductor body 15. The lateral device 50 is embedded in a well region 60, which is made of a second doping type, in this example, a p-type. The well region 60 forms a junction isolation, which is adjacent to the drift region 14. Above, it is adjacent to the body region 13, which reaches up to the first side 15.1 next to the source region 11. In an alternative embodiment, the well region 60 and the body region 13 can be separated from each other by a gap (see Figure 8 ). It can also be used with Figure 3c The doping is done opposite to the indication in , so that the vertical PMOS will be combined with the lateral PMOS.
[0059] Figure 4 The circuit diagram of FIG. 1 shows a vertical device 10, and a lateral device 50 is connected as a pull-down device 150. The drain contact 52.1 of the lateral device 50 is connected to the gate contact 26.1 of the vertical device 10, and the source contact 51.1 is connected to the source domain 311. The gate contact 56.1 of the lateral device 50 is connected to the open end of the field electrode 27 or the field electrode material 127 (via Figure 1 The field electrode 27 or the field electrode material 127 forms one capacitor electrode of the capacitor 227 , the other capacitor electrode being formed by the drain region 12 .
[0060] Via the capacitor 227, transient changes in the back or drain potential can be sensed. For example, in the case of an increased drain potential, the capacitor 227 is charged and, therefore, also the gate electrode 56 of the lateral device 50 is charged. The pull-down device 150 is switched to the on state and connects the gate contact 26.1 of the vertical device 10 to the source domain 311. In a similar manner, the pull-down device 150 is connected to another vertical device or device cell 10.1, which is connected in parallel with the vertical device 10 between the source and drain domains 311, 312. The only difference is that the field plate of the device cell 10.1 is not used for sensing the drain potential, but is directly connected to the source domain 311.
[0061] Figure 5 Shown with Figure 1 Compared to the embodiment with some modifications. Like Figure 1 As in the embodiment, the vertical device 10 and the lateral device 50 are formed with their gate and field electrodes 26, 56; 27, 57 in the same continuous trench 69. In this respect, Figure 5 The layout of Figure 1 The interconnect 257 connecting the open end of the field electrode to the gate domain of the lateral device 50 is Figure 5 Instead, the gate electrode 56 is connected to the separate field electrode 301 in the separate trench 302. This connection is made through the vertical interconnects 256, 303 and via the lateral gate metal pad 76. Figure 1 In contrast, the field electrodes or field electrode material of the devices 10, 50 are not used for sensing back-side transients, but a separate field electrode 301 is provided for this purpose (in Figure 5 , a second sense field electrode is shown and connected in a similar manner, but is not referenced in more detail).
[0062] Via interconnect 376, the body region adjacent to the separating trench 302 is connected to metal pad 76, that is, to gate electrode 56 of lateral device 50. This connection of gate electrode 56 increases the capacitance between the body region and the drift region below in parallel with the capacitance of field electrode 301. This can give a more nonlinear capacitance (stronger drive strength).
[0063] At its opposite end, that is, at Figure 5 At the lower end of the field electrode 301, the field electrode 301 is connected to the source metal pad 75 via the interconnect 304, which gives Figure 4 The source connection of the field plate resistor 290 referenced in FIG.
[0064] Figure 6 Shown with Figure 3c For a cross-sectional view of the vertical device 10 and the doped regions of the lateral device 50, see Figure 6 . Figure 6 Also shown is a buried doped layer 70, which is disposed below the well region 60, for example on the substrate or the drain region 12. The buried doped layer 70 is made of a first doping type (in the example shown, the first doping type is n-type) like the drift region 14, but has a lower doping concentration than the drift region 14.
[0065] Additionally, the doping concentration of the well region 60 is higher in the lower portion 60a of the well region 60 than in the upper portion 60b. In the example shown, this is caused by a deep buried implant 60aa, that is to say a deep buried p implant.
[0066] Figure 7 A further embodiment is shown, in which regards the vertical device 10 reference is made to the above description. Figure 7 The lateral device 50 is a PMOS, whose source and drain regions 51, 52 are p-doped, while the vertical device 10 is still an NMOS. The body region 53 is n-doped, wherein a lightly p-doped drift region 54 is arranged between the body region 53 and the drain region 52. In a first well region 60 made of a second doping type (in this example, p-type), a second well region 62 is arranged. The lateral device 50 (that is, PMOS) is embedded in a second well region 62 made of a first doping type (in the example shown, the first doping type is n-type). Alternatively, the doping can be opposite, for example a vertical PMOS is combined with a lateral NMOS.
[0067] Figure 8 The diode 400 is shown integrated in the well region 60. The cathode contact 401 is formed by an n-implanted region, wherein the well region 60 itself (or in particular, an additional p+ implant) forms the anode contact 402. The diode 400 can be used, for example, for temperature sensing, it can have a relatively low breakdown voltage (e.g., significantly below 10V). In this case, the well region 60 is made without a higher doping concentration in the lower part and can be made at the same time as the body region of the lateral device (without additional process steps), and the deep buried implant discussed above can be omitted. Figure 3c Compared to the embodiment of FIG. 5 , the source, body, drift and drain regions 11 , 13 , 14 , 12 remain unchanged, which can also apply to the well region 60 and the region 52 .
[0068] The well region 60 is laterally separated from the vertical device 10 (that is, its body region 13) by the gap 410. Thus, the anode contact 402 of the diode 400 is separated from the source region 11. For example, a p+ region may be formed as the anode contact 402 in the well region 60. In an alternative embodiment not shown, the gap 410 can be omitted and the anode contact 402 of the diode is in contact with the body region 13 (shared with the body diode of the vertical device).
[0069] Fig. 9 Some manufacturing steps are summarized, that is, the formation 501 of the vertical device 10 , the formation 502 of the well region 60 , and the formation 503 of the lateral device 50 . Fig. 9 The schematic diagram shall not imply a chronological order of the steps, which can overlap or be performed simultaneously, as detailed above.
Claims
1. A semiconductor die (1) having a semiconductor body (15), The semiconductor die (1) comprises: A vertical transistor device (10), the vertical transistor device (10) having: A source region (11) and a drain region (12) located on opposite sides (15.1, 15.2) of the semiconductor body (15); The source region (11) and the drain region (12) are made of a first doping type; The semiconductor die (1) further comprises: A lateral transistor device (50), the lateral transistor device (50) having: A source region (51) and a drain region (52) located on the same side (15.1) of the semiconductor body (15); a body region (53) located laterally between the source region (51) and the drain region (52); and a gate electrode (56); wherein the gate electrode (56) of the lateral transistor device (50) is arranged in a gate trench (59) laterally beside the body (53) region, And wherein the lateral transistor device (50) is arranged in a well region (60), and the well (60) region is made of a second doping type opposite to the first doping type.
2. The semiconductor die (1) of claim 1, wherein the source region (51) and the drain region (52) of the lateral transistor device (50) are made of the first doping type.
3. A semiconductor die (1) as claimed in claim 2, wherein a portion (60.1) of the well region extends between the source region (51) and the drain region (52) of the lateral transistor device (50) and forms the body region (53) of the lateral transistor device (50).
4. The semiconductor die (1) of claim 1, further comprising: a second well region (62) made of the first doping type and embedded in the well region (60); The body region (53) of the lateral transistor device (50) is made of the first doping type.
5. A semiconductor die (1) as claimed in any one of the preceding claims, wherein the gate electrode (26) of the vertical transistor device (10) is arranged in a gate trench (25) and extends deeper in the semiconductor body (15) than the gate electrode (56) of the lateral transistor device (50).
6. A semiconductor die (1) as claimed in any one of the preceding claims, wherein the gate electrode (26) of the vertical transistor device (10) is arranged in a gate trench (25), and the gate trench (25) of the vertical transistor device (10) and the gate trench (59) of the lateral transistor device (50) are different parts (69.1, 69.2) of a common continuous trench (69).
7. The semiconductor die (1) as claimed in any one of the preceding claims, the lateral transistor arrangement (50) further comprising: a drift region (54) made of the same doping type as the drain region (52) of the lateral transistor device (50); and A field electrode (57) is located laterally next to the drift region (54) and is arranged together with the gate electrode (56) in the gate trench (59) of the lateral transistor device (50).
8. The semiconductor die (1) of claims 6 and 7, the vertical transistor arrangement (10) further comprising: a field electrode (27) made of a field electrode material (127) and disposed below the gate electrode (26) of the vertical transistor device (10) in the gate trench (25) of the vertical transistor device (10); wherein the field electrode (57) of the lateral transistor device (50) is made of the same continuous field electrode material (127) as the field electrode of the vertical device (10); and / or The field electrode material (127) extends upwardly in the common trench (69) to a position laterally located between the gate electrode (26) of the vertical transistor device (10) and the gate electrode (56) of the lateral transistor device (50).
9. A semiconductor die (1) as claimed in any one of the preceding claims, further comprising: A buried doping layer (70) is disposed below the well region (60) in a vertical direction; The buried doped layer (70), like the drift region (14) of the vertical device, is made of the first doping type, but has a lower doping concentration than the drift region (14).
10. A semiconductor die (1) as claimed in any one of the preceding claims, wherein the lateral transistor device (50) is connected as a pull-down device (150) between a gate electrode (25) of the vertical transistor device (10) and the source region (11) of the vertical transistor device (10).
11. A semiconductor die (1) as claimed in any one of the preceding claims, wherein the gate electrode (56) of the lateral transistor device (50) is connected to a field electrode (27, 127, 301) arranged in a trench, the field electrode (27) being arranged in particular in a gate trench (25) of the vertical transistor device (10) below the gate electrode (26) of the vertical transistor device (10) and / or being arranged in a common continuous trench (69) together with the gate electrode (56) of the lateral transistor device (50).
12. The semiconductor die (1) of claim 11, wherein the field electrode (301) is arranged in a separate field electrode trench (302) which is laterally located beside the gate trench (59) of the lateral transistor device (50).
13. A semiconductor die (1) as claimed in any one of the preceding claims, wherein the doping concentration of the well region (60) is higher in a lower portion (60a) than in an upper portion (60b).
14. A semiconductor die (1) as claimed in any one of the preceding claims, comprising: A plurality of vertical transistor device cells (10.1); Each vertical transistor device cell (10.1) has a corresponding lateral device (50) associated therewith.
15. A method of manufacturing a semiconductor die (1) as claimed in any one of the preceding claims, the method comprising: - forming said vertical transistor device (10); - forming the well region (60); - forming said lateral transistor device (50).