LDMOS device and preparation method thereof

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof. The LDMOS device comprises a semiconductor substrate; the first well region and the second well region are arranged in the semiconductor substrate, and the first well region and the second well region are arranged adjacently; the body region is arranged in the second well region; the source region is arranged in the body region; the body extraction region and the Schottky region are arranged in the body region and are adjacent to the source region, a metal layer is formed on the Schottky region, and the Schottky region is in contact with the metal layer to form a Schottky diode; the drain region is arranged in the first well region; and the gate structure is formed on the surface of the semiconductor substrate. According to the invention, the device has a lower ESD trigger voltage in an ESD event, and the ESD protection capability of the device is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacture, and in particular relates to an LDMOS device and a preparation method thereof. Background Art

[0002] As the size of integrated circuit (IC) devices continues to shrink, the threat of electrostatic discharge (ESD) to devices is increasing. The transient high voltage generated by ESD events may break through the gate oxide layer of the device, causing device damage. For BCD (Bipolar-CMOS-DMOS) NLDMOS (N-type laterally diffused metal oxide semiconductor) devices, especially 30V-level devices, ESD protection design faces huge challenges under the condition of limited size.

[0003] In an ESD event, the ideal protection mechanism is to absorb energy by first turning on the body diode (Bulk) of the device, thereby preventing the gate oxide layer from being broken down. In ESD protection design, the trigger voltage (Vt1) and the holding voltage (Vh) are two key parameters. For a 30V BCD NLDMOS device, the ESD trigger voltage (Vt1) is usually about 50V, while the Vh voltage is about 40V. In the above ESD situation, it is not possible to effectively turn on the body diode (Bulk) first instead of breaking down and turning on in advance to effectively achieve electrostatic protection. Therefore, in order to improve the ESD protection capability, it is necessary to reduce the trigger voltage (Vt1) and improve the ESD protection capability.

[0004] At present, the industry has proposed a variety of methods to reduce the trigger voltage (Vt1), including optimizing device structure, adjusting layout parameters, using new protection devices, etc. Although some progress has been made in existing research, how to effectively reduce the trigger voltage (Vt1) under the ever-shrinking device size and increasingly stringent performance requirements is still an important research topic in ESD protection design.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an LDMOS device and a method for manufacturing the same, so as to solve the problem of too high ESD trigger voltage (Vt1) in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides an LDMOS device, which includes: a semiconductor substrate of a first conductivity type; a first well region of the first conductivity type and a second well region of the second conductivity type, which are arranged in the semiconductor substrate, and the first well region and the second well region are arranged adjacent to each other; a body region of the second conductivity type, which is arranged in the second well region; a source region of the first conductivity type, which is arranged in the body region; a body lead region of the second conductivity type and a Schottky region of the first conductivity type, which are arranged in the body region and adjacent to the source region, a metal layer is formed on the Schottky region, and the Schottky region contacts the metal layer to form a Schottky diode; a drain region of the first conductivity type, which is arranged in the first well region; and a gate structure, which is formed on the surface of the semiconductor substrate.

[0008] Optionally, the LDMOS device includes a body lead region and a Schottky region, and the Schottky region and the body lead region have the same area.

[0009] Optionally, the LDMOS device includes a plurality of body lead regions and a plurality of Schottky regions that are alternately arranged, and the plurality of Schottky regions and the metal layer thereover form a plurality of Schottky diodes connected in series.

[0010] Optionally, the plurality of Schottky regions are arranged at equal intervals.

[0011] Optionally, one side of the gate structure extends to the surface of the body region and is disposed close to the source region, and the other side extends to the surface of the first well region and has a spacing region between the gate structure and the drain region.

[0012] Optionally, a field plate structure is disposed on the spacing region, and the field plate structure also extends to and covers a portion of the surface of the gate structure.

[0013] Optionally, the doping ion of the body lead region is boron, and the doping dose is e14-e15 cm -2 The doping ions in the Schottky region are phosphorus or arsenic, and the doping dose is e12~e13cm -2 .

[0014] Optionally, an ESD trigger voltage of the LDMOS device is less than or equal to 40 volts.

[0015] The present invention also provides a method for preparing an LDMOS device, comprising the following steps: providing a semiconductor substrate of a first conductivity type, wherein a first well region of the first conductivity type and a second well region of the second conductivity type are formed in the semiconductor substrate, and the first well region and the second well region are adjacently arranged; forming a body region of the second conductivity type in the second well region; forming a source region of the first conductivity type in the body region and a drain region of the first conductivity type in the first well region; forming a body lead region of the second conductivity type and a Schottky region of the first conductivity type in the body region, the body lead region and the Schottky region are adjacently arranged, a metal layer is formed on the body lead region and the Schottky region, and the Schottky region contacts the metal layer to form a Schottky diode; and forming a gate structure on the surface of the semiconductor substrate.

[0016] Optionally, a body lead-out region of the second conductivity type and a Schottky region of the first conductivity type are formed in the body region, including the steps of: performing ion implantation of the second conductivity type into the body region through a first mask to form a body lead-out region of the second conductivity type in the body region; performing ion implantation of the first conductivity type into the body lead-out region through a second mask to invert a portion of the body lead-out region to form a Schottky region.

[0017] As described above, the LDMOS device and the method for manufacturing the same according to the present invention have the following beneficial effects:

[0018] The present invention embeds a parasitic Schottky diode in the body lead region of the semiconductor device, transforms the ohmic contact part of the original body lead region into a reverse Schottky diode, greatly increases the equivalent resistance of the original body lead region, and thus can significantly reduce the trigger voltage (Vt1) of the device. The present invention will also appropriately reduce the holding voltage (Vh) of the device, so that the trigger voltage (Vt1) and the holding voltage (Vh) are maintained within a certain voltage difference range to ensure that the device can effectively discharge static electricity when an ESD event occurs, and will not be falsely triggered under normal working conditions. The present invention can make the device have a lower ESD trigger voltage in an electrostatic discharge (ESD) event, greatly improving the electrostatic discharge (ESD) protection capability of the device. The present invention can keep the device at a lower power consumption under normal operating conditions, and improve the overall performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0020] Figure 1-2 It is a schematic structural diagram of the LDMOS device according to the first embodiment of the present invention.

[0021] Figure 3-4It is a schematic structural diagram of an LDMOS device according to Embodiment 2 of the present invention.

[0022] Figure 5 Schematic diagram of an equivalent circuit showing the structure of the LDMOS device of Embodiment 1 or 2 of the present invention

[0023] Component number description

[0024] 101 Semiconductor Substrate

[0025] 102 First Well Region

[0026] 103 Second well region

[0027] 104 Body Area

[0028] 105 Source Area

[0029] 106 Body lead-out area

[0030] 107 Schottky region

[0031] 108 Drain area

[0032] 109 Gate Structure

[0033] 110 Field Plate Layer

[0034] 111 Field electrode layer

[0035] 112 N-type buried layer

[0036] 113 Shallow Trench Isolation Structure DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0039] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0040] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0041] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0042] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] Example 1

[0045] like Figure 1-2 As shown, this embodiment provides an LDMOS device, which includes: a semiconductor substrate 101 of a first conductivity type, a first well region 102 of a first conductivity type and a second well region 103 of a second conductivity type, a body region 104 of a second conductivity type, a source region 105 of a first conductivity type, a body lead region 106 of a second conductivity type and a Schottky region 107 of a first conductivity type, a drain region 108 of a first conductivity type and a gate structure 109.

[0046] In this embodiment, the first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type. Of course, in other embodiments, the first conductivity type may also be a P-type conductivity type, and the second conductivity type may be an N-type conductivity type.

[0047] like Figure 1As shown, in one embodiment, the semiconductor substrate 101 of the first conductivity type may be, for example, a silicon substrate, a germanium substrate, a germanium silicon substrate, a III-V compound substrate, etc., and is not limited to the examples listed here. In this embodiment, the semiconductor substrate 101 is a silicon substrate.

[0048] like Figure 1 As shown, in one embodiment, a first well region 102 of a first conductivity type and a second well region 103 of a second conductivity type are disposed in a semiconductor substrate 101, and the first well region 102 and the second well region 103 are disposed adjacent to each other. In this embodiment, the first well region 102 is an N-well, which can be doped by implanting N-type ions (such as phosphorus, arsenic, etc.) through an ion implantation process. The second well region 103 is a P-well, which can be doped by implanting P-type ions (such as boron, etc.) through an ion implantation process.

[0049] like Figure 1 As shown, in one embodiment, an N-type buried layer 112 (NBL) is further provided between the semiconductor substrate 101 and the first well region 102 and the second well region 103. On the one hand, the N-type buried layer 112 is added between the drift region (N-well), the P-well and the semiconductor substrate 101 to maintain the stability of the device under high voltage. On the other hand, the N-type buried layer 112 can help reduce the concentration of the electric field at the edge of the device and reduce the risk of breakdown due to the concentration of the electric field. In addition, by adjusting the doping concentration and thickness of the N-type buried layer 112, the electric field distribution can be adjusted, thereby optimizing the performance of the device.

[0050] like Figure 1 As shown, in one embodiment, the second conductive type body region 104 is disposed in the second well region 103; the ion doping type of the body region 104 is the same as the ion doping type of the second well region 103, both of which are P-type ion (boron, etc.) doping. The ion doping concentration of the body region 104 can be greater than the ion doping concentration of the second well region 103.

[0051] like Figure 1 As shown, in one embodiment, a source region 105 of the first conductivity type is disposed in the body region 104. The source region 105 can be formed by performing N-type ion implantation (such as phosphorus, arsenic, etc.) in the body region 104.

[0052] like Figure 1As shown, in one embodiment, a second conductive type body lead region 106 and a first conductive type Schottky region 107 are disposed in the body region 104 and adjacent to the source region 105. A metal layer (not shown) is formed on the body lead region 106 and the Schottky region 107. The Schottky region 107 contacts the metal layer to form a Schottky diode. The body lead region 106 can be formed by performing P-type ion implantation in the body region 104, and its doping concentration is greater than the doping concentration of the body region 104. The Schottky region 107 can be formed by performing N-type ion implantation in the body lead region 106 to invert a portion of the body lead region 106 to an N-type. In this embodiment, the body lead region 106 is heavily doped with P-type, and the Schottky region 107 is lightly doped with N-type. In a specific example, the doping ion of the body lead region 106 is boron, and its doping dose is e14-e15cm -2 The doping ions of Schottky region 107 are phosphorus or arsenic, and the doping dose is e12~e13cm -2 The present invention embeds a parasitic Schottky diode in the body lead region 106 of the semiconductor device, transforms the ohmic contact portion of the original body lead region 106 into a reverse Schottky diode, greatly increases the equivalent resistance of the original body lead region 106, and thus can significantly reduce the trigger voltage (Vt1) of the device. The present invention can make the device have a lower ESD trigger voltage in an electrostatic discharge (ESD) event, greatly improving the electrostatic discharge (ESD) protection capability of the device.

[0053] like Figure 2 As shown, in one embodiment, the LDMOS device includes a body lead region 106 and a Schottky region 107, and the area of ​​the Schottky region 107 is equal to that of the body lead region 106, thereby increasing the effective area of ​​the Schottky diode while ensuring normal lead-out of the body region.

[0054] like Figure 1 As shown, in one embodiment, a drain region 108 of the first conductivity type is disposed in the first well region 102. The drain region 108 can be formed by performing N-type ion implantation (such as phosphorus, arsenic, etc.) in the first well region 102, wherein the drain region 108 can be implanted and formed simultaneously with the source region 105 using the same mask to simplify the process steps.

[0055] like Figure 1As shown, in one embodiment, the gate structure 109 is formed on the surface of the semiconductor substrate 101. The gate structure 109 may include, for example, a gate oxide layer and a polysilicon layer located on the gate oxide layer. In a specific example, one side of the gate structure 109 extends to the surface of the body region 104 and is arranged close to the source region 105, and the other side extends to the surface of the first well region 102, and there is a spacing region between the drain region 108. In one embodiment, a field plate structure is arranged on the spacing region, and the field plate structure also extends and covers a portion of the surface of the gate structure 109, and the field plate structure includes a field plate layer 110 and a field electrode layer 111 located on the field plate layer 110.

[0056] In one embodiment, the LDMOS device further includes a shallow trench isolation structure 113 disposed on both sides of the LDMOS device for isolation from other devices.

[0057] Figure 5 The equivalent circuit diagram of the LDMOS device of this embodiment is shown as follows: Figure 5 It can be seen that the parasitic Schottky diode is embedded in the body lead region 106 of the semiconductor device, and the ohmic contact part of the original body lead region 106 is transformed into a reverse Schottky diode. Because the parasitic Schottky diode (SBD) is in the body, the equivalent resistance of the branch is increased (the equivalent resistance is increased to the sum of the resistance of R-HVPB and the reverse Schottky diode SBD), the parasitic BJT capability is enhanced, and the conductivity of the device is more easily triggered. Specifically, as Figure 5 As shown, the reverse Schottky element is parasitic on the emitter and base of the Q1 BJT, which is equivalent to the reverse bias element of the Schottky being embedded in VBE (the voltage between the base and the emitter); because the Schottky diode has a reverse high-resistance characteristic, the equivalent resistance at the end of the body diode (Bulk) increases, which leads to a decrease in the turn-on voltage of Q1 and makes it easier for the BJT to turn on, thereby achieving the effect of reducing Vt1 and Vh of the NLDMOS device and improving the ESD protection capability.

[0058] As shown in Table 1, compared with the traditional LDMOS device (Baseline), the new component trigger voltage (Vt1) and holding voltage (Vh) of the LDMOS device (Newlayout) of the present invention are reduced, and the electrostatic protection capability (It2) is greatly increased, so that the high-voltage ESD protection device has better performance. In this embodiment, by embedding a parasitic Schottky diode in the body lead region 106, the ESD trigger voltage of the LDMOS device is less than or equal to 40 volts.

[0059] Table 1

[0060]

[0061] like Figure 1-2As shown, this embodiment also provides a method for preparing an LDMOS device, the preparation method comprising the following steps:

[0062] Step 1) provides a semiconductor substrate 101 of a first conductivity type, wherein a first well region 102 of a first conductivity type and a second well region 103 of a second conductivity type are formed in the semiconductor substrate 101 , and the first well region 102 and the second well region 103 are adjacent to each other.

[0063] Step 2), forming a body region 104 of the second conductivity type in the second well region 103 .

[0064] Step 3), forming a source region 105 of the first conductivity type in the body region 104 and forming a drain region 108 of the first conductivity type in the first well region 102 .

[0065] In step 4), a body lead region 106 of the second conductivity type and a Schottky region 107 of the first conductivity type are formed in the body region 104. The body lead region 106 and the Schottky region 107 are adjacent to the source region 105. A metal layer is formed on the body lead region 106 and the Schottky region 107. The Schottky region 107 contacts the metal layer to form a Schottky diode.

[0066] Step 5), forming a gate structure 109 on the surface of the semiconductor substrate 101 .

[0067] In one embodiment, a body lead-out region 106 of a second conductivity type and a Schottky region 107 of a first conductivity type are formed in the body region 104, including the steps of: performing ion implantation of the second conductivity type into the body region 104 through a first mask to form a body lead-out region 106 of a second conductivity type in the body region 104; performing ion implantation of the first conductivity type into the body lead-out region 106 through a second mask to invert a portion of the body lead-out region 106 to form a Schottky region 107.

[0068] In one embodiment, one side of the gate structure 109 extends to the surface of the body region 104 and is disposed close to the source region 105, and the other side extends to the surface of the first well region 102 and has a spacing region between the gate structure 109 and the drain region 108. The preparation method further includes the steps of: preparing a field plate structure on the gate structure 109 and the spacing region, the field plate structure also extends to and covers a portion of the surface of the gate structure 109, and the field plate structure includes a field plate layer 110 and a field electrode layer 111 located on the field plate layer 110.

[0069] Example 2

[0070] like Figure 3-4As shown, this embodiment provides an LDMOS device and a method for preparing the same, wherein the basic structure and main preparation steps are as in Embodiment 1, wherein the difference from Embodiment 1 is that the LDMOS device includes a plurality of body lead-out regions 106 and a plurality of Schottky regions 107 that are alternately arranged, and the plurality of Schottky regions 107 and the metal layer above them form a plurality of Schottky diodes connected in series.

[0071] In one embodiment, the plurality of Schottky regions 107 are arranged at equal intervals.

[0072] In this embodiment, multiple Schottky regions 107 are embedded into the body lead region 106, and the multiple Schottky regions 107 and the metal layer above them form multiple series-connected Schottky diodes (multiple reverse Schottky diodes in an ESD event), thereby further increasing the equivalent resistance of the circuit branch, further enhancing the parasitic BJT capability, and greatly increasing the electrostatic protection capability of the LDMOS device.

[0073] As described above, the LDMOS device and the method for manufacturing the same according to the present invention have the following beneficial effects:

[0074] The present invention embeds a parasitic Schottky diode in the body lead region of the semiconductor device, transforms the ohmic contact part of the original body lead region into a reverse Schottky diode, greatly increases the equivalent resistance of the original body lead region, and thus can significantly reduce the trigger voltage (Vt1) of the device. The present invention will also appropriately reduce the holding voltage (Vh) of the device, so that the trigger voltage (Vt1) and the holding voltage (Vh) are maintained within a certain voltage difference range to ensure that the device can effectively discharge static electricity when an ESD event occurs, and will not be falsely triggered under normal working conditions. The present invention can make the device have a lower ESD trigger voltage in an electrostatic discharge (ESD) event, greatly improving the electrostatic discharge (ESD) protection capability of the device. The present invention can keep the device at a lower power consumption under normal operating conditions, and improve the overall performance and reliability of the device.

[0075] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An LDMOS device, characterized in that: The LDMOS device comprises: a semiconductor substrate of a first conductivity type; A first well region of a first conductivity type and a second well region of a second conductivity type are arranged in the semiconductor substrate, and the first well region and the second well region are arranged adjacent to each other; A body region of a second conductivity type, disposed in the second well region; A source region of a first conductivity type is disposed in the body region; A body lead region of the second conductivity type and a Schottky region of the first conductivity type are arranged in the body region and adjacent to the source region, a metal layer is formed on the Schottky region, and the Schottky region contacts the metal layer to form a Schottky diode; A drain region of a first conductivity type, disposed in the first well region; A gate structure is formed on the surface of the semiconductor substrate.

2. The LDMOS device according to claim 1, characterized in that: The LDMOS device includes a body lead region and a Schottky region, and the Schottky region has the same area as the body lead region.

3. The LDMOS device according to claim 1, characterized in that: The LDMOS device includes a plurality of the body lead regions and a plurality of Schottky regions that are alternately arranged, and the plurality of Schottky regions and the metal layer thereover form a plurality of Schottky diodes connected in series.

4. The LDMOS device according to claim 3, characterized in that: The multiple Schottky regions are arranged at equal intervals.

5. The LDMOS device according to claim 1, characterized in that: One side of the gate structure extends to the surface of the body region and is arranged close to the source region, and the other side extends to the surface of the first well region and has a spacing region between the gate structure and the drain region.

6. The LDMOS device according to claim 5, characterized in that: A field plate structure is disposed on the spacing region, and the field plate structure also extends to and covers a portion of the surface of the gate structure.

7. The LDMOS device according to claim 1, characterized in that: The doping ion of the body lead region is boron, and its doping dose is e14~e15cm -2 The doping ions of the Schottky region are phosphorus or arsenic, and the doping dose is e12-e13cm -2 .

8. The LDMOS device according to claim 1, characterized in that: The ESD trigger voltage of the LDMOS device is less than or equal to 40 volts.

9. A method for preparing an LDMOS device, characterized in that: Includes steps: Providing a semiconductor substrate of a first conductivity type, wherein a first well region of the first conductivity type and a second well region of a second conductivity type are formed in the semiconductor substrate, and the first well region and the second well region are adjacently arranged; forming a body region of a second conductivity type in the second well region; forming a source region of a first conductivity type in the body region and forming a drain region of the first conductivity type in the first well region; A body lead region of the second conductivity type and a Schottky region of the first conductivity type are formed in the body region, the body lead region and the Schottky region are arranged adjacent to the source region, a metal layer is formed on the Schottky region, and the Schottky region contacts the metal layer to form a Schottky diode; A gate structure is formed on the surface of the semiconductor substrate.

10. The LDMOS device according to claim 9, characterized in that: A body lead region of a second conductivity type and a Schottky region of a first conductivity type are formed in the body region, comprising the steps of: Performing ion implantation of a second conductivity type into the body region through a first mask to form a body lead-out region of the second conductivity type in the body region; Ions of the first conductivity type are implanted into the body lead-out region through a second mask, so that a portion of the body lead-out region is inverted to form a Schottky region.

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