High dynamic adjustment method for receiving digital phased array with zero intermediate frequency architecture

Abstract

The present application discloses a method for adjusting the reception of a digital phased array with a zero intermediate frequency architecture, and relates to the field of radar communication technology. The method comprises: determining the current execution time slot of the digital phased array; if the execution time slot is a receiving time slot, performing digital domain detection on the target frame header data of the target signal to determine the target reception mode and the target reception gain of the digital phased array; configuring the radio frequency transceiver unit in the digital phased array according to the target reception mode and the target reception gain, that is, adjusting the reception mode and the reception gain of the radio frequency transceiver unit in the digital phased array with a zero intermediate frequency architecture according to the received target signal, so as to realize automatic high dynamic adjustment of reception according to the target signal, and avoid the receiving channel being in an oversaturated state or a signal-free state.

Description

Technical Field

[0001] The present application relates to the field of radar communication technology, and in particular to a high-dynamic adjustment method for receiving a zero-IF architecture digital phased array. Background Art

[0002] A digital phased array is a fully digital phased array that digitally processes the signals of each transceiver channel to achieve full digitalization of the transmission waveform generation and reception signal processing. Amplitude and phase weighting in the digital domain can make beamforming more flexible and accurate.

[0003] At present, the zero-IF digital phased array mainly uses the zero-IF chip to adjust the phase and amplitude of each antenna unit, and radiates beams of different directions in space. However, the signal amplitude range that the zero-IF digital phased array can process will be affected by the working performance of the zero-IF chip. If a signal with a large amplitude needs to be received, the digital phased array will be oversaturated due to the excessive signal strength, or the digital phased array will not be able to recognize the signal due to the low signal strength, thus limiting the signal strength range that the zero-IF digital phased array can receive.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of this application is to provide a high-dynamic adjustment method for receiving a zero-IF architecture digital phased array, aiming to solve the technical problem that the signal amplitude range that can be processed by the digital phased array is affected by the working performance of the zero-IF architecture chip, thereby limiting the strength range of the signal that the digital phased array can receive.

[0006] To achieve the above objectives, the present application proposes a high dynamic adjustment method for receiving a zero intermediate frequency architecture digital phased array, the method comprising:

[0007] Determine the current execution time slot of the digital phased array;

[0008] If the execution time slot is a receiving time slot, performing digital domain detection on the target frame header data of the target signal to determine the target receiving mode and target receiving gain of the digital phased array;

[0009] According to the target receiving mode and the target receiving gain, a radio frequency transceiver unit in the digital phased array is configured.

[0010] In one embodiment, the step of performing digital domain detection on target frame header data of the target signal to determine the target receiving mode and target receiving gain of the digital phased array includes:

[0011] Performing digital detection processing on target frame header data of the target signal to obtain the signal strength of the target signal;

[0012] Based on a preset AGC threshold and the signal strength, determining whether the radio frequency transceiver unit needs to adjust the receiving mode;

[0013] If it is determined that the receiving mode needs to be adjusted, a target receiving gain that needs to be adjusted is determined based on the target signal.

[0014] In one embodiment, if it is determined that the receiving mode needs to be adjusted, the step of determining the target receiving gain that needs to be adjusted based on the target signal includes:

[0015] If it is determined that the receiving mode needs to be adjusted, the target signal is digitally detected again to obtain an actual power value of the target signal;

[0016] A target receiving gain that needs to be adjusted is determined based on the actual power value.

[0017] In one embodiment, the receiving mode includes a noise amplification mode and an attenuation mode, and the step of determining whether the RF transceiver unit needs to adjust the receiving mode based on the preset AGC threshold and the signal strength includes:

[0018] Determine whether the signal strength is greater than a preset AGC threshold;

[0019] If the signal strength is greater than or equal to the preset AGC threshold, adjusting the receiving mode of the radio frequency transceiver unit to the attenuation mode;

[0020] If the signal strength is less than the preset AGC threshold, the receiving mode of the radio frequency transceiver unit is adjusted to the noise amplification mode.

[0021] In one embodiment, the RF transceiver unit includes a RF switch and a digital attenuator, and if the signal strength is greater than or equal to the preset AGC threshold, the step of adjusting the receiving mode of the RF transceiver unit to the attenuation mode includes:

[0022] If the signal strength is greater than or equal to the preset AGC threshold, the receiving link in the RF transceiver unit is adjusted to a link between a RF switch and a digital attenuator, and the link between the RF switch and the digital attenuator is a link for realizing the attenuation mode.

[0023] In one embodiment, the radio frequency transceiver unit further includes a low noise amplifier, and if the signal strength is less than the preset AGC threshold, the step of adjusting the receiving mode of the radio frequency transceiver unit to the noise amplification mode further includes:

[0024] If the signal strength is less than the preset AGC threshold, the receiving link in the RF transceiver unit is adjusted to a link of RF switch, low noise amplifier and digital attenuator, and the link of RF switch, low noise amplifier and digital attenuator is a link to realize the noise amplification mode.

[0025] In one embodiment, before the step of determining the current execution time slot of the digital phased array, the step further includes:

[0026] The receiving mode of the radio frequency transceiver unit in the digital phased array is adjusted to a noise amplification mode, and the receiving gain of the radio frequency transceiver unit is adjusted to a maximum gain.

[0027] In addition, to achieve the above-mentioned purpose, the present application also proposes an adjustment device for a digital phased array based on a zero intermediate frequency architecture, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the receiving high dynamic adjustment method for a zero intermediate frequency architecture digital phased array as described above.

[0028] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the high dynamic adjustment method for receiving a zero intermediate frequency architecture digital phased array are implemented as described above.

[0029] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the high dynamic adjustment method for receiving a zero intermediate frequency architecture digital phased array as described above.

[0030] One or more technical solutions proposed in this application have at least the following technical effects:

[0031] Since the zero-IF architecture chip will limit the range of signal amplitude, in order to reduce the range limitation of signal amplitude, when receiving the signal, the receiving mode and receiving gain are configured for the RF transceiver unit in the digital phased array, that is, the target frame header of the target signal is first digitally detected to determine the target receiving mode and target receiving gain of the RF transceiver unit, so as to flexibly adjust the RF transceiver unit according to the target receiving mode and target receiving gain of the target signal. Therefore, by adjusting the receiving mode and receiving gain of the RF transceiver unit according to the received target signal, automatic reception high dynamic adjustment can be achieved according to the target signal, thereby avoiding the receiving channel being in an oversaturated state or a no signal state. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0034] Figure 1 A flowchart diagram of Embodiment 1 of the method for high dynamic adjustment of receiving of a zero intermediate frequency architecture digital phased array of the present application is provided;

[0035] Figure 2 A flowchart diagram of Embodiment 2 of the method for high dynamic adjustment of receiving of a digital phased array with a zero intermediate frequency architecture of the present application is provided;

[0036] Figure 3 This is the hardware block diagram of the RF transceiver unit in the digital phased array system of this application;

[0037] Figure 4 A flowchart diagram of Embodiment 3 of the method for high dynamic adjustment of receiving of a digital phased array with a zero intermediate frequency architecture of the present application is provided;

[0038] Figure 5 Schematic diagram of the device structure of the hardware operating environment involved in the high dynamic adjustment method for receiving a zero intermediate frequency architecture digital phased array in an embodiment of the present application.

[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0041] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0042] The main solution of the embodiment of the present application is: determine the current execution time slot of the digital phased array through the phased array controller; if the execution time slot is a receiving time slot, perform digital domain detection on the target frame header data of the target signal to determine the target receiving mode and target receiving gain of the digital phased array; configure the RF transceiver unit in the digital phased array according to the target receiving mode and the target receiving gain.

[0043] The present application provides a solution. Since the zero-IF architecture chip will limit the range of signal amplitude, in order to reduce the range limitation of the signal amplitude, when a signal is received, the receiving mode and receiving gain are configured for the RF transceiver unit in the digital phased array, that is, the target frame header of the target signal is first digitally detected to determine the target receiving mode and target receiving gain of the RF transceiver unit, so as to flexibly adjust the RF transceiver unit according to the target receiving mode and target receiving gain of the target signal. Therefore, by adjusting the receiving mode and receiving gain of the RF transceiver unit according to the received target signal, automatic reception high-dynamic adjustment is achieved according to the target signal, thereby avoiding the receiving channel being in an oversaturated state or a no-signal state.

[0044] It should be noted that the execution subject of this embodiment may be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a phased array controller, etc. The following takes the phased array controller as an example to illustrate this embodiment and the following embodiments.

[0045] Based on this, the embodiment of the present application provides a high dynamic adjustment method for receiving a digital phased array with a zero intermediate frequency architecture, referring to Figure 1 , Figure 1 1 is a flow chart of a first embodiment of a method for high dynamic adjustment of a receiving digital phased array with a zero intermediate frequency architecture according to the present invention.

[0046] In this embodiment, the high dynamic adjustment method for receiving a zero intermediate frequency digital phased array includes steps S10 to S30:

[0047] Step S10, determining the current execution time slot of the digital phased array;

[0048] It should be noted that the digital phased array can be a multi-channel digital phased array based on AD9361. The execution time slot can be a task that the digital phased array needs to perform in the current time slot, such as receiving a signal or sending a signal. Among them, AD9361 can be a high-performance, low-power, software-defined zero-IF architecture RF transceiver chip.

[0049] It should be noted that a phased array can be composed of multiple antenna units, which are arranged in a certain pattern. By controlling the phase and amplitude of each antenna unit, directional radiation and reception of electromagnetic waves can be achieved. In the transmitting mode, by precisely controlling the phase of the transmitted signal of each antenna unit, the electromagnetic waves can be superimposed in phase in a specific direction in space, thereby enhancing the radiation power in that direction, while in other directions, they may be destructively superimposed, weakening the radiation, so as to quickly change the direction of the beam without moving the physical position of the antenna. In the receiving mode, electromagnetic waves from different directions will produce different phase differences on the antenna unit. By measuring and processing these phase differences, the direction of the signal can be determined, and the phase can be adjusted to make the antenna receive the signal in a specific direction optimally. A digital phased array can be a phased array that uses digital processing technology to control the phase and amplitude of each antenna unit.

[0050] In a specific implementation, after the digital phased array system is powered on, the control signal processing unit, the RF transceiver unit, and the RF calibration unit are initialized. After determining that the digital phased array system has performed receiving and transmitting calibration, the current execution time slot is determined according to the current task requirements.

[0051] Step S20, if the execution time slot is a receiving time slot, performing digital domain detection on the target frame header data of the target signal to determine the target receiving mode and target receiving gain of the digital phased array;

[0052] It should be noted that the receiving time slot may be the time point when the digital phased array system needs to receive the signal. The target signal may be the signal received by the digital phased array system. The receiving mode may include a small signal receiving mode and a large signal receiving mode; wherein, the small signal may be a signal whose target signal power is less than a preset division threshold. For example, -40dBm is set as the preset division threshold. When the power of the received target signal is less than -40dBm, the received signal is considered to be a small signal, and the small signal receiving mode may be used to receive the signal; the large signal may be a signal whose power is greater than or equal to the preset division threshold. The preset division threshold is determined based on the instantaneous dynamic range of the selected zero intermediate frequency architecture chip.

[0053] It can be understood that when the execution time slot is a receiving time slot, the receiving mode and receiving gain corresponding to the target signal are configured for the RF transceiver unit to dynamically adjust the receiving mode and receiving gain of the RF transceiver unit according to the target signal, so that when the RF transceiver unit receives the target signal, the transmission channel will not be oversaturated due to the excessive transmission power of the target signal, and the target signal cannot be received normally due to the transmission power of the target signal being too small.

[0054] In a specific implementation, when determining that the execution time slot is a receiving time slot, the signal strength of the target signal can be first determined based on the information of the target signal, so as to determine the target receiving mode and the target receiving gain required to receive the target signal based on the signal strength, so as to facilitate the subsequent determination of the link required to receive the target signal based on the target receiving mode, and determine the antenna gain required to receive the target signal based on the target receiving gain.

[0055] Step S30, configuring a radio frequency transceiver unit in the digital phased array according to the target receiving mode and the target receiving gain;

[0056] It is understandable that since the target receiving mode corresponds to the power range of the received target signal, after determining the target receiving mode, further digital detection is required to determine the actual power of the target signal and adjust the target receiving gain to avoid a reduction in the quality of the signal received by the digital phased array.

[0057] It is understandable that, since different receiving modes correspond to different power ranges, it is necessary to configure the RF transceiver unit according to the target receiving mode and the target receiving gain so that the RF transceiver unit can be flexibly adjusted according to different target signals.

[0058] The present embodiment provides a method for high-dynamic adjustment of reception of a digital phased array with a zero intermediate frequency architecture. Since a zero intermediate frequency architecture chip will limit the range of signal amplitude, in order to reduce the range limitation of the signal amplitude, when a signal is received, a receiving mode and a receiving gain are configured for the RF transceiver unit in the digital phased array, that is, a target frame header of the target signal is firstly detected in the digital domain to determine the target receiving mode and the target receiving gain of the RF transceiver unit, so as to flexibly adjust the RF transceiver unit according to the target receiving mode and the target receiving gain of the target signal. Therefore, by adjusting the receiving mode and the receiving gain of the RF transceiver unit according to the received target signal, automatic high-dynamic adjustment of reception is achieved according to the target signal, thereby avoiding the receiving channel being in an oversaturated state or a signal-free state.

[0059] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 2 , step S20 also includes steps S01 to S03:

[0060] Step S01, performing digital detection processing on target frame header data of a target signal to obtain a signal strength of the target signal;

[0061] It should be noted that digital detection can be the process of extracting the modulated signal from the modulated signal, that is, performing mathematical operations on the signal to extract useful information. For example, in wireless communication, the modulated signal reaches the receiving end after transmission, and the receiving end uses digital detection technology to extract the original modulated signal from the received signal. Signal strength can refer to the power level of the wireless signal, usually expressed in decibel milliwatts (dBm).

[0062] It is understandable that the target signal is digitally detected to extract the original unmodulated signal from the target signal before the transmitter transmits the target signal, so as to determine the signal strength of the target signal based on the original signal, thereby making the determined signal strength more accurate.

[0063] Step S02, judging whether the radio frequency transceiver unit needs to adjust the receiving mode based on a preset AGC threshold and the signal strength;

[0064] It should be noted that the preset AGC (Automatic Gain Control) threshold may be a range of automatic gain.

[0065] It can be understood that since the receiving mode includes a large signal mode and a small signal mode, the RF transceiver unit can set a default receiving mode, and determine whether the RF transceiver unit needs to adjust the receiving mode based on the signal strength and the preset AGC threshold, so as to realize flexible adjustment of the receiving mode according to the signal strength, that is, flexible adjustment of the transmission link required for transmitting the target signal according to the signal strength, so as to avoid the transmission link used not being able to meet the signal strength of the target signal.

[0066] Step S03: If it is determined that the receiving mode needs to be adjusted, a target receiving gain that needs to be adjusted is determined based on the target signal.

[0067] It can be understood that after the receiving mode is adjusted, the receiving gain of the corresponding transmission link also needs to be adjusted. Therefore, after determining the target receiving mode that needs to be adjusted for the RF transceiver unit, the target receiving gain that needs to be adjusted for the transmission channel (transmission link) is further determined so that the transmission channel corresponding to the target receiving mode meets the signal strength of the target signal, thereby avoiding the signal transmission channel from being in an oversaturated state.

[0068] Furthermore, the receiving mode includes a noise amplification mode (small signal mode) and an attenuation mode (large signal mode), and the step S02 further includes:

[0069] Determine whether the signal strength is greater than a preset AGC threshold;

[0070] If the signal strength is greater than or equal to the preset AGC threshold, adjusting the receiving mode of the radio frequency transceiver unit to the attenuation mode, and reconfiguring the receiving gain corresponding to the receiving mode;

[0071] If the signal strength is less than the preset AGC threshold, the receiving mode of the radio frequency transceiver unit is adjusted to the noise amplification mode.

[0072] It is understandable that the RF transceiver unit can set the small signal mode as the default mode. When the signal strength is greater than the preset AGC threshold, it means that the transmission link corresponding to the default mode cannot meet the signal strength required by the target signal during transmission. In order to avoid the transmission channel being in an oversaturated state, the receiving mode of the RF transceiver unit needs to be adjusted to the attenuation mode.

[0073] It is understandable that in order to ensure the optimization of the small signal noise coefficient, when the signal strength is less than or equal to the preset AGC threshold, if the default mode of the RF transceiver unit is the small signal mode, there is no need to adjust the receiving mode, and only the required receiving gain needs to be determined based on the signal strength.

[0074] Further, refer to Figure 3 The RF transceiver module also includes an RF switch, a low noise amplifier, a digitally controlled attenuator, etc. Among them, the link composed of AD9361_TX (RF transceiver chip_transmit), low noise amplifier 2, RF switch 2, RF switch 1, and RF B represents the transmission mode; the link composed of RF B, RF switch 1, RF switch 2, RF switch 3, digitally controlled attenuator, and RF transceiver chip_receive represents the large signal mode (attenuation mode); the link composed of RF B, RF switch 1, low noise amplifier 1, RF switch 3, digitally controlled attenuator, and RF transceiver chip_receive represents the small signal mode (noise amplification mode). It should be noted that after the large dynamic compression of the reception is achieved through the RF switch, the optimal reception sampling range of AD9361 is met, and the original dynamic range of 60dB is increased to 95dB.

[0075] Further, if the signal strength is greater than or equal to the preset AGC threshold, the step of adjusting the receiving mode of the radio frequency transceiver unit to the attenuation mode includes:

[0076] If the signal strength is greater than or equal to the preset AGC threshold, the receiving link in the RF transceiver unit is adjusted to a link between a RF switch and a digital attenuator, and the link between the RF switch and the digital attenuator is a link for realizing the attenuation mode.

[0077] It can be understood that since the digital attenuator can adjust the amplitude of the signal through digital control, that is, the signal strength can be adjusted to adapt to different transmission distances and signal quality requirements. In order to enable the digital phased array to receive higher-power signals, and since the amplitude adjustment of the signal through the digital attenuator is limited, the RF switch can be controlled to allow the received signal to pass through the digital attenuator, and the amplitude of the large signal can be adjusted through the digital attenuator to increase the dynamic range of the digital phased array and enable the digital phased array to receive high-power signals that exceed a certain range of the upper limit of its own signal strength.

[0078] Furthermore, if the signal strength is less than the preset AGC threshold, the step of adjusting the receiving mode of the radio frequency transceiver unit to the noise amplification mode also includes:

[0079] If the signal strength is less than the preset AGC threshold, the receiving link in the RF transceiver unit is adjusted to a link of RF switch, low noise amplifier and digital attenuator, and the link of RF switch, low noise amplifier and digital attenuator is a link to realize the noise amplification mode.

[0080] It can be understood that since the low noise amplifier is used to amplify weak input signals and maintain the noise level as low as possible, in order to increase the power of the digital phased array receiving signal while being able to normally receive small signals with weak signal strength, after determining that the signal strength is less than the preset AGC threshold, the RF switch is adjusted to allow the received signal to pass through the low noise amplifier, so as to utilize the low noise amplifier to amplify the signal and reduce the noise in the signal, thereby achieving clear reception of small signals.

[0081] Exemplarily, in order to help understand the implementation process of the high dynamic adjustment method for receiving a zero intermediate frequency architecture digital phased array obtained by combining this embodiment with the above embodiments, specifically:

[0082] After the digital phased array system performs receiving and transmitting calibration, the transmitting time slot and receiving time slot are selected according to system needs; if the receiving time slot is selected, the RF transceiver unit is first configured to a small signal receiving mode with the receiving gain as the maximum. After the signal processing unit digitally detects the power, the required receiving mode and receiving gain of the RF transceiver unit are determined by comparing with the AGC threshold, and the receiving mode and receiving gain of the RF transceiver unit are reconfigured until the detection power is within the set threshold, the AGC loop is exited, and the target receiving mode and target receiving gain are obtained, so that the RF transceiver unit is configured according to the target receiving mode and target receiving gain.

[0083] Based on the first and second embodiments of the present application, in the third embodiment of the present application, the same or similar contents as those in the above embodiments can be referred to the above introduction, and will not be described in detail later. Figure 4 Before step S10, the zero intermediate frequency architecture digital phased array receiving high dynamic adjustment method further includes step S1:

[0084] Step S1, adjusting the receiving mode of the radio frequency transceiver unit in the digital phased array to a noise amplification mode, and adjusting the receiving gain of the radio frequency transceiver unit to a maximum gain.

[0085] It is understandable that in order to ensure that the system can detect small signals, the initial state of the RF transceiver module needs to be configured to receive small signal mode, and the receiving gain needs to be configured to be maximum. When the target signal is detected to be a large signal, the RF switch in the RF transceiver module is adjusted so that the RF transceiver module can receive large signals.

[0086] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the high dynamic adjustment method for receiving a digital phased array with a zero intermediate frequency architecture of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0087] The present application provides an adjustment device for a digital phased array based on a zero intermediate frequency architecture, and the adjustment device for a digital phased array based on a zero intermediate frequency architecture includes: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the high dynamic adjustment method for receiving a digital phased array with a zero intermediate frequency architecture in the above-mentioned embodiment 1.

[0088] Reference below Figure 5 , which shows a schematic diagram of the structure of a digital phased array adjustment device based on a zero intermediate frequency architecture suitable for implementing the embodiment of the present application. The digital phased array adjustment device based on a zero intermediate frequency architecture in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The adjustment device of the digital phased array based on the zero intermediate frequency architecture shown is only an example and should not bring any limitation to the function and scope of use of the embodiments of the present application.

[0089] like Figure 5As shown, the adjustment device of the digital phased array based on the zero intermediate frequency architecture may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM: Read Only Memory) 1002 or the program loaded from the storage device 1003 to the random access memory (RAM: Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the adjustment device of the digital phased array based on the zero intermediate frequency architecture are also stored. The processing device 1001, the ROM 1002 and the RAM 1004 are connected to each other through a bus 1005. The input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the adjustment device of the digital phased array based on the zero intermediate frequency architecture to communicate with other devices wirelessly or by wire to exchange data. Although the figure shows the adjustment device of the digital phased array based on the zero intermediate frequency architecture with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0090] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0091] The adjustment device of the digital phased array based on the zero intermediate frequency architecture provided in the present application adopts the high dynamic adjustment method for receiving the digital phased array with the zero intermediate frequency architecture in the above-mentioned embodiment, which can solve the technical problem that the signal amplitude range that the digital phased array can process will be affected by the working performance of the phase shifter, limiting the intensity range of the signal that the digital phased array can receive. Compared with the prior art, the beneficial effects of the adjustment device of the digital phased array based on the zero intermediate frequency architecture provided in the present application are the same as the beneficial effects of the high dynamic adjustment method for receiving the digital phased array with the zero intermediate frequency architecture provided in the above-mentioned embodiment, and the other technical features of the adjustment device of the digital phased array based on the zero intermediate frequency architecture are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0092] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0093] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0094] The present application provides a computer-readable storage medium having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the receiving high dynamic adjustment method of the zero intermediate frequency architecture digital phased array in the above-mentioned embodiment.

[0095] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0096] The computer-readable storage medium may be included in the adjustment device of the digital phased array based on the zero intermediate frequency architecture; or may exist independently without being assembled into the adjustment device of the digital phased array based on the zero intermediate frequency architecture.

[0097] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the adjustment device of the digital phased array based on the zero intermediate frequency architecture, the adjustment device of the digital phased array based on the zero intermediate frequency architecture is: applied to a phased array controller, and the phased array controller is used to control the RF transceiver unit in the digital phased array, and the RF transceiver unit includes a transmission channel; specifically: determine the current execution time slot of the digital phased array; if the execution time slot is a receiving time slot, determine the target receiving mode and target receiving gain configured for the RF transceiver unit to receive the target signal; based on the target receiving mode and the target receiving gain, retrieve the receiving compensation value required for transmitting the target signal; configure the RF transceiver unit according to the target receiving mode and the target receiving gain, and adjust the phase amplitude required for the transmission channel to receive the target signal according to the receiving compensation value.

[0098] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0099] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0100] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0101] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned zero intermediate frequency architecture digital phased array receiving high dynamic adjustment method, which can solve the technical problem that the signal amplitude range that can be processed by the digital phased array is affected by the working performance of the phase shifter, limiting the strength range of the signal that can be received by the digital phased array. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the zero intermediate frequency architecture digital phased array receiving high dynamic adjustment method provided in the above-mentioned embodiment, and will not be repeated here.

[0102] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-mentioned method for high dynamic adjustment of reception of a zero intermediate frequency architecture digital phased array.

[0103] The computer program product provided by the present application can solve the technical problem that the signal amplitude range that can be processed by the digital phased array is affected by the working performance of the phase shifter, which limits the strength range of the signal that can be received by the digital phased array. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the high dynamic adjustment method for receiving the zero intermediate frequency architecture digital phased array provided by the above embodiment, and will not be repeated here.

[0104] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for adjusting the receiving dynamics of a zero intermediate frequency digital phased array, characterized in that: The method includes: Determine the current execution time slot of the digital phased array; If the execution time slot is a receiving time slot, performing digital domain detection on the target frame header data of the target signal to determine the target receiving mode and target receiving gain of the digital phased array; According to the target receiving mode and the target receiving gain, configuring a radio frequency transceiver unit in the digital phased array, wherein the radio frequency transceiver unit includes a radio frequency switch and a digital attenuator; The step of performing digital domain detection on the target frame header data of the target signal to determine the target receiving mode and the target receiving gain of the digital phased array comprises: Performing digital detection processing on target frame header data of the target signal to obtain the signal strength of the target signal; Based on a preset AGC threshold and the signal strength, determining whether the radio frequency transceiver unit needs to adjust a receiving mode, wherein the receiving mode includes a noise amplification mode and an attenuation mode; If it is determined that the receiving mode needs to be adjusted, determining a target receiving gain that needs to be adjusted based on the target signal; The step of judging whether the radio frequency transceiver unit needs to adjust the receiving mode based on the preset AGC threshold and the signal strength includes: Determine whether the signal strength is greater than a preset AGC threshold; If the signal strength is greater than or equal to the preset AGC threshold, adjusting the receiving link in the radio frequency transceiver unit to be a link between a radio frequency switch and a digital attenuator, wherein the link between the radio frequency switch and the digital attenuator is a link for realizing the attenuation mode; If the signal strength is less than the preset AGC threshold, the receiving mode of the radio frequency transceiver unit is adjusted to the noise amplification mode.

2. The method according to claim 1, characterized in that If it is determined that the receiving mode needs to be adjusted, the step of determining the target receiving gain that needs to be adjusted based on the target signal includes: If it is determined that the receiving mode needs to be adjusted, the target signal is digitally detected again to obtain an actual power value of the target signal; A target receiving gain that needs to be adjusted is determined based on the actual power value.

3. The method according to claim 1, characterized in that The radio frequency transceiver unit further includes a low noise amplifier, and if the signal strength is less than the preset AGC threshold, the step of adjusting the receiving mode of the radio frequency transceiver unit to the noise amplification mode further includes: If the signal strength is less than the preset AGC threshold, the receiving link in the RF transceiver unit is adjusted to a link of RF switch, low noise amplifier and digital attenuator, and the link of RF switch, low noise amplifier and digital attenuator is a link to realize the noise amplification mode.

4. The method according to claim 1, characterized in that The step of determining the current execution time slot of the digital phased array also includes: The receiving mode of the radio frequency transceiver unit in the digital phased array is adjusted to a noise amplification mode, and the receiving gain of the radio frequency transceiver unit is adjusted to a maximum gain.

5. A digital phased array adjustment device based on a zero intermediate frequency architecture, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the method for high dynamic adjustment of reception of a zero intermediate frequency architecture digital phased array according to any one of claims 1 to 4.

6. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the high dynamic adjustment method for receiving a zero intermediate frequency architecture digital phased array are implemented as described in any one of claims 1 to 4.

7. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the method for high dynamic adjustment of reception of a zero intermediate frequency architecture digital phased array according to any one of claims 1 to 4 are implemented.

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