Semiconductor test equipment and test method
By using a driving unit and a bridge circuit in the test channel of a semiconductor test device, a voltage test signal containing three levels is generated, which solves the problems of parallel test reduction and cost increase caused by multiple test channels in the prior art, and realizes the problem of "similarity" and "substantial testing" and "substantial testing" More efficient testing efficiency.
Patent Information
- Application Number
- CN202411500752.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2024-12-27
AI Technical Summary
Existing semiconductor test equipment needs to use multiple test channels when it is necessary to provide three level signals, resulting in a decrease in the number of chips that can be tested in parallel, increasing test time and cost.
A semiconductor test device is designed to generate voltage test signals including three levels in a single test channel, including logic low level, logic high level and Reference voltage.
This increases the number of chips that a single test device can be tested in parallel, reduces the testing cost and improves the testing efficiency.
Smart Images
Figure CN119199453A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor chip testing, and in particular to a semiconductor testing device and a testing method. Background Art
[0002] After semiconductor devices are manufactured, they need to be tested to eliminate defective products. Semiconductor testing equipment, such as automatic test equipment ATE (Automatic Test Equipment), can be used to identify and verify the performance of the manufactured semiconductor devices.
[0003] ATE is used to simulate the operating conditions that the device under test (DUT) will experience in the application, monitor the response of the DUT, and make a pass or fail judgment by comparing the test value with the expected value.
[0004] ATE contains multiple test channels, and one test channel is generally used to test one pin of a chip. The input pins of digital chips generally require the test equipment to simulate two level signals, namely the logic high level voltage VIH and the logic low level voltage VIL. A test channel can generally provide two voltage outputs, VIH and VIL.
[0005] But there are a few scenarios where you need to provide three levels to the input pin, such as Figure 5 As shown, the test equipment needs to simulate Figure 5 In the waveform shown, the HSCL pin has two levels, but the HSDA pin has three levels, namely low level (0), high level (1, corresponding to VDD) and mid-VCC between the two. For example, the mid-VCC voltage is VDD / 2.
[0006] In this case, two test channels are usually required to provide three levels for testing one pin. Taking the HSPA pin as an example, one test channel provides low level 0 and high level VDD, and the other test channel provides low level 0 and mid-level mid-VCC.
[0007] Assume that the test equipment has 32 test channels in total and a chip has 8 input pins to be tested. If each input pin only requires two levels, then a chip only needs 8 test channels. In this way, a test equipment can test 4 chips at the same time.
[0008] If each input pin requires three levels, according to the above solution, one chip needs 16 test channels, and one test device can only test two chips at the same time, which greatly reduces the number of chips that can be tested in parallel, resulting in an increase in test time and test costs.
[0009] How to increase the number of chips that can be tested in parallel, improve test efficiency, and reduce test costs is a problem that is waiting to be solved. Summary of the invention
[0010] One of the purposes of the present invention is to provide a semiconductor testing device and a testing method in view of the problems existing in the prior art.
[0011] The technical solution provided by the present invention is as follows:
[0012] A semiconductor testing device, comprising:
[0013] At least one test channel, used for testing a tested pin of the device under test;
[0014] The test channel includes:
[0015] A driving unit, used to output a corresponding low driving voltage when the input signal is a logic low level, and output a corresponding high driving voltage when the input signal is a logic high level, and when its input terminal is suspended, the output terminal is in a high impedance state;
[0016] A first switch, a second switch and a third switch; an input end of the first switch is connected to the driving unit, and an output end is connected to the tested pin;
[0017] a bridge circuit, wherein a first node is connected to a first current source through the second switch, a second node is connected to an output end of the first switch, a third node is connected to a second current source through the third switch, and a fourth node is connected to a reference voltage;
[0018] A switch control unit is connected to the control ends of the first switch, the second switch and the third switch, respectively, and is used to control the first switch to be closed and the second switch and the third switch to be opened when an input test is performed; and is used to control the first switch to be opened and the second switch and the third switch to be closed when an output test is performed.
[0019] In some embodiments, it includes: a third digital-to-analog converter connected to the third node of the bridge circuit, for providing the reference voltage.
[0020] In some embodiments, including:
[0021] A first digital-to-analog converter, connected to the driving unit, and configured to provide the low driving voltage to the driving unit;
[0022] The second digital-to-analog converter is connected to the driving unit and is used to provide the high driving voltage to the driving unit.
[0023] In some embodiments, the bridge circuit includes a first diode to a fourth diode, wherein the anode of the first diode is connected to the anode of the fourth diode to form the first node; the cathode of the first diode is connected to the anode of the second diode to form the second node; the cathode of the second diode is connected to the cathode of the third diode to form the third node; the anode of the third diode is connected to the cathode of the fourth diode to form the fourth node.
[0024] The present invention further provides a method for testing a semiconductor device, which is applied to the semiconductor testing device described in any of the above embodiments, comprising:
[0025] Obtaining a test instruction for a test channel of the semiconductor test equipment;
[0026] Acquire input signal information of the driving unit of the test channel and input signal information of the switch control unit according to the test instruction;
[0027] When the current test is determined to be an input test according to the input signal information of the switch control unit, the test channel generates a voltage test signal including three levels according to the following rules:
[0028] If the input signal of the driving unit indicates a logic low level, a low driving voltage VIL is output;
[0029] If the input signal of the driving unit indicates a logic high level, a high driving voltage VIH is output;
[0030] If the input signal of the driving unit indicates that the input terminal is suspended, a reference voltage Vref is output;
[0031] The voltage test signal including three levels is applied to the tested pin of the device under test.
[0032] In some embodiments, before obtaining the test instruction, the process includes:
[0033] Setting low drive voltage and high drive voltage;
[0034] Sets the reference voltage.
[0035] The semiconductor testing device and testing method provided by the present invention can at least bring the following beneficial effects:
[0036] The present invention provides voltages corresponding to two logic levels through a driving unit of a test channel, and provides a voltage corresponding to a third logic level through a reference voltage of a bridge circuit, thereby realizing that a voltage test signal containing three levels is provided to a tested pin of a device under test through a single test channel, thereby increasing the number of chips that can be tested in parallel using a single test device, reducing test costs, and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The preferred implementation scheme will be described below in a clear and understandable manner in conjunction with the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of a semiconductor testing device and a testing method.
[0038] Figure 1 It is a structural schematic diagram of a test channel of a semiconductor test device of the present invention;
[0039] Figure 2 is a structural schematic diagram of an embodiment of a semiconductor testing device of the present invention;
[0040] Figure 3 is a circuit structure schematic diagram of another embodiment of a semiconductor testing device of the present invention;
[0041] Figure 4 is a flow chart of an embodiment of a semiconductor testing method of the present invention;
[0042] Figure 5 It is a schematic diagram of a voltage test signal waveform. DETAILED DESCRIPTION
[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.
[0044] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".
[0045] One embodiment of the present invention, as Figure 1-2 As shown, a semiconductor testing device comprises:
[0046] A control module 100 and n test channels 200, n>=1. Each test channel is used to test a tested pin of the device under test DUT. The control module 100 receives a command from the host computer, executes a corresponding test program according to the command, controls the start of each test channel, sends a test instruction to it, generates a test signal to apply to the DUT, and collects the response from the DUT.
[0047] For example, if the device under test is a NOT gate, test channel 1 is connected to the input pin of the DUT, and test channel 2 is connected to the output pin of the DUT. To perform a functional test on the NOT gate, the control module controls test channel 1 to generate a voltage test signal and apply it to the input pin of the DUT, and controls test channel 2 to collect the signal on the output pin of the DUT, obtain the response value of the DUT, compare it with the expected value, and make a pass or fail judgment.
[0048] The test channel 200 includes a voltage test signal generator 210 , a second switch 221 , a third switch 222 , a switch control unit 220 , and a bridge circuit 230 . The voltage test signal generator 210 includes a driving unit 211 and a first switch 212 .
[0049] When the input signal Vin of the driving unit is symbol 0 (indicating a logic low level), the driving unit 211 outputs a corresponding low driving voltage VIL; when the input signal Vin is symbol 1 (indicating a logic high level), the driving unit outputs a corresponding high driving voltage VIH; when the input signal Vin is symbol X (indicating that the input terminal is suspended, i.e., float), the driving unit is set in a high output impedance mode, i.e., the output terminal is in a high impedance state. In actual use, 2 bits can be used to represent the symbols 0, 1, and X.
[0050] The driving unit is connected to the tested pin of the DUT through the first switch.
[0051] The first node of the bridge circuit 230 is connected to one end of the first current source IOL through the second switch, and the other end of the first current source is grounded; the second node is connected to the output end of the first switch, the third node is connected to one end of the second current source IOH through the third switch, and the other end of the second current source is grounded; the fourth node is connected to the reference voltage Vref.
[0052] The switch control unit 220 is connected to the control ends of the first switch, the second switch and the third switch, respectively, and is used for switching between input test and output test. When the test is an input test, the first switch is controlled to be closed, and the second and third switches are disconnected; when the test is an output test, the first switch is controlled to be disconnected, and the second and third switches are closed. The input test provides a test signal for the tested pin, and the output test is used to measure the output signal provided by the tested pin.
[0053] For example, the switch control unit generates a first control signal and a second control signal according to its input signal IOswitch, and the first control signal and the second control signal are inverted. The first control signal is connected to the control end of the first switch, and the second control signal is connected to the control ends of the second switch and the third switch respectively. Assuming that IOswitch is at a low level, it indicates that the input test is valid, and at a high level, it indicates that the output test is valid. When IOswitch is at a low level, the first control signal is at a high level, controlling the first switch to close, and the second control signal is at a low level, controlling the other two switches to open; when IOswitch is at a high level, the first control signal is at a low level, controlling the first switch to open, and the second control signal is at a high level, and the second and third switches are closed.
[0054] Specifically, the driving unit is generally used to provide a voltage test signal including two levels in an input test.
[0055] The bridge circuit is generally used to provide a current load in the output test, acting as a load for the output terminal of the DUT, and providing a current IOL from the test equipment to the DUT or a current IOH from the DUT to the test equipment. When the voltage at the output terminal of the DUT is greater than the reference voltage Vref, IOH provides current; when the voltage at the output terminal of the DUT is less than the reference voltage Vref, IOL provides current. Generally, a bridge circuit is not required in the input test.
[0056] In order to generate a voltage test signal including three levels, in the input test, this embodiment uses a driving unit to provide voltages corresponding to two of the logic levels, such as the voltage VIL corresponding to the logic low level and the voltage VIH corresponding to the logic high level, and also uses a bridge circuit to provide a voltage corresponding to the third logic level, namely, the reference voltage Vref.
[0057] When the test is an input test, the first switch is closed, the second switch and the third switch are open, the first node and the third node of the bridge circuit are not connected to the current source, and the bridge circuit does not provide current to the DUT, but can provide voltage to the DUT. If the input end of the driving unit is suspended at this time, the driving unit is in the output high impedance mode, and the output end of the driving unit will not affect the voltage of the second node of the bridge circuit, then the voltage of the second node of the bridge circuit will be equal to the reference voltage Vref, so at this time the bridge circuit will provide the voltage Vref to the tested pin of the DUT.
[0058] In the above manner, the semiconductor test equipment can generate a voltage test signal including three levels through one test channel.
[0059] To provide Figure 5 Taking the voltage test signal of the HSDA pin shown as an example, the pin is required to output 0V, 1V, and 2V voltages.
[0060] use Figure 3 The semiconductor testing equipment shown in the figure only presents the structure of the test channel 1, while other test channels are not presented. The test channel 1 is used to test the HSDA pin of the DUT.
[0061] Figure 3 In the embodiment, the bridge circuit includes a first diode D1 to a fourth diode D4, wherein the anode of the first diode D1 is connected to the anode of the fourth diode D4 to form a first node; the cathode of the first diode D1 is connected to the anode of the second diode D2 to form a second node; the cathode of the second diode D2 is connected to the cathode of the third diode D3 to form a third node; the anode of the third diode D3 is connected to the cathode of the fourth diode D4 to form a fourth node. The first node of the bridge circuit is connected to the first current source IOL through the second switch, the second node is connected to the output end of the first switch, the third node is connected to the second current source IOH through the third switch, and the fourth node is connected to the reference voltage Vref.
[0062] The voltage test signal generator 210 includes a driving unit and a first switch (not shown), the output end of the driving unit is connected to one end of the first switch, and the other end of the first switch is used as the output end of the voltage test signal generator. The driving unit outputs a corresponding driving voltage VIL or VIH according to the logic level of the input signal Driver, and the control end of the first switch is connected to the inverted signal of the signal I / O. When the signal I / O is at a logic low level, the first switch is controlled to close, indicating that the input test is valid.
[0063] The signal I / O is connected to the control end of the second switch via a diode, and is connected to the control end of the third switch via another diode. When the signal I / O is at a logic low level, the second switch and the third switch are disconnected. When the signal I / O is at a logic high level, it indicates that the output test is valid, and the second switch and the third switch are closed.
[0064] To perform input test, provide voltage test signal to HSDA pin. It is necessary to pre-set voltage VIH=2V, VIL=0V, Vref=1V.
[0065] The signal I / O (ie, the input signal of the switch control unit) is set to a logic low level 0, indicating that the input test is valid.
[0066] According to the way that the symbol 1 corresponds to VIH, 0 corresponds to VIL, and X corresponds to Vref, Figure 5 The voltage waveform of the HSDA pin shown in the figure controls the change of the signal Driver (i.e., the input signal of the drive unit), so that the test channel 1 can generate Figure 5 The voltage test signal of the HSDA pin is shown.
[0067] In one embodiment, a third digital-to-analog converter is further included, connected to the third node of the bridge circuit, and configured to provide a reference voltage Vref. Figure 3 shown.
[0068] The input end of the third digital-to-analog converter can be connected to the control module, so that it is easy to adjust the required reference voltage value through the digital-to-analog converter to achieve programmable reference voltage.
[0069] In one embodiment, the first digital-to-analog converter is connected to the driving unit and used to provide a low driving voltage VIL to the driving unit; the second digital-to-analog converter is connected to the driving unit and used to provide a high driving voltage VIH to the driving unit. Figure 3 shown.
[0070] The input ends of the first and second digital-to-analog converters can be connected to the control module, so that it is easy to adjust the required high / low driving voltage values through the digital-to-analog converters to achieve programmable high / low driving voltage values.
[0071] One embodiment of the present invention, as Figure 4 As shown, a semiconductor testing method is applied to the semiconductor testing device described in any of the above embodiments, comprising:
[0072] Step S100 sets voltage parameters, including a low drive voltage value VIL, a high drive voltage value VIH and a reference voltage value Vref; sets input circuit information and control circuit information;
[0073] Step S200 obtains a test instruction for a test channel of a semiconductor test device;
[0074] Step S300: Read input circuit information and control circuit information according to the test instruction, obtain information of input signal Vin of the driving unit of the test channel from the input circuit information, and obtain information of input signal IOswitch of the switch control unit from the control circuit information;
[0075] Step S400: When the current test is determined to be an input test according to the information of the input signal IOswitch of the switch control unit, the test channel generates a voltage test signal including three levels according to the following rules:
[0076] If the input signal Vin of the driving unit indicates a logic low level 0, a low driving voltage VIL is output;
[0077] If the input signal Vin of the driving unit indicates a logic high level 1, a high driving voltage VIH is output;
[0078] If the input signal Vin of the driving unit indicates that the input terminal is suspended, the reference voltage Vref is output;
[0079] Step S500 applies a voltage test signal including three levels to a tested pin of the device under test.
[0080] Specifically, required voltage parameters are preset, for example, VIL, VIH and Vref are set according to the input test requirements of the device under test DUT, and these three voltages correspond to voltages corresponding to three required levels respectively.
[0081] Set input circuit information and control circuit information. The control circuit information is used to control whether the current test is an input test or an output test, for example, to set the input signal information of the switch control unit. The input circuit information is used to control the circuit behavior of the test channel providing the test signal to the DUT. In this embodiment, it includes: according to the rule that the symbol 1 corresponds to VIH, 0 corresponds to VIL, and X corresponds to Vref, the input signal information of the driving unit is designed according to the required voltage test signal waveform.
[0082] The input circuit information and the control circuit information may be pre-stored in the memory.
[0083] According to the test command for the test channel from the control module, the input circuit information and control circuit information are obtained from the memory, input testing is performed, each switch is controlled according to the control circuit information, and the test channel is controlled according to the input circuit information to generate the required test signal and apply it to the pin under test.
[0084] It should be noted that the above embodiments can be freely combined as needed. The above are only preferred embodiments of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.
Claims
1. A semiconductor testing device, characterized in that: include: At least one test channel, used for testing a tested pin of the device under test; The test channel includes: A driving unit, used to output a corresponding low driving voltage when the input signal is a logic low level, and output a corresponding high driving voltage when the input signal is a logic high level, and when its input terminal is suspended, the output terminal is in a high impedance state; A first switch, a second switch and a third switch; an input end of the first switch is connected to the driving unit, and an output end is connected to the tested pin; a bridge circuit, wherein a first node is connected to a first current source through the second switch, a second node is connected to an output end of the first switch, a third node is connected to a second current source through the third switch, and a fourth node is connected to a reference voltage; A switch control unit is connected to the control ends of the first switch, the second switch and the third switch, respectively, and is used to control the first switch to be closed and the second switch and the third switch to be opened when an input test is performed; and is used to control the first switch to be opened and the second switch and the third switch to be closed when an output test is performed.
2. The semiconductor testing device according to claim 1, characterized in that: include: The third digital-to-analog converter is connected to the third node of the bridge circuit and is used to provide the reference voltage.
3. The semiconductor testing device according to claim 1, characterized in that include: A first digital-to-analog converter, connected to the driving unit, and configured to provide the low driving voltage to the driving unit; The second digital-to-analog converter is connected to the driving unit and is used to provide the high driving voltage to the driving unit.
4. The semiconductor testing device according to claim 1, characterized in that The bridge circuit includes a first diode to a fourth diode, wherein the anode of the first diode is connected to the anode of the fourth diode to form the first node; the cathode of the first diode is connected to the anode of the second diode to form the second node; the cathode of the second diode is connected to the cathode of the third diode to form the third node; the anode of the third diode is connected to the cathode of the fourth diode to form the fourth node.
5. A method for testing a semiconductor device, applied to the semiconductor testing device according to any one of claims 1 to 4, characterized in that: include: Obtaining a test instruction for a test channel of the semiconductor test equipment; Acquire input signal information of the driving unit of the test channel and input signal information of the switch control unit according to the test instruction; When the current test is determined to be an input test according to the input signal information of the switch control unit, the test channel generates a voltage test signal including three levels according to the following rules: If the input signal of the driving unit indicates a logic low level, a low driving voltage VIL is output; If the input signal of the driving unit indicates a logic high level, a high driving voltage VIH is output; If the input signal of the driving unit indicates that the input terminal is suspended, a reference voltage Vref is output; The voltage test signal including three levels is applied to the tested pin of the device under test.
6. The method according to claim 5, characterized in that Before getting the test instructions, include: Setting low drive voltage and high drive voltage; Sets the reference voltage.