A method, system and device for locating faults in functional testing of CLB modules

Abstract

The present invention relates to the field of FPGA chip testing technology, and in particular to a method, system and device for locating functional test faults of a CLB module. The method comprises: dividing a CLB module into blocks according to test requirements, performing a rapidity test on the CLB module, judging whether the CLB module passes the rapidity test, and sending the test information to the host computer if the rapidity test is passed, and the test is terminated. If the test is not passed, the fault block where the fault is located is determined; the fault block where the fault is located is divided to obtain the divided fault block; the divided fault block is precisely searched for the fault to determine the coordinates of the fault point. The present invention detects the CLB module using the IP core of the FIFO, thereby solving the technical problem that the CLB module detection is too slow, achieving the technical effect of improving the test efficiency, and is suitable for mass production FPGA batch testing.

Description

Technical Field

[0001] The present invention relates to the field of FPGA chip testing technology, and in particular to a method, system and device for locating a functional test fault of a CLB module. Background Art

[0002] FPGA (Field Programmable Gate Array) chips are widely used in integrated circuit design. They are mainly composed of input and output units, CLB (Configurable Logic Block) modules, embedded block RAM, interconnection line resources, bottom-level embedded functional units, and embedded dedicated hard cores. CLB is the most basic logic architecture in FPGA chips. Most logic functions are implemented by CLB modules. Therefore, testing of CLB modules in FPGA is extremely important.

[0003] The conventional test method of CLB module is mainly to divide the CLB module array into equal parts, and the CLB modules in each equal part are arranged in parallel in the same row and in series in the same column. By comparing the output data with the input data, the CLB modules are self-tested one by one. This test method can achieve full coverage test of CLB module resources, and if the CLB module fails, the specific position can be located. However, since there are usually more CLB resources in FPGA chips, the compilation and running time of FPGA code in this test method is too long, and the test work is too cumbersome for batch FPGA testing. The patent of the present invention proposes a functional test and fault location method of CLB module of FPGA chip, with the goal of improving test efficiency. A rapidity test is added to the functional test of CLB module in FPGA. If the rapidity test passes, the CLB module test passes. If the rapidity test fails, a fault location test is introduced. The rapidity test can simplify the test process, and the partition process can also greatly reduce the scope of the fault. This method can greatly shorten the FPGA compilation time and CLB module test time, improve the test efficiency, and is suitable for mass production FPGA batch testing. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the related art. To this end, the present invention provides a method, system and device for locating a functional test fault of a CLB module, so as to realize fast and large-scale testing of the CLB module of an FPGA.

[0005] The present invention provides a method for locating a functional test fault of a CLB module, comprising:

[0006] S1: Connect the main control board with the test board, and connect the main control board with the host computer, wherein the test board carries the FPGA chip to be tested;

[0007] S2: Divide the FPGA chip into CLB blocks according to test requirements;

[0008] S3: Perform a rapidity test on the CLB block and send the test result to the host computer;

[0009] S4: Determine whether the CLB block passes the rapidity test. If the rapidity test fails, determine the fault block where the fault is located, and execute step S5;

[0010] S5: Determine the size of the fault block where the fault is located. If the size of the fault block is smaller than the precise search threshold, execute step S6. If the size of the fault block is greater than or equal to the precise search threshold, divide the fault block to obtain divided fault blocks, and return to step S3.

[0011] S6: Perform precise fault finding on the fault block to determine the coordinates of the fault point.

[0012] According to a method for locating a functional test fault of a CLB module provided by the present invention, step S2 comprises:

[0013] S21: Divide the FPGA chip into CLB blocks according to test requirements and set coverage thresholds;

[0014] S22: Burn the test board program to establish communication between the host computer and the main control board, and between the main control board and the test board;

[0015] S23: The host computer sends a test instruction to the test board;

[0016] S24: calling the FIFO (First In First Out) IP core (Intellectual Property core) in the FPGA chip, configuring the CLB block to FIFO mode, and the host computer generates random input data;

[0017] S25: input the random input data to the CLB block; if the output data of the CLB block is the same as the random input data, generate a CLB correct signal; if the output data of the CLB block is different from the random input data, generate a CLB error signal;

[0018] S26: Detect whether the test coverage reaches the coverage threshold, and if so, generate a coverage success signal; if not, generate a coverage failure signal;

[0019] S27: The test result includes a CLB correct signal, a CLB error signal, a coverage success signal and a coverage failure signal, and the test result is sent to the host computer.

[0020] According to a functional test fault locating method for a CLB module provided by the present invention, step S4 includes: when the test result is a CLB correct signal and a coverage success signal, the rapidity test passes; otherwise, the rapidity test fails.

[0021] According to a method for locating a functional test fault of a CLB module provided by the present invention, step S6 comprises:

[0022] S61: The CLB units of each row of the fault block are used in series, the host computer inputs precise search random data from the beginning to the CLB units of each row, outputs precise search data from the end of the CLB units of each row, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units of this row are normal, if not consistent, the current row coordinates are recorded;

[0023] S62: The CLB units of each column of the faulty block are used in series, the host computer inputs precise search random data from the beginning to the CLB units of each column, outputs precise search data from the end of the CLB units of each column, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units of this column are normal, if they are inconsistent, the current column coordinates are recorded;

[0024] S63: According to the row coordinates and column coordinates, combined with the partitioning status of the fault block, the specific coordinates of the CLB fault can be obtained.

[0025] According to a method for locating a functional test fault of a CLB module provided by the present invention, a routine for burning a test board card includes:

[0026] The test board programming software, FPGA and the FLASH chip of the test board are connected through the FPGA simulator.

[0027] According to a method for locating a functional test fault of a CLB module provided by the present invention, the host computer sends a test instruction program including a current test partition and a test number.

[0028] The present invention also provides a CLB module functional test fault location system, comprising:

[0029] Preparation module: connecting the main control board with the test board, and connecting the main control board with the host computer, wherein the test board carries the FPGA chip to be tested;

[0030] Rapidity test module: divide the FPGA chip into CLB blocks according to the test requirements, perform rapidity test on the CLB blocks, and send the test results to the host computer to determine whether the CLB blocks pass the rapidity test. If the rapidity test passes, the test ends. If the rapidity test fails, determine the faulty block where the fault is located, and execute the segmentation block module;

[0031] The block segmentation module determines the size of the fault block where the fault is located. If the size of the fault block is smaller than the fine search threshold, the fine search module is executed. If the size of the fault block is greater than or equal to the fine search threshold, the module returns to the rapidity test module.

[0032] Precision search module: performs precision fault search on the segmented fault blocks to determine the coordinates of the fault point.

[0033] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of a functional test fault location method for a CLB module as described in any one of the above are implemented.

[0034] The above one or more technical solutions in the embodiments of the present invention have at least one of the following technical effects:

[0035] The present invention provides a method, system and device for locating faults in a functional test of a CLB module, which detects the CLB module by using a FIFO IP core, thereby improving the test efficiency and being suitable for batch testing of mass-produced FPGAs.

[0036] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a flow chart of a method for locating a functional test fault of a CLB module provided by the present invention;

[0039] Figure 2 It is a structural block diagram of a functional test fault location system for a CLB module provided by the present invention;

[0040] Figure 3It is a structural schematic diagram of the electronic device provided by the present invention.

[0041] Reference numerals:

[0042] 101. Preparation module; 102. Rapidity test module; 103. Block segmentation module; 104. Precision search module; 810. Processor; 820. Communication interface; 830. Memory; 840. Communication bus. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0044] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0045] Example

[0046] Combine the following Figures 1 to 3 Description of the Invention

[0047] like Figure 1 As shown, the present invention provides a method for locating a functional test fault of a CLB, comprising:

[0048] S1: Connect the main control board with the test board, and connect the main control board with the host computer, wherein the test board carries the FPGA chip to be tested;

[0049] S2: Divide the FPGA chip into CLB blocks according to test requirements;

[0050] S3: Perform a rapidity test on the CLB block and send the test result to the host computer;

[0051] S4: Determine whether the CLB block passes the rapidity test. If the rapidity test fails, determine the fault block where the fault is located, and execute step S5;

[0052] S5: Determine the size of the fault block where the fault is located. If the size of the fault block is smaller than the precise search threshold, execute step S6. If the size of the fault block is greater than or equal to the precise search threshold, divide the fault block to obtain divided fault blocks, and return to step S3.

[0053] S6: Perform precise fault finding on the fault block to determine the coordinates of the fault point.

[0054] Specifically, in step S1:

[0055] The host computer is used to realize the rapid and convenient test process and introduce the human-computer interaction interface. The test board needs to be equipped with an FPGA chip to execute the test program. The main control board realizes the communication between the host computer and the test board, and sends the host computer instructions to the test board. Among them, the instructions are test mode selection, and the test mode includes rapidity test and fault location test. At the same time, the main control board can reduce the loss when the test board is damaged.

[0056] Specifically, step S2 includes:

[0057] S21: Divide the FPGA chip into CLB blocks according to the test requirements and set the coverage threshold. If the occupancy rate of the CLB block of the tested FPGA chip is 100%, the FPGA cannot work normally, so it is necessary to divide it into CLB blocks according to the test requirements. The method of dividing the blocks in the embodiment of the present invention is: divided into two CLB half-areas, and the occupancy rate of each CLB half-area is 50%.

[0058] S22: Burn the test board program to establish communication between the host computer and the main control board, and between the main control board and the test board. Burning the test board program involves using an FPGA simulator to burn software, FPGA, and the FLASH chip of the test board.

[0059] S23: The host computer sends a test instruction to the test board, wherein the test instruction includes the selected partition to be tested; the number of tests for the selected partition; the test mode for the selected partition, including: rapidity test and fault finding mode; test coverage, etc.

[0060] S24: calling the IP core of the FIFO in the FPGA chip, configuring the CLB block into FIFO mode, and the host computer generates random input data.

[0061] S25: Input the random input data to the CLB block; if the output data of the CLB block is the same as the random input data, generate a CLB correct signal; if the output data of the CLB block is different from the random input data, generate a CLB error signal.

[0062] S26: Detect whether the test coverage reaches the coverage threshold, and if so, generate a coverage success signal; if not, generate a coverage failure signal.

[0063] S27: The test result includes a CLB correct signal, a CLB error signal, a coverage success signal and a coverage failure signal, and the test result is sent to the host computer.

[0064] In the embodiment of the present invention, the chip of the FPGA to be tested is divided into two upper and lower CLB blocks, and rapidity tests are performed on the upper and lower CLB blocks respectively to obtain two corresponding test results, and the two results are sent to the host computer.

[0065] Specifically, in step S4: when the test result is a CLB correct signal and a coverage success signal, the rapidity test passes; if the test result is not a CLB correct signal and a coverage success signal, the rapidity test fails.

[0066] In the embodiment of the present invention, the test results of the upper half area are CLB correct signals and coverage success signals; the test results of the lower half area are CLB error signals and coverage failure signals. Therefore, the upper half area passes the rapidity test and no further tests are performed on it; the lower half area fails the rapidity test and therefore needs to be further tested.

[0067] Specifically, the step determines the size of the fault block where the fault is located. If the size of the fault block is smaller than the precise search threshold, step S5 is executed. If the size of the fault block is greater than or equal to the precise search threshold, the fault block is divided to obtain the divided fault blocks, and then step S3 is returned.

[0068] In the embodiment of the present invention, the precise search threshold is 10000, and the CLB module resource in the lower half is 64000. Therefore, the CLB module resources in the lower half need to be divided again, and the process returns to step S3 until the number of faulty CLB modules is less than 10000, and then executes step S6.

[0069] Specifically, step S6 includes:

[0070] S61: The CLB units of each row of the fault block are used in series, the host computer inputs precise search random data from the beginning to the CLB units of each row, outputs precise search data from the end of the CLB units of each row, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units of this row are normal, if not consistent, the current row coordinates are recorded;

[0071] S62: The CLB units of each column of the faulty block are used in series, the host computer inputs precise search random data from the beginning to the CLB units of each column, outputs precise search data from the end of the CLB units of each column, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units of this column are normal, if they are inconsistent, the current column coordinates are recorded;

[0072] S63: According to the row coordinates and column coordinates, combined with the partitioning status of the fault block, the specific coordinates of the CLB fault can be obtained.

[0073] In the embodiment of the present invention, the fault block is 8000 CLB units, which are 80 rows and 100 columns. The CLB units in each row are used in series, and the host computer inputs precise search random data from the beginning to the CLB units in each row, outputs precise search data from the end of the CLB units in each row, and compares the precise search random data with the precise search data; compares the precise search random data with the precise search data, if they are consistent, the CLB units in this row are normal, if not consistent, the current row coordinates are recorded, which is the 65th row.

[0074] The CLB units in each column are used in series respectively, the upper computer inputs precise search random data from the beginning to the CLB units in each column, outputs precise search data from the end of the CLB units in each column, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units in this column are normal, if not consistent, the current column coordinate is recorded, which is the 21st column.

[0075] According to the row coordinates and column coordinates, combined with the partitioning of the fault block, the specific coordinates of the CLB fault can be obtained.

[0076] One of the advantages of the present invention is that the test routine is simple and effective. The IP core using FIFO can greatly shorten the compile time of the test routine and the test time of the FPGA chip. If the CLB module function in the FPGA chip is normal, the test can be passed quickly, which is very suitable for batch FPGA chip testing. At the same time, the IP core using FIFO can observe the abnormal position of the CLB module function in real time. When a bad area appears in the CLB module, the output data of FIFO is inconsistent with the input random data, and the detection can be stopped to determine the location of the faulty block, which greatly improves the test efficiency of the CLB module. At the same time, the FIFO module is used to test the CLB. Compared with the traditional traversal CLB aging configuration test method, the speed is significantly accelerated, shortened from the original one day to several hours.

[0077] The second advantage of the present invention is that it adds a human-computer interaction interface and is easy to operate, so that even non-FPGA professional testers can perform FPGA chip CLB module testing.

[0078] The third advantage of the present invention is that the error unit of the CLB module of the FPGA can be accurately located, and accurate replacement and repair can be performed according to the corresponding error block.

[0079] like Figure 2 As shown, a functional test fault locating system for a CLB module provided by the present invention is described below. The functional test fault locating system for a CLB module described below and the functional test fault locating method for a CLB module described above can correspond to each other.

[0080] Preparation module 101: connecting the main control board with the test board, and connecting the main control board with the host computer, wherein the test board carries the FPGA chip to be tested;

[0081] Rapidity test module 102: divides the FPGA chip into CLB blocks according to the test requirements, performs rapidity test on the CLB blocks, and sends the test results to the host computer to determine whether the CLB blocks pass the rapidity test. If the rapidity test fails, the fault block where the fault is located is determined, and the segmentation block module is executed;

[0082] The block division module 103 determines the size of the fault block where the fault is located. If the size of the fault block is smaller than the fine search threshold, the fine search module is executed. If the size of the fault block is greater than or equal to the fine search threshold, the fault block is divided to obtain the divided fault blocks, and the fault blocks are returned to the rapidity test module.

[0083] The precise search module 104 performs precise fault search on the segmented fault blocks to determine the coordinates of the fault point.

[0084] Figure 3 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 3 As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820 and the memory 830 communicate with each other through the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a functional test fault location method of a CLB module, the method comprising:

[0085] S1: Connect the main control board with the test board, and connect the main control board with the host computer, wherein the test board carries the FPGA chip to be tested;

[0086] S2: Divide the FPGA chip into CLB blocks according to test requirements;

[0087] S3: Perform a rapidity test on the CLB block and send the test result to the host computer;

[0088] S4: Determine whether the CLB block passes the rapidity test. If the rapidity test fails, determine the fault block where the fault is located, and execute step S5;

[0089] S5: Determine the size of the fault block where the fault is located. If the size of the fault block is smaller than the precise search threshold, execute step S6. If the size of the fault block is greater than or equal to the precise search threshold, divide the fault block to obtain divided fault blocks, and return to step S3.

[0090] S6: Perform precise fault finding on the fault block to determine the coordinates of the fault point.

[0091] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for locating a functional test fault of a CLB module, characterized in that: include: S1: Connect the main control board with the test board, and connect the main control board with the host computer, wherein the test board carries the FPGA chip to be tested; S2: Divide the FPGA chip into CLB blocks according to test requirements; S21: Divide the FPGA chip into CLB blocks according to test requirements and set coverage thresholds; S22: Burn the test board program to establish communication between the host computer and the main control board, and between the main control board and the test board; S23: The host computer sends a test instruction to the test board; S24: calling the IP core of the FIFO in the FPGA chip, configuring the CLB block to the FIFO mode, and the host computer generates random input data; S25: input the random input data to the CLB block; if the output data of the CLB block is the same as the random input data, generate a CLB correct signal; if the output data of the CLB block is different from the random input data, generate a CLB error signal; S26: Detect whether the test coverage reaches the coverage threshold, and if so, generate a coverage success signal; if not, generate a coverage failure signal; S27: The test result includes a CLB correct signal, a CLB error signal, a coverage success signal, and a coverage failure signal, and the test result is sent to the host computer; S3: Perform a rapidity test on the CLB block and send the test result to the host computer; S4: Determine whether the CLB block passes the rapidity test. If the rapidity test fails, determine the fault block where the fault is located, and execute step S5; S5: Determine the size of the fault block where the fault is located. If the size of the fault block is smaller than the precise search threshold, execute step S6. If the size of the fault block is greater than or equal to the precise search threshold, divide the fault block to obtain divided fault blocks, and return to step S3. S6: Perform precise fault finding on the faulty block to determine the coordinates of the fault point.

2. A method for locating a CLB module's functional test fault according to claim 1, characterized in that: Step S4 includes: when the test result is a CLB correct signal and a coverage success signal, the rapidity test is passed; otherwise, the rapidity test is not passed.

3. A method for locating a CLB module's functional test fault according to claim 1, characterized in that: Step S6 includes: S61: The CLB units of each row of the fault block are used in series, the host computer inputs precise search random data from the beginning to the CLB units of each row, outputs precise search data from the end of the CLB units of each row, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units of this row are normal, if not consistent, the current row coordinates are recorded; S62: The CLB units of each column of the faulty block are used in series, the host computer inputs precise search random data from the beginning to the CLB units of each column, outputs precise search data from the end of the CLB units of each column, and compares the precise search random data with the precise search data; the precise search random data is compared with the precise search data, if they are consistent, the CLB units of this column are normal, if they are inconsistent, the current column coordinates are recorded; S63: According to the row coordinates and column coordinates, combined with the partitioning status of the fault block, the specific coordinates of the CLB fault can be obtained.

4. A method for locating a CLB module's functional test fault according to claim 1, characterized in that: The routines for burning and testing the board include: The test board programming software, FPGA and the FLASH chip of the test board are connected through the FPGA simulator.

5. The method for locating a functional test fault of a CLB module according to claim 1, characterized in that: The host computer sends a test instruction program, including the current test partition and the number of tests.

6. A CLB module functional test fault location system, used to execute a CLB module functional test fault location method as claimed in any one of claims 1 to 5, characterized in that: include: Preparation module: connecting the main control board with the test board, and connecting the main control board with the host computer, wherein the test board carries the FPGA chip to be tested; Rapidity test module: divide the FPGA chip into CLB blocks according to test requirements, perform rapidity test on the CLB blocks, divide the FPGA chip into CLB blocks according to test requirements, and set coverage thresholds; Burn the test board program to establish communication between the host computer and the main control board, and between the main control board and the test board; the host computer sends test instructions to the test board; call the IP core of the FIFO in the FPGA chip, configure the CLB block to the FIFO mode, and the host computer generates random input data; input the random input data into the CLB block; if the output data of the CLB block is the same as the random input data, a CLB correct signal is generated; if the output data of the CLB block is different from the random input data, a CLB error signal is generated; detect whether the test coverage reaches the coverage threshold, if it reaches, a coverage success signal is generated; if not, a coverage failure signal is generated; the test results include a CLB correct signal, a CLB error signal, a coverage success signal, and a coverage failure signal; and send the test results to the host computer to determine whether the CLB block passes the rapidity test. If the rapidity test fails, determine the faulty block where the fault is located, and execute the segmentation block module; Block segmentation module: determines the size of the fault block where the fault is located. If the size of the fault block is smaller than the fine search threshold, the fine search module is executed. If the size of the fault block is greater than or equal to the fine search threshold, the fault block is segmented to obtain the segmented fault blocks, which are then returned to the rapidity test module. Precision search module: performs precision fault search on the segmented fault blocks to determine the coordinates of the fault point.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the functional test fault location method of a CLB module as described in any one of claims 1 to 5 are implemented.

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