Input signal analysis device, input signal analysis method, test device and test system
By using the combination of input signal delay module, comparison processing module and result analysis module in Timing Generator, the problem of high design complexity in traditional technology is solved, and the detection of signal jump edges and the acquisition of performance indicator data is realized, reducing the Design complexity and suitable for general-purpose chips.
Patent Information
- Application Number
- CN202310710408.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-27
AI Technical Summary
When conducting chip testing, traditional Timing Generator needs to adjust the clock phase for the control of the input signal sampling time, resulting in high design complexity and the use of special ICs, which has the disadvantage of high design complexity.
The input signal delay module is used to delay the comparison signal output by the PE module according to the configured delay parameters, and samples the delayed signal. The comparison processing module analyzes and determines the actual sampling value, and the input configuration module adjusts the delay parameters until The signal jump edge is detected, and the result analysis module determines the performance index data of the input signal.
By delaying the signal first and then sampling, there is no need to switch the clock phase, which reduces the design complexity and can use a general-purpose chip to detect the signal jump edge.
Smart Images
Figure CN119200745A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of signal processing technology, and in particular to an input signal analysis device, method, test device and test system. Background Art
[0002] Timing Generator (TG) is an important component of the tester, responsible for synthesizing the output waveform according to the user's requirements and sampling the input signal according to the sampling time configured by the user. When the traditional Timing Generator is testing the chip, the sampling time of the input signal is controlled by adjusting the clock phase, and a dedicated IC (Integrated Circuit) must be used. The implementation structure is complex and has the disadvantage of high design complexity. Summary of the invention
[0003] Based on this, it is necessary to provide a universal input signal analysis device, method, test device and test system that can reduce the high design complexity in order to solve the above problems.
[0004] An input signal analysis device, comprising:
[0005] An input signal delay module, connected to the PE module, is used to delay the comparison signal output by the PE module according to the configured delay parameter, and sample the delayed signal to obtain a sampled signal;
[0006] A comparison processing module, connected to the input signal delay module, used to determine the actual sampling value according to the sampling signal analysis to obtain a comparison result;
[0007] An input configuration module, connected to the input signal delay module and the comparison processing module, for adjusting the delay parameter of the input signal delay module according to the comparison result and the set target comparison result until the signal transition edge is stably detected, and obtaining the delay parameter corresponding to the input signal delay module and sending it to the result analysis module;
[0008] The result analysis module is connected to the input configuration module and is used to determine the performance indicator data of the input signal according to the received delay parameter analysis.
[0009] In one embodiment, the comparison signal output by the PE module includes two output signals; the input signal delay module includes a first delay chain and a second delay chain, the first delay chain connects the PE module, the comparison processing module and the input configuration module; the second delay chain connects the PE module, the comparison processing module and the input configuration module.
[0010] In one embodiment, the first delay chain and the second delay chain are IODELAY delay chains.
[0011] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value as the comparison result and output it to the input configuration module.
[0012] In one embodiment, the input configuration module detects, based on the received comparison result, that the first signal and the second signal are both stable at a low level during one sampling, and the first signal and the second signal are both stable at a high level during another sampling, and then determines that a signal transition edge is stably detected.
[0013] In one embodiment, the input configuration module sends the delay parameter of the input signal delay module when the first signal and the second signal are simultaneously stable at a high level, and the delay parameter of the input signal delay module when the first signal and the second signal are simultaneously stable at a low level, to the result analysis module; the result analysis module subtracts the received delay parameters and uses the difference as the performance indicator data of the input signal.
[0014] In one embodiment, when the input configuration module continuously detects that the first signal and the second signal are continuously and simultaneously at low levels, the input configuration module determines the range of the delay parameter of the input signal delay module and sends it to the result analysis module; or
[0015] When the input configuration module continuously detects that the first signal and the second signal are continuously and simultaneously at high levels, the input configuration module determines the range of the delay parameter of the input signal delay module and sends it to the result analysis module.
[0016] An input signal analysis method, comprising:
[0017] The input signal delay module delays the comparison signal output by the PE module according to the delay parameter, and samples the delayed signal to obtain a sampling signal;
[0018] The comparison processing module determines the actual sampling value according to the sampling signal analysis to obtain a comparison result;
[0019] The input configuration module adjusts the delay parameter of the input signal delay module according to the comparison result and the set target comparison result until the signal transition edge is stably detected, and obtains the delay parameter corresponding to the input signal delay module and sends it to the result analysis module;
[0020] The result analysis module determines the performance indicator data of the input signal according to the received delay parameter analysis.
[0021] A testing device comprises a waveform synthesis module, an output signal delay module and the above-mentioned input signal analysis device, wherein the waveform synthesis module is connected to the output signal delay module, and the output signal delay module is used to connect to a device to be tested.
[0022] A test system comprises a PE module and the above-mentioned test device, wherein the output signal delay module is connected to the PE module, the PE module is connected to a device to be tested, and the input signal delay module is connected to the PE module.
[0023] In one of the embodiments, the PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the input signal delay module.
[0024] In the above-mentioned input signal analysis device, method, test device and test system, the input signal delay module delays the comparison signal output by the PE module according to the configured delay parameters, and samples the delayed signal to obtain a sampled signal. The comparison processing module determines the actual sampling value based on the sampled signal analysis to obtain a comparison result. The input configuration module adjusts the delay parameters of the input signal delay module according to the comparison result and the set target comparison result until the signal transition edge is stably detected. The result analysis module determines the performance indicator data of the input signal based on the delay parameter analysis of the input signal delay module. By adopting the method of delaying the signal first and then sampling the signal, there is no need to switch the phase of the clock, and a general chip can be used to realize the detection of the signal transition edge, which reduces the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a structural block diagram of an input signal analysis device in one embodiment;
[0026] Figure 2 A schematic diagram of signal conversion of a PE module in one embodiment;
[0027] Figure 3 It is a structural block diagram of an input signal delay module and an input configuration module in one embodiment;
[0028] Figure 4 is a structural block diagram of a test system in one embodiment;
[0029] Figure 5 It is a structural block diagram of an output signal delay module and an output configuration module in one embodiment;
[0030] Figure 6 A comparison truth table and a comparison processing principle diagram in one embodiment. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0033] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.
[0035] When detecting the signal transition edge, the clock or signal needs to be delayed. The current Timing Generator controls the input signal sampling time by adjusting the clock phase. If you want to sample the chip output signal at different positions, you usually adjust the sampling clock phase first, and then sample the chip output signal. You must design a dedicated chip to implement it, and the dedicated chip implementation structure is complex. Based on this, the present application provides an input signal analysis device, and the input signal delay module delays the comparison signal output by the PE module according to the configured delay parameters, and samples the delayed signal to obtain the sampled signal. The comparison processing module determines the actual sampling value based on the sampled signal analysis to obtain the comparison result. The input configuration module adjusts the delay parameter of the input signal delay module according to the comparison result and the set target comparison result until the signal transition edge is stably detected, and obtains the delay parameter corresponding to the input signal delay module and sends it to the result analysis module. The result analysis module determines the performance indicator data of the input signal based on the received delay parameter analysis. By adopting the method of delaying the signal first and then sampling the signal, there is no need to switch the clock phase, and a general chip can be used to detect the signal transition edge, reducing the design complexity.
[0036] In one embodiment, Figure 1As shown, an input signal analysis device is provided, including an input signal delay module 220, a comparison processing module 230, an input configuration module 240 and a result analysis module, wherein the input signal delay module 220 is connected to the PE (Pin Electronics Driver / Comparator) module 210, the comparison processing module 230 is connected to the input signal delay module 220, and the input configuration module 240 is connected to the input signal delay module 220 and the comparison processing module 230. The input signal delay module 220 is used to delay the comparison signal output by the PE module 210 according to the configured delay parameters, and to sample the delayed signal to obtain a sampled signal; the comparison processing module 230 is used to determine the actual sampling value according to the sampled signal analysis to obtain a comparison result; the input configuration module 240 is used to adjust the delay parameters of the input signal delay module 220 according to the comparison result and the set target comparison result until the signal transition edge is stably detected, and then obtain the delay parameters corresponding to the input signal delay module 220 and send them to the result analysis module; the result analysis module determines the performance indicator data of the input signal according to the received delay parameter analysis. The result analysis module can be a host computer, such as a personal computer, a desktop computer, etc., or it can be a module in an FPGA. For ease of understanding, the following explanations are all given using the host computer as an example of the result analysis module.
[0037] Among them, the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value, and outputs the comparison signal to the input signal delay module 220. The device under test DUT can be a chip under test or other devices. The structure of the input signal delay module 220 is not unique, and can be implemented through dedicated resources inside the FPGA, such as IDELAY, ODELAY, CARRY, and basic delay units. For example, when the input signal delay module 220 adopts IDELAY and ODELAY, the delay parameter configured by the input signal delay module 220 is specifically the tap value. Among them, the delay span of the input signal delay module 220 can cover the clock cycle range, ensuring that any position within the clock cycle can be sampled. In addition, the input configuration module 240 can also be connected to the host computer. Specifically, taking the input signal delay module 220, the comparison processing module 230 and the input configuration module 240 as an example, the host computer is connected to the FPGA through a burner, the FPGA is connected to the PE module 210 through a microstrip line, and the PE module 210 and the device under test DUT are connected through a flat cable.
[0038] The value of the preset level threshold is not unique and can be adjusted during the test process. The way in which the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold is not unique. In one embodiment, the preset level threshold includes a threshold value VOH and a threshold value VOL. The values of the threshold value VOH and the threshold value VOL are not unique and can be set according to actual needs. It is only necessary to satisfy that the threshold value VOH is greater than the threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. The output signal of the PE module 210 is delayed and sampled by the input signal delay module 220 to obtain two sampling signals that are sent to the comparison processing module 230. The output signal CA\output signal CB are standard high and low level digital signals, such as Figure 2 When the input signal is less than the threshold value VOL, the output signal CA is low level, and the output signal CB is low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is low level, and the output signal CB is high level; when the input signal is greater than the threshold value VOH, the output signal CA is high level, and the output signal CB is high level.
[0039] The way in which the input configuration module 240 stably detects the signal transition edge is not unique. For example, the input configuration module 240 may detect that both sampling signals are stable at a high level and become stable at a low level, or detect that both sampling signals are stable at a low level and become stable at a high level, then it can be considered that the signal transition edge is stably detected. Among them, it can be that when the two sampling signals are detected as high levels for a set number of consecutive times, it is considered that the two sampling signals are stable at a high level, and when the two sampling signals are detected as low levels for a set number of consecutive times, it is considered that the two sampling signals are stable at a low level. The specific value of the set number of times is not unique, and can be 1 time, or 2 times or more times. When the set number of times is at least 2 times, the level stability is determined by multiple detections, and the interference of instantaneous abnormal signals can be excluded. It can be understood that when each module operates stably, there is no abnormal interference or the abnormal interference is not enough to affect the level detection, the level stability can also be determined by 1 detection.
[0040] In the above-mentioned input signal analysis device, the input signal delay module 220 delays the comparison signal output by the PE module 210 according to the configured delay parameters, and samples the delayed signal to obtain a sampled signal. The comparison processing module 230 determines the actual sampling value based on the sampled signal analysis to obtain a comparison result. The input configuration module 240 adjusts the delay parameters of the input signal delay module 220 according to the comparison result and the set target comparison result until the signal transition edge is stably detected. The result analysis module determines the performance indicator data of the input signal based on the delay parameter analysis of the input signal delay module 220. By adopting the method of delaying the signal first and then sampling the signal, there is no need to switch the phase of the clock, and a general chip can be used to realize the detection of the signal transition edge, thereby reducing the design complexity.
[0041] In one embodiment, the comparison signal output by the PE module 210 includes two output signals; the input signal delay module 220 includes a first delay chain and a second delay chain, the first delay chain connects the PE module 210, the comparison processing module 230 and the input configuration module 240; the second delay chain connects the PE module 210, the comparison processing module 230 and the input configuration module 240. Among them, the first delay chain and the second delay chain can be delay chains composed of IDELAY and ODELAY, or can be delay chains composed of CARRY or basic delay units. The first delay chain and the second delay chain respectively delay and sample the two output signals output by the PE module 210, and output corresponding sampling signals to the comparison processing module 230. Further, the sampling signal includes a first signal and a second signal, and the comparison processing module 230 performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and outputs it to the input configuration module 240 as a comparison result. In addition, the comparison processing module 230 can also perform parallel comparison and judgment based on the actual sampling value and the preset expected value, and use the obtained comparison value and the actual sampling value together as the comparison result.
[0042] Specifically, the output signal CA and the output signal CB of the PE module 210 are delayed and sampled by the first delay chain and the second delay chain respectively, and two sampling signals are obtained and sent to the comparison processing module 230. The comparison processing module 230 can analyze the two sampling signals according to the set comparison truth table to determine the actual sampling value, and then compare and judge the actual sampling value and the preset expected value, and output the comparison result after obtaining it for data storage or analysis. Among them, the specific value of the expected value is not unique and can be changed during the test process.
[0043] In one embodiment, the first delay chain and the second delay chain are IODELAY delay chains. Specifically, the IODELAY delay chain includes an IDELAY unit, an ODELAY unit and a tap configuration unit. The number of IDELAY units and ODELAY units can be one or more than two. The connection relationship between the IDELAY unit and the ODELAY unit is not unique. In this embodiment, after the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit at the head end is connected to the PE module 210, the ODELAY unit at the tail end is connected to the comparison processing module 230, and the tap configuration unit is connected to the IDELAY unit, the ODELAY unit and the input configuration module 240. The tap configuration unit delays the accessed signal according to the IDELAY tap value and the ODELAY tap value configured by the input configuration module 240, and outputs the sampling signal through the ODELAY unit at the tail end.
[0044] In one embodiment, Figure 3 As shown, the first delay chain and the second delay chain include a basic delay unit 222 and a signal sampling unit 224, and the number of the basic delay units 222 is at least two. The delay span of all basic delay units can cover the clock cycle range, so that the sampling position can be set to any position in the clock. In the first delay chain and the second delay chain, each basic delay unit 222 is connected in series in sequence, the basic delay unit 222 at the head end is connected to the PE module 210, the basic delay unit 222 at the tail end is connected to the signal sampling unit 224, the signal sampling unit 224 is connected to the comparison processing module 230, and the input configuration module 240 is connected to each basic delay unit 222 and the signal sampling unit 224.
[0045] It can be understood that the specific structure of the basic delay unit is not unique. In this embodiment, Figure 3As shown, the first delay chain and the second delay chain may include a basic delay unit 1, a basic delay unit 2, ..., a basic delay unit n. Each basic delay unit includes a direct line, a basic logic unit and a data selector MUX. After the direct line is connected in parallel with the basic logic unit, one end is connected to the data selector MUX, and the other end is connected to the basic delay unit or PE module 210 of the previous level. The data selector MUX is connected to the basic delay unit or signal sampling unit 224 of the next level. Specifically, in the basic delay unit located at the head end, the basic logic unit is connected to the PE module 210, and the data selector MUX is connected to the basic delay unit of the next level. In the basic delay unit located at the end, the basic logic unit is connected to the basic delay unit of the previous level, and the data selector MUX is connected to the signal sampling unit 224. In addition, the data selector MUX of each basic logic unit can also be connected to the signal sampling unit 224. The direct line delay and basic logic unit delay of each basic delay unit are both in the ps level, and there are slight differences. By connecting multiple basic delay units in series in a delay chain, the cumulative difference can cover the signal test cycle with a resolution of ps level.
[0046] The input configuration module 240 connects the data selector MUX in each basic delay unit and the signal sampling unit 224, and configures the path setting parameter sel corresponding to the required signal delay and the signal sampling selection parameter num according to the current sampling position requirement. The basic delay units in the first delay chain and the second delay chain respectively delay the two output signals of the PE module 210 for a corresponding time according to the path setting parameter sel, and the signal sampling unit 224 outputs the sampling values of the two signals according to the signal sampling selection parameter num. Among them, the data selector MUX of each basic delay unit selects the signal transmitted by the basic logic unit or the direct line in the basic delay unit according to the configured parameters, and transmits it to the next basic delay unit or the signal sampling unit 224, thereby controlling whether each basic delay unit delays the signal through the basic logic unit or directly transmits the signal through the direct line.
[0047] Further, in one embodiment, the data selectors of adjacent basic delay units are arranged in adjacent resource blocks. Specifically, during FPGA layout and routing, the logic of the data selector MUX of the adjacent basic delay unit is arranged in the adjacent resource block to achieve the minimum resolution. It can be understood that if the resolution requirement is not high, it is not necessary to arrange the logic of the data selector MUX of the adjacent basic delay unit in the adjacent resource block.
[0048] In one embodiment, the input configuration module 240 detects that the first signal and the second signal are both stable at a low level during one sampling, and the first signal and the second signal are both stable at a high level during another sampling according to the comparison result received, and then determines that the signal transition edge is stably detected. Among them, the input configuration module 240 adjusts the delay parameter of the input signal delay module 220 once, and obtains the comparison result obtained by one sampling comparison. The input configuration module 240 detects that the first signal and the second signal are both stable at a low level during one sampling, and the first signal and the second signal are both stable at a high level during another sampling according to the comparison result received, and then determines that the signal transition edge is stably detected. Similarly, when the first signal and the second signal are detected as low levels for a set number of consecutive times, it is considered that the first signal and the second signal are both stable at a low level; when the first signal and the second signal are detected as high levels for a set number of consecutive times, it is considered that the first signal and the second signal are both stable at a high level. The set number of times can be 1 time, or it can be 2 times or more times.
[0049] In this embodiment, the first signal is a signal obtained by sampling the output signal CA, and the second signal is a signal obtained by sampling the output signal CB. The target comparison result can be that the first signal and the second signal are both low level, or the first signal and the second signal are both high level. According to the comparison result output by the comparison processing module 230, it can be determined whether the first signal and the second signal are high level or low level. According to the actual detection purpose, the expected next comparison result will also correspond to all different. When detecting the transition edge, if both signals are high level, adjust the delay parameter of the input signal delay module 220, and expect the next comparison result to be that both signals are low level; if the first signal is low level and the second signal is high level, adjust the delay parameter of the input signal delay module 220, and expect the next comparison result to be that both signals are low level or both are high level; if both signals are low level, adjust the delay parameter of the input signal delay module 220, and expect the next comparison result to be that both signals are high level. When detecting the level duration, if both signals are detected to be high level, the next comparison result is expected to remain unchanged, and if both signals are detected to be low level, the next comparison result is also expected to remain unchanged. In addition, if the first signal is high level and the second signal is low level, it is considered that the PE module 210 is configured incorrectly, and the input configuration module 240 can also report alarm information to the host computer.
[0050] Taking the current comparison result that both signals are high level and the next comparison result that both signals are low level as an example, if the input signal is low level first and high level later, the delay time of the input signal delay module 220 can be reduced to detect the low level part of the input signal; if the input signal is high level first and low level later, the delay time of the input signal delay module 220 can be increased to detect the low level part of the input signal. It can be understood that according to different input signals, the input configuration module 240 will adjust the delay parameters of the input signal delay module 220 according to the comparison result and the set target comparison result, and will not be elaborated on here.
[0051] When it is detected that the first signal and the second signal change from a stable low level to a stable high level at the same time, or change from a stable high level to a stable low level at the same time, it is considered that the signal transition edge is stably detected. Depending on the purpose of the analysis, according to the delay parameters of the input signal delay module 220, the method of analyzing and determining the performance indicator data of the input signal will also be different. After the signal transition edge is stably detected, the input configuration module 240 uploads the delay parameters corresponding to the input signal delay module 220 to the host computer, so as to be used by the host computer to determine the performance indicator data and analyze the input signal.
[0052] In one embodiment, the input configuration module 240 sends the delay parameters of the input signal delay module 220 when the first signal and the second signal are simultaneously stable at a high level, and the delay parameters of the input signal delay module 220 when the first signal and the second signal are simultaneously stable at a low level, to the result analysis module; the result analysis module subtracts the received delay parameters and uses the difference as the performance indicator data of the input signal.
[0053] The input configuration module 240 can be a delay parameter of the input signal delay module 220 when the first signal and the second signal are simultaneously stable at a high level, and the delay parameter of the input signal delay module 220 when the first signal and the second signal are simultaneously stable at a low level is subtracted, and sent to the host computer. The host computer subtracts the received delay parameters, and uses the absolute value of the difference as the performance indicator data of the input signal, which is used to analyze the duration of the input signal from a high level to a low level, or from a low level to a high level. For example, if the first signal and the second signal are first detected to be stable at a high level at the same time, and then the first signal and the second signal are detected to be stable at a low level at the same time, the host computer can determine the duration of the input signal from a high level to a low level according to the absolute value of the difference, that is, the duration of the falling edge of the signal; if the first signal and the second signal are first detected to be stable at a low level at the same time, and then the first signal and the second signal are detected to be stable at a high level at the same time, the host computer can determine the duration of the input signal from a low level to a high level according to the absolute value of the difference, that is, the duration of the rising edge of the signal.
[0054] In one embodiment, when the input configuration module 240 continuously detects that the first signal and the second signal are continuously and simultaneously at low levels, it determines the range of the delay parameter of the input signal delay module 220 and sends it to the result analysis module.
[0055] The input configuration module 240 may also determine the range of the delay parameter of the input signal delay module 220 when the first signal and the second signal are continuously and stably detected to be at low levels at the same time, and send it to the host computer. The host computer uses the range of the delay parameter as the performance indicator data of the input signal to analyze the duration of the low level of the input signal.
[0056] In one embodiment, when the input configuration module 240 continuously detects that the first signal and the second signal are continuously at high levels at the same time, it determines the range of the delay parameter of the input signal delay module 220 and sends it to the result analysis module.
[0057] The input configuration module 240 can also determine the range of the delay parameter of the input signal delay module 220 when the first signal and the second signal are continuously and stably detected to be high at the same time, and send it to the host computer. The host computer uses the range of the delay parameter as the performance indicator data of the input signal to analyze the duration of the high level of the input signal. For example, the host computer can convert the high level duration of the input signal according to the range of the delay parameter, and then divide the high level duration by the signal period to obtain the duty cycle of the input signal.
[0058] In one embodiment, an input signal analysis method is also provided, including: an input signal delay module delays a comparison signal output by a PE module according to a delay parameter, and samples the delayed signal to obtain a sampled signal; a comparison processing module determines an actual sampling value based on sampled signal analysis to obtain a comparison result; an input configuration module adjusts a delay parameter of an input signal delay module based on the comparison result and a set target comparison result until a signal transition edge is stably detected, and then obtains a delay parameter corresponding to the input signal delay module and sends it to a result analysis module; the result analysis module determines performance indicator data of the input signal based on the received delay parameter analysis.
[0059] It can be understood that the specific implementation of the above-mentioned input signal analysis method has been explained in detail in the above-mentioned input signal analysis device, and will not be repeated here.
[0060] In one embodiment, Figure 4As shown, a test device is also provided, including a waveform synthesis module 120, an output signal delay module 130 and the above-mentioned input signal analysis device, the waveform synthesis module 120 is connected to the output signal delay module 130, and the output signal delay module 130 is used to connect to the device under test DUT. The waveform synthesis module 120 performs waveform format synthesis on the original data stream according to the configured waveform format to obtain a synthesized waveform; the output signal delay module 130 performs delay processing on the synthesized waveform according to the configured output delay value to obtain an output waveform. Further, the test device also includes an output data source module 110 connected to the waveform synthesis module 120, and the output data source module 110 is used to output the original data stream.
[0061] Among them, according to the different output waveforms actually required, the waveform format configured by the waveform synthesis module 120 and the output delay value configured by the output signal delay module 130 will also be different, and can be adjusted according to the actual situation. In one embodiment, the test device also includes an output configuration module 140, which connects the waveform synthesis module 120 and the output signal delay module 130 to configure the waveform format and the output delay value. The tester can configure the waveform format and the output delay value through the output configuration module 140 according to the actual test needs, so that the output waveform control device generates the corresponding output waveform according to the actual needs. After the waveform synthesis module 120 synthesizes the waveform format of the original data stream output by the output data source module 110 according to the configured waveform format, it outputs the synthesized waveform to the output signal delay module 130. The output signal delay module 130 delays the synthesized waveform according to the configured output delay value and the internal clock to obtain the output waveform. The output waveform is used to be transmitted to the device under test DUT to test the device under test DUT. The type of waveform format is not unique, for example, it may include NRZ, RZ, XORBC and other formats.
[0062] The delay width of the output signal delay module 130 covers the clock cycle. It can be understood that the specific structure of the output signal delay module 130 is not unique and can be implemented through dedicated resources inside the FPGA, such as IDELAY, ODELAY, CARRY, and basic delay units.
[0063] In one embodiment, the output signal delay module 130 is an IODELAY module. Specifically, the IODELAY module includes an IDELAY unit, an ODELAY unit and a tap configuration unit. The number of IDELAY units and ODELAY units can be one or at least two. The connection method of the IDELAY unit and the ODELAY unit is not unique and can be set according to actual needs. In this embodiment, after the IDELAY unit and the ODELAY unit are alternately connected in sequence, the IDELAY unit at the head end is connected to the waveform synthesis module 120, the ODELAY unit at the tail end is used to connect the device to be tested DUT, and the tap configuration unit connects the IDELAY unit, the ODELAY unit and the output configuration module 140. The tap configuration unit performs delay control on the connected waveform according to the IDELAY tap value and the ODELAY tap value configured by the output configuration module 140, and the delayed waveform is output through the ODELAY unit at the tail end.
[0064] In one embodiment, the output signal delay module 130 includes at least two basic delay units, and the delay span of all basic delay units can cover the clock cycle range, so that the position of the output signal edge can be set to any position in the clock. The basic delay units are connected in series in sequence, and the basic delay unit at the head end is connected to the waveform synthesis module 120, and the basic delay unit at the tail end is connected to the device under test DUT.
[0065] In this embodiment, Figure 5As shown, the basic delay unit in the output signal delay module 130 includes a basic delay unit 1, a basic delay unit 2, ..., a basic delay unit n. Each basic delay unit includes a direct line, a basic logic unit and a data selector MUX. After the direct line is connected in parallel with the basic logic unit, one end is connected to the data selector MUX, and the other end is connected to the basic delay unit or waveform synthesis module 120 of the previous level. The data selector MUX is connected to the basic delay unit or the device to be tested DUT of the next level. Specifically, in the basic delay unit located at the head end, the basic logic unit is connected to the waveform synthesis module 120, and the data selector MUX is connected to the basic delay unit of the next level. In the basic delay unit located at the end, the basic logic unit is connected to the basic delay unit of the previous level, and the data selector MUX is used to connect the device to be tested DUT. The output configuration module 140 configures the path setting parameter sel corresponding to the required delay of the signal according to actual needs, and the output signal delay module 130 delays the input synthetic waveform for a corresponding time according to the path setting parameter sel. Among them, the data selector MUX of each basic delay unit in the output signal delay module 130 selects the signal transmitted by the basic logic unit or the direct line in the basic delay unit according to the configured parameters, and transmits it to the next basic delay unit or the device to be tested DUT, thereby controlling whether each basic delay unit delays the signal through the basic logic unit or directly transmits the signal through the direct line. The direct line delay and basic logic unit delay of each basic delay unit are both at the ps level, and there are slight differences. By connecting multiple basic delay units in series, the cumulative difference can cover the signal test cycle, and the resolution reaches the ps level.
[0066] Further, in one embodiment, in the output signal delay module 130, the data selectors of the adjacent basic delay units are arranged in the adjacent resource blocks. Specifically, during the FPGA layout and routing, the logic of the data selector MUX of the adjacent basic delay unit is arranged in the adjacent resource block to achieve the minimum resolution. It can be understood that if the resolution requirement is not high, it is not necessary to arrange the logic of the data selector MUX of the adjacent basic delay unit in the adjacent resource block.
[0067] The above-mentioned test device first synthesizes the waveform format of the original data stream according to the configured waveform format through the waveform synthesis module 120 to obtain a synthesized waveform, and then delays the synthesized waveform according to the configured output delay value through the output signal delay module 130. The output waveform is obtained by first synthesizing the waveform and then delaying it. The output waveform can be obtained without adjusting the driving clock phase, and a general chip can be used to implement the waveform output function, which reduces the design complexity.
[0068] In one embodiment, Figure 4As shown, a test system is also provided, including a PE module 210 and the above-mentioned test device, the output signal delay module 130 is connected to the PE module 210, the PE module 210 is connected to the device under test DUT, and the input signal delay module 220 is connected to the PE module 210.
[0069] Specifically, the output data source module 110, the waveform synthesis module 120, the output signal delay module 130, the PE module 210 and the device under test DUT are connected in sequence, the waveform format synthesis is first performed on the original data stream and then the signal delay is performed, and finally the excitation signal is output to the device under test DUT through the PE module 210. Among them, the output data source module 110 can be ALPG (Algorithmic Pattern Generator, algorithmic graphic generation module), which automatically generates the original data stream according to the written program. The output data source module 110 can also be PG (Pattern Generator, graphic generation module), which generates the original data stream according to the specified test vector. The PE module 210 receives the output waveform obtained by the output signal delay module 130, converts it according to the set level threshold value (VIH\VIL) to obtain the excitation signal and sends it to the device under test DUT.
[0070] In one embodiment, the PE module 210 compares and judges the input signal fed back by the device under test according to the preset level threshold value, and outputs the comparison signal to the input signal delay module 220. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB.
[0071] Specifically, the input signal analysis execution process is as follows:
[0072] 1) Drive the device under test (DUT) to output signals.
[0073] 2) The PE module 210 converts the signal fed back by the device under test DUT into output signals CA and CB according to the two set comparison threshold values (VOH\VOL).
[0074] 3) The input configuration module 240 sets the tap value to the input signal delay module 220 .
[0075] 4) The input signal delay module 220 delays the output signals CA and CB according to the tap value, and outputs the sampling signals CA_s and CB_s to the comparison processing module 230 .
[0076] 5) The comparison processing module 230 uses the comparison truth table to determine the actual sampling value according to the state values of the sampling signal CA_s and the sampling signal CB_s. The principle of comparison is as follows Figure 6If the sampling signal CA_s and the sampling signal CB_s are both high levels, the comparison result is that the current input is high level, recorded as Result1; if the sampling signal CA_s is low level and the sampling signal CB_s is high level, the comparison result is that the current input is high impedance, recorded as Result2; if the sampling signal CA_s and the sampling signal CB_s are both low levels, the comparison result is that the current input is low level, recorded as Result3; if the sampling signal CA_s is high level and the sampling signal CB_s is low level, the current comparison result is invalid, and the PE module 210 is incorrectly configured, recorded as Result4.
[0077] 6) The comparison processing module 230 adjusts the tap value sent according to the comparison result: in the case of Result1, the tap value is adjusted so that the next comparison result is expected to be Result3; in the case of Result2, the tap value is adjusted so that the next comparison result is expected to be Result1 or Result3; in the case of Result3, the tap value is adjusted so that the next comparison result is expected to be Result1; in the case of Result4, an alarm information is reported to indicate that the PE module 210 is incorrectly configured.
[0078] 7) Repeat steps 1 to 6 until the signal acquisition results of the two delay chains can stably feedback the tap value difference corresponding to the acquisition signal jump edge to the minimum, and send the two tap values at this time to the host computer to complete the detection of the signal jump edge.
[0079] By performing signal analysis in the above manner, the resolution of signal transition edge detection is high, up to picosecond level. The signal transition edge detection function is realized by using more common and general FPGA chips, which is no longer limited by dedicated chips. In addition, using one FPGA chip can realize both signal delay function and logic control, and can also save printed circuit board space.
[0080] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0081] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. An input signal analysis device, characterized in that: include: An input signal delay module, connected to the PE module, is used to delay the comparison signal output by the PE module according to the configured delay parameter, and sample the delayed signal to obtain a sampled signal; A comparison processing module, connected to the input signal delay module, used to determine the actual sampling value according to the sampling signal analysis to obtain a comparison result; An input configuration module, connected to the input signal delay module and the comparison processing module, for adjusting the delay parameter of the input signal delay module according to the comparison result and the set target comparison result until the signal transition edge is stably detected, and obtaining the delay parameter corresponding to the input signal delay module and sending it to the result analysis module; The result analysis module is connected to the input configuration module and is used to determine the performance indicator data of the input signal according to the received delay parameter analysis.
2. The input signal analysis device according to claim 1, characterized in that: The comparison signal output by the PE module includes two output signals; the input signal delay module includes a first delay chain and a second delay chain, the first delay chain connects the PE module, the comparison processing module and the input configuration module; the second delay chain connects the PE module, the comparison processing module and the input configuration module.
3. The input signal analysis device according to claim 2, characterized in that: The first delay chain and the second delay chain are IODELAY delay chains.
4. The input signal analysis device according to claim 2, characterized in that: The sampling signal includes a first signal and a second signal. The comparison processing module performs a table lookup analysis based on the first signal and the second signal to determine an actual sampling value as the comparison result and outputs it to the input configuration module.
5. The input signal analysis device according to claim 4, characterized in that: The input configuration module detects, based on the received comparison result, that the first signal and the second signal are both stable at a low level during one sampling, and the first signal and the second signal are both stable at a high level during another sampling, and then determines that a signal transition edge is stably detected.
6. The input signal analysis device according to claim 5, characterized in that: The input configuration module sends the delay parameter of the input signal delay module when the first signal and the second signal are simultaneously stable at a high level, and the delay parameter of the input signal delay module when the first signal and the second signal are simultaneously stable at a low level, to the result analysis module; the result analysis module subtracts the received delay parameters and uses the difference as the performance indicator data of the input signal.
7. The input signal analysis device according to claim 5, characterized in that: When the input configuration module continuously detects that the first signal and the second signal are continuously and simultaneously at low levels, the input configuration module determines the range of the delay parameter of the input signal delay module and sends it to the result analysis module; or When the input configuration module continuously detects that the first signal and the second signal are continuously and simultaneously at high levels, the input configuration module determines the range of the delay parameter of the input signal delay module and sends it to the result analysis module.
8. A method for analyzing an input signal, characterized in that: include: The input signal delay module delays the comparison signal output by the PE module according to the delay parameter, and samples the delayed signal to obtain a sampling signal; The comparison processing module determines the actual sampling value according to the sampling signal analysis to obtain a comparison result; The input configuration module adjusts the delay parameter of the input signal delay module according to the comparison result and the set target comparison result until the signal transition edge is stably detected, and obtains the delay parameter corresponding to the input signal delay module and sends it to the result analysis module; The result analysis module determines the performance indicator data of the input signal according to the received delay parameter analysis.
9. A testing device, characterized in that: It comprises a waveform synthesis module, an output signal delay module and the input signal analysis device according to any one of claims 1 to 7, wherein the waveform synthesis module is connected to the output signal delay module, and the output signal delay module is used to connect to a device to be tested.
10. A testing system, characterized in that: It comprises a PE module and the test device according to claim 9, wherein the output signal delay module is connected to the PE module, the PE module is connected to the device to be tested, and the input signal delay module is connected to the PE module.
11. The test system according to claim 10, characterized in that: The PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the input signal delay module.