A method, system and device for optimizing program compilation for continuous memory access

Abstract

The present invention belongs to the field of computing software technology, and specifically relates to a program compilation optimization method, system and device for continuous memory access, and the method includes: storing memory access instructions in the intermediate code into a candidate instruction queue; grouping memory access instructions in pairs to obtain memory access instruction pairs; if the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG class memory access instruction, then adding an immediate instruction before the LDG class memory access instruction pair; based on the immediate instruction, converting the memory access instruction pair into the LDG class memory access instruction; otherwise directly converting the memory access instruction pair into the LDG class memory access instruction; merging and deleting redundant immediate instructions in the instruction sequence; and using a program composed of all converted LDG class memory access instructions as an optimization program. The present application has the effect of improving program operation efficiency and reducing code volume.

Description

Technical Field

[0001] The present invention belongs to the field of computing software technology, and in particular relates to a program compilation optimization method, system and device for continuous memory access. Background Art

[0002] RISC-V (Reduced Instruction Set Computer - V) is an open instruction set architecture (ISA) designed by the University of California, Berkeley in 2010. The design of RISC-V ISA aims to provide a simple and modular architecture to meet the needs of a wide range of applications from embedded to high-performance computing. The RISC-V instruction set includes a basic instruction set (RV64I) and a series of modular extension instruction sets, such as multiplication-division extension (M), atomic operation extension (A), floating point extension (F / D), etc. The design combines the simplicity of hardware implementation with good instruction set extensibility and software flexibility. Compared with other commercial instruction set architectures, RISC-V has the advantages of openness and modularity, so it has attracted many hardware engineers to design and implement RISC-V processors that meet various market needs. At the same time, it has also attracted many software engineers to develop efficient compiler tool chains for it and compile and optimize customer application software.

[0003] In RISC-V processors, memory access is a key performance bottleneck, especially for high-performance processors such as superscalar out-of-order processors. Memory access usually requires more clock cycles to complete than other instructions (such as arithmetic instructions). This bottleneck cannot be simply solved by hardware iteration and upgrade, because the memory frequency is basically always lower than the processor main frequency, so memory access operations are always slower than the processor's instruction calculation speed (and the gap is gradually widening), and the processor has a limited number of memory access processing units, while program memory access operations are usually triggered multiple times in a short period of time, resulting in a shortage of processing units and instruction execution needs to wait in line, resulting in low program execution efficiency and large program memory usage. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a program compilation optimization method, system and device for continuous memory access, which can reduce the number of memory accesses, improve program execution efficiency and reduce instruction size.

[0005] A program compilation optimization method for continuous memory access, comprising:

[0006] Compile the encoded program to obtain an intermediate code;

[0007] Traversing the intermediate code, and storing the memory access instructions in the intermediate code into a candidate instruction queue;

[0008] Grouping memory access instructions in the candidate instruction queue in pairs to obtain memory access instruction pairs, wherein a plurality of memory access instruction pairs form a memory access instruction pair queue;

[0009] Determine whether the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction;

[0010] If the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction, then an immediate instruction is added to the memory access instruction pair;

[0011] Based on the immediate instruction, convert the memory access instruction pair into an LDG-type memory access instruction;

[0012] If the low address offset in the memory access instruction pair is less than or equal to the value range of the immediate operand of the LDG class memory access instruction, then based on the low address offset and the base register, convert the memory access instruction pair into an LDG class memory access instruction;

[0013] All converted LDG-type memory access instructions are inserted into corresponding positions in the encoded program to form a new program as an optimized program.

[0014] Optionally, traversing the intermediate code and storing the memory access instructions in the intermediate code into the candidate instruction queue includes:

[0015] Determine whether the candidate instruction queue is empty before the memory access instruction in the intermediate code is stored;

[0016] If the candidate instruction queue is not empty, determining whether to store the current memory access instruction into the candidate instruction queue based on a preset rule;

[0017] If the candidate instruction queue is empty, the current memory access instruction is stored in the candidate instruction queue.

[0018] Optionally, the determining whether to store the current memory access instruction into the candidate instruction queue based on a preset rule includes:

[0019] Determine whether the memory space of the current memory access instruction overlaps with the memory space of the memory access instructions in the candidate instruction queue, whether the operation code of the current memory access instruction is consistent with the operation code of the memory access instruction in the candidate instruction queue, and whether the base address register of the current memory access instruction is consistent with the base address register of the memory access instruction in the candidate instruction queue;

[0020] If the memory space of the current memory access instruction does not overlap with the memory space of the memory access instructions in the candidate instruction queue, the operation code of the current memory access instruction is consistent with the operation code of the memory access instruction in the candidate instruction queue, and the base register of the current memory access instruction is consistent with the base register of the memory access instruction in the candidate instruction queue, then the current memory access instruction is stored in the candidate instruction queue.

[0021] Optionally, the step of grouping the memory access instructions in the candidate instruction queue into pairs to obtain memory access instruction pairs comprises:

[0022] The memory access instructions with the same base address register in the candidate instruction queue are saved as an instruction queue;

[0023] According to the operation code of each memory access instruction in the instruction queue, determining whether there is a memory access instruction in the instruction queue that can form a memory access instruction pair;

[0024] If there are memory access instructions that can form a memory access instruction pair, the memory access instructions in the instruction queue that can form a memory access instruction pair are grouped in pairs to obtain a memory access instruction pair.

[0025] Optionally, the step of grouping the memory access instructions in the candidate instruction queue into pairs to obtain memory access instruction pairs comprises:

[0026] Determining whether the memory access instruction pair will trigger an unaligned instruction exception;

[0027] If the memory access instruction pair triggers a non-aligned instruction exception, the corresponding memory access instruction pair is deleted from the memory access instruction queue.

[0028] Optionally, the LDG class memory access instructions form an LDG class memory access instruction queue, and converting the memory access instruction pair into an LDG class memory access instruction comprises:

[0029] Determining whether addresses of adjacent LDG class memory access instructions in the LDG class memory access instruction queue are continuous;

[0030] If the addresses of adjacent LDG-type memory access instructions in the memory access instruction queue are continuous, the LDG-type memory access instructions with continuous addresses are used as a merge queue, and redundant immediate instructions in the merge queue are deleted.

[0031] Optionally, the value range of the immediate operand of the LDG class memory access instruction depends on the hardware design specifications of the LDG class instruction.

[0032] A program compilation optimization system for continuous memory access, comprising:

[0033] A compiling module is used to compile the encoded program to obtain an intermediate code;

[0034] A traversal module, used for traversing the intermediate code and storing the memory access instructions in the intermediate code into a candidate instruction queue;

[0035] A teaming module, used for teaming the memory access instructions in the candidate instruction queue in pairs to obtain memory access instruction pairs, wherein a plurality of memory access instruction pairs form a memory access instruction pair queue;

[0036] A judging module, used for judging whether the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction;

[0037] A first execution module, if the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction, the first execution module is used to add an immediate instruction in the memory access instruction pair;

[0038] A conversion module, used for converting the memory access instruction pair into an LDG-type memory access instruction based on the immediate instruction;

[0039] A second execution module, if the low address offset in the memory access instruction pair is less than or equal to the value range of the immediate operand of the LDG class memory access instruction, the second execution module is used to convert the memory access instruction pair into the LDG class memory access instruction based on the low address offset and the base address register;

[0040] The merging module is used to insert all converted LDG-type memory access instructions into corresponding positions in the encoded program to form a new program as an optimized program.

[0041] A terminal device comprises a memory and a processor. The memory stores a computer program that can be run on the processor. When the processor loads and executes the computer program, a program compilation optimization method oriented to continuous memory access is adopted.

[0042] A computer-readable storage medium stores a computer program. When the computer program is loaded and executed by a processor, a program compilation optimization method oriented to continuous memory access is adopted.

[0043] The beneficial effects of the present invention are as follows: the encoded program is compiled by a compiler to obtain a number of intermediate codes, and then the intermediate codes are traversed to screen out the memory access instructions therein and store them in a candidate instruction queue, and then the candidate instruction queues are grouped in pairs to obtain a memory access instruction pair, and it is determined whether the low address offset in the memory access instruction pair is greater than the value range of N. If it is less than or equal to, the memory access instruction pair is directly converted into an LDG-class memory access instruction, and the converted LDG-class memory access instructions are used to form a new program as an optimized program. If it is greater than, that is, it exceeds the hardware design limit of the LDG-class memory access offset, the offset step filling method adds an immediate instruction to further increase the number of LDG-class memory access instructions generated, and replaces two consecutive memory access instructions with one consecutive LDG-class memory access instruction, thereby improving the program's running performance and reducing the code volume. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 The present invention is a flowchart of a method for optimizing program compilation for continuous memory access. DETAILED DESCRIPTION

[0045] A program compilation optimization method for continuous memory access, such as Figure 1 As shown, the present invention includes:

[0046] S100, compile the encoded program to obtain an intermediate code.

[0047] Specifically, the compiler compiles the program encoded in the high-level language and converts the program into an intermediate code (IR) based on RISC-V ISA. The source code of the high-level language is divided into multiple stages in the compilation process of the compiler. The front-end is responsible for converting the program from the high-level language to the compiler's IR, and the optimizer (Middle-end) is used to optimize the performance of the expression sequence converted to IR; the back-end converts the optimized intermediate code into machine code for each platform. Among them, since there are many different optimization algorithms and theories, the middle-end stage also has many corresponding optimization steps that follow one after another. The above-mentioned front-end stage and middle stage are independent of the processor, because the form of the IR in the middle stage does not involve any hardware characteristics of the target processor. LDG-class memory access instructions are customized instructions based on the RISC-V ISA processor. Therefore, in order to fully explore more LDG-class memory access instruction conversion opportunities, this example will be implemented in the back-end of the compiler.

[0048] S110, traverse the intermediate code, and store the memory access instructions in the intermediate code into the candidate instruction queue.

[0049] Specifically, traverse the intermediate expression and select memory access instructions suitable for optimization. Memory access instructions are instructions that implement memory access operations. Memory access instructions are a very critical part of computer programs and are used to read or write data from memory. Ensuring data address alignment can improve program performance and reduce the possibility of exceptions. For all instructions in the basic block in the IR, traverse from top to bottom according to the instruction sequence. If the current memory access instruction is a memory access instruction and meets the storage conditions, it will be stored in the candidate instruction queue.

[0050] The storage conditions are as follows: traversing the intermediate code, storing the memory access instructions in the intermediate code into the candidate instruction queue includes:

[0051] S1100, determining whether the candidate instruction queue before the memory access instruction in the intermediate code is stored is empty.

[0052] Specifically, if the candidate queue is empty before the current memory access instruction is ready to be stored in the candidate queue, that is, the current memory access instruction is the first instruction, it is not necessary to consider the impact of other instructions on the current memory access instruction and store it in the candidate queue.

[0053] S1101: If the candidate instruction queue is not empty, determine whether to store the current memory access instruction into the candidate instruction queue based on a preset rule.

[0054] Specifically, if there is already an instruction in the candidate queue before the current memory access instruction is stored, before the current memory access instruction is stored in the candidate instruction, the current memory access instruction needs to meet a preset rule before it can be stored in the candidate instruction queue.

[0055] The default rules are:

[0056] Determining whether to store the current memory access instruction into the candidate instruction queue based on a preset rule includes:

[0057] S11000, determining whether the memory space of the current memory access instruction overlaps with the memory space of the memory access instruction in the candidate instruction queue, whether the operation code of the current memory access instruction is consistent with the operation code of the memory access instruction in the candidate instruction queue, and whether the base address register of the current memory access instruction is consistent with the base address register of the memory access instruction in the candidate instruction queue;

[0058] S11001. If the memory space of the current memory access instruction does not overlap with the memory space of the memory access instructions in the candidate instruction queue, the operation code of the current memory access instruction is consistent with the operation code of the memory access instruction in the candidate instruction queue, and the base address register of the current memory access instruction is consistent with the base address register of the memory access instruction in the queue, then the current memory access instruction is stored in the candidate instruction queue.

[0059] Specifically, it is necessary to ensure that there is no overlap in the access memory space of the current memory access instruction and the memory access instructions in the queue, the operation code of the current memory access instruction is consistent with the memory access instructions in the queue, and the base address register of the current memory access instruction is consistent with the base address register of the instructions in the queue.

[0060] Ensure that the memory space accessed by the current memory access instruction and the memory access instruction in the queue does not overlap, and ensure that the memory areas accessed by the memory access instructions in the same queue are independent and do not overlap or interfere with each other. This can avoid data dependency problems and ensure that memory access instructions can be processed in parallel or reordered, thereby improving execution efficiency. Whether the memory space accessed by the current memory access instruction and the memory access instruction in the queue does not overlap is determined by the base register and address offset. The base register determines the starting address of the memory access, and the address offset determines the specific memory location relative to the base address. Ensuring that the memory space does not overlap requires checking the combination of the base register and the address offset.

[0061] The opcode of the current memory access instruction is consistent with the memory access instructions in the queue, ensuring that the memory access instructions in the same queue perform the same operation (such as load or store). Consistent opcodes help identify patterned memory access operations, and the compiler can better optimize, such as merging adjacent identical operations to reduce the number of instructions. The opcode of the current memory access instruction is consistent with the memory access instructions in the queue, which can be directly judged by the opcode. The opcode is a field of the instruction that determines the specific operation performed by the instruction.

[0062] Intermediate code is an abstract representation used by the compiler when converting a high-level language program into a target instruction set architecture (such as RISC-V ISA). It is located between the source code and the target machine code. The intermediate code is an abstraction of the source code, and its purpose is to simplify the compiler's analysis and optimization process. It does not depend on a specific hardware platform, making it easier for the compiler to perform subsequent optimization and code generation. The intermediate code includes various types of instructions, such as load, store, arithmetic and logic instructions, and exception handling instructions.

[0063] The base register of the current memory access instruction is consistent with the base register of the instructions in the queue, ensuring that the memory access instructions in the same queue use the same base register. This ensures that the address calculation method of these instructions is consistent, which is conducive to optimizing the merging of address calculations and reducing repeated calculations of base registers, thereby improving instruction execution efficiency. The consistency of the base register of the current memory access instruction and the base register of the instructions in the queue is determined by the base register. The base register is the register specified in the instruction for memory access, which determines the basic address of the memory access.

[0064] S1102: If the candidate instruction queue is empty, store the current memory access instruction into the candidate instruction queue.

[0065] S120 , grouping memory access instructions in the candidate instruction queue in pairs to obtain memory access instruction pairs, and multiple memory access instruction pairs form a memory access instruction queue.

[0066] The memory access instructions in the candidate instruction queue are grouped in pairs, and the memory access instruction pairs obtained include:

[0067] S1200. Save the memory access instructions with the same base address register in the candidate instruction queue into one instruction queue.

[0068] S1201. According to the operation code of each memory access instruction in the instruction queue, determine whether there is a memory access instruction in the instruction queue that can form a memory access instruction pair.

[0069] S1202. If there are memory access instructions that can form a memory access instruction pair, group the memory access instructions in the instruction queue that can form a memory access instruction pair into pairs to obtain a memory access instruction pair.

[0070] Specifically, since the base address registers of the memory access instructions in the candidate instruction queue are the same, it is determined whether they are the same type of instructions based on the opcode. If so, step S1202 is executed, indicating that there are instructions in the candidate queue that can form a memory access instruction pair. If not, a memory access instruction pair cannot be formed.

[0071] After forming instruction pairs, not all instruction pairs can be converted to obtain memory access instruction pairs.

[0072] The memory access instructions in the candidate instruction queue are grouped in pairs, and the memory access instruction pairs obtained include:

[0073] Determine whether the memory access instruction pair will trigger a non-aligned instruction exception;

[0074] If the memory access instruction pair triggers a non-aligned instruction exception, the corresponding memory access instruction pair is deleted from the memory access instruction queue.

[0075] Specifically, the misaligned instruction exception refers to the data address being aligned to a multiple of its size. For example, a 32-bit integer (4 bytes) usually requires its address to be a multiple of 4. If the data address does not meet the alignment requirement, the system may generate a misaligned instruction exception, affecting performance or even causing errors.

[0076] Therefore, if the composed memory access instruction pair triggers a non-aligned instruction exception, the instruction cannot run normally and needs to be deleted from the instruction queue to ensure that every instruction in the instruction queue can be converted.

[0077] S130, determining whether the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction.

[0078] S140. If the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction, then an immediate instruction is added to the memory access instruction pair.

[0079] Specifically, the immediate instruction is added before the memory access instruction pair to transform the memory access instruction pair.

[0080] Convert the LD instruction pair in the instruction pair queue into LDG, where the base register of LDG is the base register rs of the LD instruction pair, and the offset is the offset offset of the low-address LD instruction in the instruction pair. If the value of offset exceeds the value range of the LDG instruction imm operand* (immediate instruction), then assign imm to 0, insert the ADDI instruction in front of the LDG instruction, and use the ra register as the base register of the current LDG instruction. In this embodiment, the value range of the immediate operand of the LDG class memory access instruction is represented by N.

[0081] For example, suppose the compiler backend generates the following intermediate code: ...

[0082] LD rd1, rs, N;

[0083] LD rd2, rs, N+8;

[0084] After being converted into LDG class memory access instructions, it becomes: ...

[0085] ADDI ra, rs, N;

[0086] LDG rd1, rd2, ra, 0; ...

[0087] Among them, the value of N is greater than the value range of the immediate operand of the LDG class memory access instruction. LD represents a 64-bit data load instruction, which is used to load a 64-bit data from the memory to the register. rd1 is the target register, which is used to store the loaded 64-bit data. rs is the source register, which is used to store the base address of the memory address. N is a constant offset, which is used to calculate the exact memory address of the data to be loaded. ADDI represents AddImmediate, which is used to add an immediate number to the value of a register. ra is the target register, which is used to store the calculation result. The function of this instruction is to add the value in the rs register to the constant N, and the result is stored in the ra register. The value range of the immediate operand of the LDG class memory access instruction depends on the hardware design specifications of the LDG class instruction.

[0088] LDG represents an instruction capable of loading 128-bit data. It is used to load a 128-bit from memory. rd1 is the target register, which is used to store the lower 64 bits of the loaded 128-bit data. rd2 is the target register, which is used to store the upper 64 bits of the loaded 128-bit data. ra is the base register, which stores the base address of the memory address. 0 is the offset, which indicates the exact memory address starting from the base address ra. The effect of this instruction is to load the 128-bit data stored at the address ra in the memory into registers rd1 and rd2, where rd2 stores the upper 64 bits of the data and rd1 stores the lower 64 bits of the data. Therefore, the function of this code snippet is to load two 64-bit data from the memory, which are stored in the rd1 and rd2 registers respectively, and calculate the address through the ADDI instruction, and use the LDG instruction to load the two 64-bit data into the target register.

[0089] Comparing the intermediate codes before and after optimization, we found that because the value of N exceeds the value range of the imm operand of LDG, an additional ADDI instruction is inserted into the optimized instruction sequence. Therefore, in this example, the size of the executable file generated after compilation is not reduced. However, the execution time of ADDI is less than that of memory access instructions such as LD in most processors. In other words, if the instruction sequence before optimization in this example appears, after optimization by this method, the purpose of optimizing the program memory access efficiency can still be achieved.

[0090] The value range of the immediate operand of the LDG class memory access instruction depends on the hardware design specifications of the LDG class instruction.

[0091] S150. Based on the immediate instruction, convert the memory access instruction pair into an LDG type memory access instruction.

[0092] S160. If the low address offset in the memory access instruction pair is less than or equal to the value range of the immediate operand of the LDG class instruction, the memory access instruction pair is converted into an LDG class memory access instruction based on the low address offset and the base register.

[0093] The LDG class memory access instructions form an LDG class memory access instruction queue, and converting the memory access instruction pair into the LDG class memory access instruction comprises:

[0094] S1600. Determine whether the addresses of adjacent LDG memory access instructions in the LDG memory access instruction queue are continuous.

[0095] S1601. If the addresses of adjacent LDG memory access instructions in the LDG memory access instruction queue are continuous, the LDG memory access instructions with continuous addresses are used as a merge queue, and redundant immediate instructions in the merge queue are deleted.

[0096] Specifically, the generated LDG instruction is inserted into the corresponding position. Since the value of the address offset exceeds the value range of the imm operand of the LDG instruction, some ADDI instructions are added. In some cases, the addition of ADDI is redundant, so it can be merged and deleted. If the addresses of adjacent LDG instructions in the instruction queue are continuous, if they are continuous, these LDG instructions are saved using the queue. Then the LDG instruction queue is grouped into groups of N+1. The value of N is the maximum value of the imm operand of the LDG instruction.

[0097] Finally, the ADDI inserted in the LDG instruction group to access the high address space LDG is deleted, and the value of the imm operand in the high address space is updated. At this time, all memory access instructions are converted into LDG memory access instructions and saved in the form of a merge queue.

[0098] All converted LDG-type memory access instructions are inserted into the corresponding positions of the original program in the form of a merge queue to form a new optimized program.

[0099] For example, the compiler backend generates the following intermediate code: ...

[0100] LD rd1, rs, N;

[0101] LD rd2, rs, N+8;

[0102] LD rd1, rs, N+16;

[0103] LD rd2, rs, N+24;

[0104] LD rd1, rs, N+32;

[0105] LD rd2, rs, N+40;

[0106] LD rd1, rs, N+48;

[0107] LD rd2, rs, N+56; ...

[0108] After optimization by the patented method of this invention, the code is as follows: ...

[0109] ADDI ra, rs, N;

[0110] LDG rd1, rd2, ra, 0;

[0111] LDG rd3, rd4, ra, 1;

[0112] LDG rd5, rd6, ra, 2;

[0113] LDG rd7, rd8, ra, 3; ...

[0114] Comparing the codes before and after optimization, we found that the data loading task that required 8 LD instructions to complete only required 4 LDG instructions and 1 ADDI after optimization. In terms of the number of instructions, the number of instructions was reduced from 8 to 5. In general, in this example, the size of the executable file generated after compilation was reduced, and the memory access efficiency of the program was optimized.

[0115] It is worth mentioning that in this implementation example, the LD memory access instruction is used to illustrate the method, but these examples do not mean that the method can only be used for this instruction. The use of the LD memory access instruction is only for the convenience of description. In fact, the method used in this embodiment is also applicable to instructions such as SD, SW, and LW. When used for these memory access instructions, it is only necessary to make corresponding conversions according to the specific memory access instructions. In this embodiment, the instructions that implement these similar expressions are collectively referred to as memory access instructions.

[0116] S170. Insert all converted LDG memory access instructions into corresponding positions in the encoded program to form a new program as an optimized program.

[0117] A program compilation optimization system for continuous memory access, comprising:

[0118] A compiling module is used to compile the encoded program to obtain an intermediate code;

[0119] A traversal module, used for traversing the intermediate code and storing the memory access instructions in the intermediate code into a candidate instruction queue;

[0120] A teaming module, used for teaming the memory access instructions in the candidate instruction queue in pairs to obtain memory access instruction pairs, wherein a plurality of memory access instruction pairs form a memory access instruction pair queue;

[0121] A judging module, used for judging whether the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction;

[0122] A first execution module, if the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction, the first execution module is used to add an immediate instruction before the memory access instruction pair;

[0123] A conversion module, used for converting the memory access instruction pair into an LDG-type memory access instruction based on the immediate instruction;

[0124] A second execution module, if the low address offset in the memory access instruction pair is less than or equal to the value range of the immediate operand of the LDG class memory access instruction, the second execution module is used to convert the memory access instruction pair into the LDG class memory access instruction based on the low address offset and the base address register;

[0125] The merging module is used to insert all converted LDG-type memory access instructions into corresponding positions in the encoded program to form a new program as an optimized program.

[0126] An embodiment of the present application also discloses a terminal device, including a memory and a processor. The memory stores a computer program that can be run on the processor. When the processor loads and executes the computer program, a program compilation optimization method for continuous memory access is adopted.

[0127] The terminal device may be a computer device such as a desktop computer, a laptop computer or a cloud server, and the terminal device includes but is not limited to a processor and a memory. For example, the terminal device may also include input and output devices, a network access device and a bus.

[0128] Among them, the processor can adopt a central processing unit (CPU). Of course, according to actual usage, other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. can also be adopted. The general-purpose processor can adopt a microprocessor or any conventional processor, etc., and this application does not impose any restrictions on this.

[0129] Among them, the memory can be an internal storage unit of the terminal device, such as a hard disk or memory of the terminal device, or it can be an external storage device of the terminal device, such as a plug-in hard disk, a smart memory card (SMC), a secure digital card (SD) or a flash memory card (FC) equipped on the terminal device, and the memory can also be a combination of an internal storage unit and an external storage device of the terminal device. The memory is used to store computer programs and other programs and data required by the terminal device. The memory can also be used to temporarily store data that has been output or is to be output, and this application does not impose any restrictions on this.

[0130] Among them, through this terminal device, a program compilation optimization method for continuous memory access in the above embodiment is stored in the memory of the terminal device, and is loaded and executed on the processor of the terminal device for easy use.

[0131] An embodiment of the present application further discloses a computer-readable storage medium, and the computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, a program compilation optimization method for continuous memory access in the above embodiment is adopted.

[0132] Among them, the computer program can be stored in a computer-readable medium, the computer program includes computer program code, the computer program code can be in the form of source code, object code, executable file or certain middleware, etc. The computer-readable medium includes any entity or device that can carry the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the computer-readable medium includes but is not limited to the above-mentioned components.

[0133] Among them, through this computer-readable storage medium, a program compilation optimization method for continuous memory access in the above embodiment is stored in a computer-readable storage medium, and is loaded and executed on a processor to facilitate the storage and application of the above method.

[0134] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of protection of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0135] One or more embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A program compilation optimization method for continuous memory access, characterized in that: include: Compile the encoded program to obtain an intermediate code; Traversing the intermediate code, and storing the memory access instructions in the intermediate code into a candidate instruction queue; Grouping memory access instructions in the candidate instruction queue in pairs to obtain memory access instruction pairs, wherein a plurality of memory access instruction pairs form a memory access instruction pair queue; Determine whether the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction; If the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type memory access instruction, then an immediate instruction is added to the memory access instruction pair; Based on the immediate instruction, convert the memory access instruction pair into an LDG-type memory access instruction; If the low address offset in the memory access instruction pair is less than or equal to the value range of the immediate operand of the LDG class memory access instruction, then based on the low address offset and the base register, convert the memory access instruction pair into an LDG class memory access instruction; All converted LDG-type memory access instructions are inserted into corresponding positions in the encoded program to form a new program as an optimized program.

2. A method for optimizing program compilation for continuous memory access as claimed in claim 1, characterized in that: The traversing the intermediate code and storing the memory access instructions in the intermediate code into the candidate instruction queue comprises: Determine whether the candidate instruction queue is empty before the memory access instruction in the intermediate code is stored; If the candidate instruction queue is not empty, determining whether to store the current memory access instruction into the candidate instruction queue based on a preset rule; If the candidate instruction queue is empty, the current memory access instruction is stored in the candidate instruction queue.

3. A method for optimizing program compilation for continuous memory access as claimed in claim 2, characterized in that: The determining whether to store the current memory access instruction into the candidate instruction queue based on a preset rule comprises: Determine whether the memory space of the current memory access instruction overlaps with the memory space of the memory access instructions in the candidate instruction queue, whether the operation code of the current memory access instruction is consistent with the operation code of the memory access instruction in the candidate instruction queue, and whether the base address register of the current memory access instruction is consistent with the base address register of the memory access instruction in the candidate instruction queue; If the memory space of the current memory access instruction does not overlap with the memory space of the memory access instructions in the candidate instruction queue, the operation code of the current memory access instruction is consistent with the operation code of the memory access instruction in the candidate instruction queue, and the base register of the current memory access instruction is consistent with the base register of the memory access instruction in the candidate instruction queue, then the current memory access instruction is stored in the candidate instruction queue.

4. A method for optimizing program compilation for continuous memory access as claimed in claim 1, characterized in that: The step of grouping the memory access instructions in the candidate instruction queue into pairs to obtain memory access instruction pairs comprises: The memory access instructions with the same base address register in the candidate instruction queue are saved as an instruction queue; According to the operation code of each memory access instruction in the instruction queue, determining whether there is a memory access instruction in the instruction queue that can form a memory access instruction pair; If there are memory access instructions that can form a memory access instruction pair, the memory access instructions in the instruction queue that can form a memory access instruction pair are grouped in pairs to obtain a memory access instruction pair.

5. A method for optimizing program compilation for continuous memory access as claimed in claim 1, characterized in that: The step of grouping the memory access instructions in the candidate instruction queue into pairs to obtain memory access instruction pairs comprises: Determining whether the memory access instruction pair will trigger an unaligned instruction exception; If the memory access instruction pair triggers a non-aligned instruction exception, the corresponding memory access instruction pair is deleted from the memory access instruction pair queue.

6. A method for optimizing program compilation for continuous memory access as claimed in claim 5, characterized in that: The LDG class memory access instructions form an LDG class memory access instruction queue, and the converting of the memory access instruction pair into the LDG class memory access instruction comprises: Determining whether addresses of adjacent LDG class memory access instructions in the LDG class memory access instruction queue are continuous; If the addresses of adjacent LDG class memory access instructions in the LDG class memory access instruction queue are continuous, the LDG class memory access instructions with continuous addresses are used as a merge queue, and redundant immediate instructions in the merge queue are deleted.

7. A method for optimizing program compilation for continuous memory access as claimed in claim 1, characterized in that: The value range of the immediate operand of the LDG class memory access instruction depends on the hardware design specifications of the LDG class instruction.

8. A program compilation optimization system for continuous memory access, characterized in that: include: A compiling module is used to compile the encoded program to obtain an intermediate code; A traversal module, used for traversing the intermediate code and storing the memory access instructions in the intermediate code into a candidate instruction queue; A teaming module, used for teaming the memory access instructions in the candidate instruction queue in pairs to obtain memory access instruction pairs, wherein a plurality of memory access instruction pairs constitute a memory access instruction queue; A judging module, used for judging whether the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG type instruction; A first execution module, if the low address offset in the memory access instruction pair is greater than the value range of the immediate operand of the LDG class instruction, the first execution module is used to add an immediate instruction before the memory access instruction pair; A conversion module, used for converting the memory access instruction pair into an LDG-type memory access instruction based on the immediate instruction; A second execution module, if the low address offset in the memory access instruction pair is less than or equal to the value range of the operand, the second execution module is used to convert the memory access instruction pair into an LDG-type memory access instruction based on the low address offset and the base address register; The merging module is used to insert all converted LDG-type memory access instructions into corresponding positions in the encoded program to form a new program as an optimized program.

9. A terminal device, comprising a memory and a processor, characterized in that: The memory stores a computer program that can be run on the processor, and when the processor loads and executes the computer program, the optimization method according to any one of claims 1 to 7 is adopted.

10. A computer-readable storage medium having a computer program stored therein, characterized in that: When the computer program is loaded and executed by a processor, the optimization method according to any one of claims 1 to 7 is adopted.

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