Fault diagnosis method and device and computer readable storage medium

Abstract

The invention provides a fault diagnosis method and device and a computer readable storage medium, and is applied to the technical field of computers.The method comprises the steps that an instruction with the occurrence frequency smaller than a preset threshold value in a reference instruction stream generated by normally executing a sample program serves as a mark instruction, and after a to-be-processed instruction stream segment including an abnormal instruction is obtained, the to-be-processed instruction stream segment is processed; determining a target mark instruction closest to the first instruction of the to-be-processed instruction stream segment in the plurality of mark instructions, taking the target mark instruction as a starting instruction, determining an instruction which is inconsistent with the reference instruction stream in the same execution order in the to-be-processed instruction stream segment, positioning an abnormal instruction, and storing the abnormal instruction in the to-be-processed instruction stream segment in the to-be-processed instruction stream segment. According to the method, the target mark instruction is used as the initial instruction to compare the instruction stream segment to be processed with the reference instruction stream, the initial position of the comparison process is consistent, repeated positioning operation caused by positioning errors is avoided, the abnormal instruction positioning period is effectively shortened, and the fault diagnosis accuracy is improved. And the diagnosis efficiency of the function module is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a fault diagnosis method, device and computer-readable storage medium. Background Art

[0002] With the development of computer technology, computer devices are integrated with multiple functional modules that implement different preset functions by executing software programs. These functional modules need to execute software programs to complete necessary verification operations before they are officially put into production. Taking the processor core as an example, during the stage of functional verification of the processor core, the processor core needs to run the operating system program and further determine whether the processor core can operate normally based on the operation process of the operating system.

[0003] When the processor core runs the operating system, the number of instructions that need to be run is as high as billions. R&D personnel need to identify the instructions with abnormal execution among the billions of instructions, and then diagnose the processor core based on the abnormal instructions. Due to the large number of instructions and the long cycle of locating abnormal instructions, it takes a lot of time to diagnose the processor core, which is inefficient. Summary of the invention

[0004] In view of this, the present application is committed to providing a fault diagnosis method, device and computer-readable storage medium to solve the problems of long abnormal instruction locating cycle and low functional module diagnosis efficiency in the prior art.

[0005] In a first aspect, the present application provides a fault diagnosis method, comprising:

[0006] Obtaining a fragment of an instruction stream to be processed during the execution of a sample program by a function module to be diagnosed;

[0007] Determine a target marker instruction closest to the first instruction of the instruction stream fragment to be processed from a plurality of marker instructions, wherein the marker instruction includes an instruction whose number of appearances in the reference instruction stream generated by normal execution of the sample program is less than a preset threshold;

[0008] Taking the target flag instruction as a starting instruction, determining instructions in the to-be-processed instruction stream fragment that are inconsistent with the reference instruction stream at the same execution order, and obtaining abnormal instructions;

[0009] Performing a fault analysis on the functional module to be diagnosed based on the abnormal instruction.

[0010] In a possible implementation, determining the target flag instruction closest to the first instruction of the instruction stream fragment to be processed from the multiple flag instructions includes:

[0011] Determine at least one target instruction stream segment including the first instruction of the instruction stream segment to be processed from a plurality of reference instruction stream segments, wherein the plurality of reference instruction stream segments are obtained by dividing the reference instruction stream according to a preset step size;

[0012] Respectively determining the flag instructions included in each of the target instruction stream fragments;

[0013] Among the flag instructions included in each of the target instruction stream fragments, a target flag instruction closest to the first instruction is determined.

[0014] In a possible implementation, determining at least one target instruction stream segment including the first instruction of the target instruction stream segment from among the multiple reference instruction stream segments comprises:

[0015] Obtaining the number of instructions of the sample program that have been executed by the to-be-diagnosed functional module before the to-be-processed instruction stream segment;

[0016] Based on the number of instructions and the preset step size, at least one target instruction stream segment including the first instruction is determined from the plurality of reference instruction stream segments.

[0017] In a possible implementation, each of the reference instruction stream fragments is encoded according to the instruction execution order;

[0018] Based on the number of instructions and the preset step size, determining at least one target instruction stream segment including the first instruction from the plurality of reference instruction stream segments comprises:

[0019] Determining a reference code based on a quotient of the instruction quantity and the preset step length;

[0020] Determine a plurality of target codes based on the reference code and a preset screening window, wherein the preset screening window is used to limit the range of the target code and the plurality of target codes include the reference code;

[0021] At least one target instruction stream segment including the first instruction is determined from the reference instruction stream segments corresponding to the target codes.

[0022] In a possible implementation, determining at least one target instruction stream segment including the first instruction of the instruction stream segment to be processed from a plurality of reference instruction stream segments comprises:

[0023] Determine, among a plurality of reference instruction stream segments, a reference instruction stream segment that matches a target format corresponding to the instruction stream segment to be processed;

[0024] Determine, among the reference instruction stream segments matching the target format, at least one target instruction stream segment including the first instruction of the instruction stream segment to be processed;

[0025] or,

[0026] Determine the function characteristics of the target function to which any instruction in the instruction stream fragment to be processed belongs;

[0027] Determine, among a plurality of reference instruction stream segments, a reference instruction stream segment matching the function feature;

[0028] At least one target instruction stream segment including the first instruction of the instruction stream segment to be processed is determined in the reference instruction stream segment matching the function feature.

[0029] In a possible implementation manner, the respectively determining the flag instructions included in each of the target instruction stream fragments includes:

[0030] According to a preset mapping relationship between the reference instruction stream fragment and the flag instruction, the flag instruction included in each of the target instruction stream fragments is determined.

[0031] In a possible implementation, each of the reference instruction stream fragments is encoded according to the instruction execution order;

[0032] The preset mapping relationship includes a mapping relationship between the encoding of each reference instruction stream fragment and a flag instruction.

[0033] In a possible implementation manner, the process of creating the preset mapping relationship includes:

[0034] Acquire a reference instruction stream generated by the verified hardware module normally executing the sample program;

[0035] Determine as a marker instruction an instruction whose number of appearances in the reference instruction stream is less than the preset threshold;

[0036] Dividing the reference instruction stream into a plurality of reference instruction stream segments according to a preset step length, and determining a flag instruction included in each of the reference instruction stream segments;

[0037] Based on each of the reference instruction stream fragments and the flag instructions included in each of the reference instruction stream fragments, a preset mapping relationship between the flag instructions and the reference instruction stream fragments is created.

[0038] In a possible implementation, taking the target flag instruction as a starting instruction, determining instructions in the to-be-processed instruction stream fragment that are inconsistent with the reference instruction stream at the same execution order, and obtaining abnormal instructions, includes:

[0039] Extracting a first instruction stream segment starting with the target flag instruction and including the abnormal instruction from the instruction stream segments to be processed;

[0040] Extracting from the reference instruction stream a second instruction stream fragment that uses the target flag instruction as a starting instruction and has a length greater than or equal to the first instruction stream fragment;

[0041] In the first instruction stream fragment, instructions inconsistent with the second instruction stream fragment in the same execution order are determined to obtain abnormal instructions.

[0042] In a second aspect, the present application provides a fault diagnosis device, including: a loading module and a diagnosis module, wherein:

[0043] The loading module is used to load the function module to be diagnosed and control the function module to be diagnosed to execute the sample program;

[0044] The diagnostic module is communicatively connected to the loading module, and is used to execute the fault diagnosis method as described in any one of the first aspects of the present application.

[0045] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the fault diagnosis method as described in any one of the first aspects of the present application are implemented.

[0046] Based on the above content, the fault diagnosis method provided by the present application uses the instructions that appear less than the preset threshold in the reference instruction stream generated by the normal execution of the sample program as the marker instruction. Based on this, after obtaining the to-be-processed instruction stream fragment including the abnormal instruction, the target marker instruction closest to the first instruction of the to-be-processed instruction stream fragment is determined among multiple marker instructions, and the target marker instruction is further used as the starting instruction to determine the instructions that are inconsistent with the reference instruction stream in the same execution order in the to-be-processed instruction stream fragment, thereby locating the abnormal instruction, and finally performing fault analysis on the to-be-diagnosed functional module based on the abnormal instruction. The present method uses the target marker instruction as the starting instruction to compare the to-be-processed instruction stream fragment with the reference instruction stream, which can not only ensure the consistency of the starting position of the comparison process, but also improve the efficiency of determining the starting position because the target marker instruction is an instruction that appears less frequently. Using the reference instruction stream as the standard for locating the abnormal instruction can ensure the reliability of the abnormal instruction locating process and avoid repeated locating operations caused by locating errors. Therefore, the present method can effectively shorten the abnormal instruction locating cycle and improve the diagnostic efficiency of the functional module. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0048] Figure 1 It is a flow chart of a fault diagnosis method provided by an embodiment of the present invention.

[0049] Figure 2 It is a flow chart of another fault diagnosis method provided by an embodiment of the present invention.

[0050] Figure 3 This is a flowchart of another fault diagnosis method provided by an embodiment of the present invention.

[0051] Figure 4 It is a structural block diagram of a fault diagnosis device provided by an embodiment of the present invention.

[0052] Figure 5 It is a flow chart of a method for determining a mapping relationship between a flag instruction and a reference instruction stream fragment provided by an embodiment of the present invention.

[0053] Figure 6 It is a structural block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] As mentioned above, with the development of computer technology, computer devices are integrated with multiple functional modules that implement different preset functions by executing software programs, such as processor cores, system controllers, input / output processors, security modules, etc. These functional modules need to execute software programs to complete necessary verification operations before the computer devices are officially put into production to determine whether the computer devices can run the corresponding software programs normally. Taking the processor core as an example, during the stage of functional verification of the processor core, the processor core needs to run the operating system program, and further determine whether the processor core can run normally based on the operation process of the operating system.

[0056] It is understandable that the operating system has complex functions and a large system. Therefore, when the processor core runs the operating system, the number of instructions that need to be run is as high as billions. In other words, R&D personnel need to determine the abnormal instructions among the billions of instructions, and then diagnose the processor core based on the abnormal instructions. Due to the large number of instructions and the long cycle of locating abnormal instructions, the actual diagnosis of the processor core takes a lot of time, the diagnostic efficiency is low, and it may even extend the entire product development cycle.

[0057] In order to solve the above technical problems, the present application provides a fault diagnosis method, which uses instructions that appear less than a preset threshold in a reference instruction stream generated by the normal execution of a sample program as marker instructions, and uses the target marker instruction that is closest to the first instruction of the instruction stream fragment to be processed among the marker instructions. The target marker instruction is used as the starting instruction to compare the instruction stream fragment to be processed with the reference instruction stream. This can not only ensure that the starting position of the comparison process is consistent, but also, since the target marker instruction is an instruction that appears less frequently, it can also improve the efficiency of determining the starting position. Using the reference instruction stream as the standard for locating abnormal instructions can ensure the reliability of the abnormal instruction locating process and avoid repeated positioning operations caused by positioning errors. Therefore, the present method can effectively shorten the abnormal instruction positioning cycle and improve the diagnostic efficiency of the functional module.

[0058] The fault diagnosis method provided in the present application is applied to an electronic device, which may be a hardware simulation device used to verify the physical architecture of the processor and simulate and verify the processor design, or an electronic product that can allow software programs, such as laptops, personal computers, and PDAs, and in some cases, may also be a server located remotely.

[0059] Combination Figure 1 As shown, the fault diagnosis method provided by the present application includes the following steps.

[0060] S100, obtaining a fragment of an instruction stream to be processed during the execution of a sample program by a function module to be diagnosed.

[0061] As mentioned above, the computer device includes a plurality of function modules for realizing preset functions, and the present embodiment defines the function modules that need to be diagnosed in each function module as the function modules to be diagnosed. In practical applications, the function module can simulate its application environment in the actual product through the hardware simulation device in the relevant technology, based on which, it is ensured that the function module smoothly executes the software program under the condition of relative independence (lack of other function modules), and the hardware simulation device can monitor the execution process of the software program during the operation of the function module, and report an error when the software program is executed abnormally. Therefore, in practical applications, a certain function module can be first loaded and run through the hardware simulation device, if the operation process is successfully completed, it can be basically determined that the function module is normal, on the contrary, if the function module is abnormal in the process of running the software program, it can be determined that there are some problems with the function module, in this case, the function module that is preliminarily run and reported by the hardware simulation device can be used as the function module to be diagnosed described in the present embodiment. Of course, in practical applications, after the design of the function module is completed, the fault diagnosis method provided by the present application can be directly applied to diagnose and verify the function module, which is also feasible.

[0062] Furthermore, as mentioned above, the functional module verification involved in this application requires the functional module to execute the corresponding software program. For the convenience of expression, this application defines the software program that runs the functional module to be diagnosed and verifies and diagnoses the functional module to be diagnosed based on the running process as a sample program. It can be understood that in actual applications, different functional modules implement different preset functions, and the software programs run are naturally different. Therefore, when diagnosing and analyzing different functional modules, it is necessary to use the software program corresponding to the functional module as the sample program of the corresponding functional module. Taking the processor core as an example, it is mainly used to load the operating system in actual applications. Therefore, when diagnosing and analyzing the processor core, the operating system program can be used as a sample program.

[0063] Based on the above content, in the process of the function module to be diagnosed executing the sample program, a corresponding instruction stream will be generated, and the instruction stream records the instructions executed in sequence in the process of the function module to be diagnosed executing the sample program. The fault diagnosis method provided by the present application is to diagnose the function module to be diagnosed based on the instruction stream generated in the process of the function module to be diagnosed executing the sample program. Considering that the instruction stream generated by the complete execution of the sample program by the function module to be diagnosed may include billions of instructions, it is extremely difficult to analyze the entire instruction stream. Therefore, the present application first obtains a part of the instruction stream in the process of the function module to be diagnosed executing the sample program as the instruction stream fragment to be processed, and performs diagnostic analysis on the function module to be diagnosed based on the instruction stream fragment to be processed.

[0064] In a possible implementation, the function module to be diagnosed is loaded on a hardware simulation device. The hardware simulation device can not only obtain the instruction stream generated by the function module to be diagnosed during the execution of the sample program, but more importantly, the hardware simulation device can also monitor the fault site during the execution of the sample program (it is impossible to monitor the abnormal execution of instructions). Based on this, if a fault is detected during the execution of the sample program, a certain number of instructions before the fault site, such as millions of instructions, can be intercepted. At the same time, a certain number of instructions after the fault site can be intercepted to obtain the instruction stream fragment to be processed including the fault site. With such a setting, it is possible to avoid analyzing and processing the instruction stream fragments with completely normal execution process, and only analyze and process the instruction stream fragments including the fault site, that is, including abnormal instructions, effectively improving the execution efficiency of fault diagnosis and avoiding wasting human and material resources.

[0065] S110. Determine, from among the multiple flag instructions, a target flag instruction that is closest to the first instruction of the instruction stream fragment to be processed.

[0066] Select a functional module that runs the same sample program as the functional module to be diagnosed and has been verified (for ease of expression, defined as a verified functional module), and obtain the complete instruction stream of the verified functional module during the sample program running process as a reference instruction stream. For example, if the functional module to be diagnosed is a processor core to be diagnosed, it is necessary to select a processor core that can run the same operating system as the processor core to be diagnosed and has been verified as a verified processor core, and use the complete instruction stream generated by loading the operating system on the verified processor core as a reference instruction stream.

[0067] Furthermore, instructions that appear less than a preset threshold in the reference instruction stream are filtered as flag instructions. As a preferred implementation, the preset threshold can be 3, that is, instructions that appear less than 3 times are used as flag instructions. Of course, ideally, instructions that appear only once can be used as flag instructions. The larger the value selected for the preset threshold, the more instructions can be used as flag instructions, which will lead to a decrease in the reference when determining the starting position of the comparison based on the flag instruction. Therefore, in practical applications, it is necessary to set the preset threshold in combination with the specific number of instructions contained in the instruction stream fragment to be processed and the reference instruction stream. The present application does not limit the specific value of the preset threshold.

[0068] Based on the above content, this step determines the target flag instruction closest to the first instruction of the instruction stream fragment to be processed among multiple flag instructions.

[0069] In an optional embodiment, reference may be made to Figure 2 The method provided by the illustrated embodiment determines a target flag instruction.

[0070] S1101. Determine, from a plurality of reference instruction stream segments, at least one target instruction stream segment including a first instruction of an instruction stream segment to be processed.

[0071] It can be understood that the reference instruction stream includes all instructions generated by the complete execution of the sample program by the verified functional module, including up to billions of instructions. In order to facilitate the storage of the reference instruction stream and determine the target flag instructions, after obtaining the reference instruction stream, the reference instruction stream is divided into multiple reference instruction stream fragments according to a preset step size, such as a step size of one million instructions.

[0072] Furthermore, since the functional module to be diagnosed and the verified functional module run the same sample program, the instructions included in the instruction stream to be processed and the instructions included in the corresponding instruction stream fragments in the reference instruction stream fragment should correspond one to one. In other words, based on the acquired instruction stream fragment to be processed, reference instruction stream fragments that can cover the instruction stream fragment to be processed can be screened out from the aforementioned multiple reference instruction stream fragments, thereby further narrowing the scope of the reference instruction stream used to locate abnormal instructions.

[0073] Based on the above content, first obtain the number of instructions of the sample program that the function module to be diagnosed has executed before the instruction stream segment to be processed. In an optional implementation, the hardware simulation device can obtain and record the sequence of each instruction generated by the function module in the process of executing the software program. Of course, in the process of storing the instruction stream, it is also stored in the execution order of each instruction. Based on this, for the determined instruction segment to be processed, the number of instructions of the sample program that the module to be diagnosed has executed before the segment can be obtained through the hardware simulation device. It can be understood that the number of instructions of the sample program that the module to be diagnosed has executed before the instruction segment to be processed is the approximate position of the first instruction of the instruction segment to be processed in the complete instruction stream.

[0074] Further, based on the number of instructions obtained and the preset step length used in the aforementioned process of dividing the reference instruction stream fragments, at least one target instruction stream fragment including the first instruction of the instruction stream fragment to be processed can be determined from the multiple reference instruction stream fragments. In a possible implementation, after the reference instruction stream is divided into multiple reference instruction stream fragments in advance, each reference instruction stream fragment is encoded according to the instruction execution order, for example, reference instruction stream fragments with codes of 1, 2, 3, etc. can be obtained. Based on this, the quotient of the number of instructions of the sample program executed by the module to be diagnosed before the instruction fragment to be processed and the aforementioned preset step length is calculated, and the quotient value is used as the reference code. In practical applications, if the number of instructions and the preset step length cannot be divided, the quotient value can be directly selected as the reference code, or the result of the upward carry can be used as the reference code, which is also feasible and also belongs to the scope of protection of this application. For example, the number of instructions of the sample program executed by the module to be diagnosed before the instruction fragment to be processed is 10 million, and the preset step length is 1 million, then the result of the division between the two is 10, which is the reference code. For another example, the number of instructions of the sample program executed by the module to be diagnosed before the instruction fragment to be processed is 10 million, and the preset step size is 1.2 million. Then, either the quotient 8 of the division between the two can be used as the reference code, or the result 9 after the carry upward can be used as the reference code.

[0075] Furthermore, multiple target codes are determined based on the obtained reference code and the preset screening window, wherein the preset screening window is used to limit the range of the target code. For example, the range formed by the first number of codes before the reference code and the second number of codes after the reference code can be used as the preset screening window. For example, if the reference code is 5, the first number is 2, and the second number is 4, then the range corresponding to the preset screening window is [3, 9]. All codes within the preset screening window are target codes. It can be seen that the multiple target codes screened according to this step include the target code determined in the above step.

[0076] After the target code is determined, at least one reference instruction stream segment including the first instruction of the instruction stream segment to be processed can be determined from the reference instruction stream segments corresponding to each target code as the target instruction stream segment.

[0077] It should be noted that although the first instruction of the instruction stream fragment to be processed is a specific instruction, in actual applications, if the instruction is in a loop body, the first instruction will appear repeatedly in the instruction stream. Therefore, there may be multiple target instruction stream fragments, and each target instruction stream fragment includes at least one of the first instructions.

[0078] S1102, respectively determine the flag instructions included in each target instruction stream fragment.

[0079] As an optional implementation, the present application provides a preset mapping relationship, which records the correspondence between reference instruction stream fragments and flag instructions. After the aforementioned steps, multiple target instruction stream fragments have been screened and obtained. For each target instruction stream fragment, the preset mapping relationship is queried to determine the flag instructions included in the target instruction stream fragment.

[0080] As mentioned above, as an optional implementation, each reference instruction stream segment is encoded according to the instruction execution order. Based on this, the aforementioned preset mapping relationship can specifically record the mapping relationship between the encoding of each reference instruction stream segment and the flag instruction. As for the specific creation process of the preset mapping relationship, it will be expanded in detail in the subsequent content and will not be described in detail here.

[0081] Of course, in another optional implementation, considering that the number of target instruction stream fragments is not very large, a traversal method can also be adopted to extract the flag instructions included in each target instruction stream fragment in turn.

[0082] S1103. Determine the target flag instruction closest to the first instruction among the flag instructions included in each target instruction stream fragment.

[0083] Based on the above steps, at least one target instruction stream segment including the above first instruction has been obtained. At the same time, since each instruction included in the instruction stream is executed sequentially during the actual execution of the sample program, the instruction order recorded in the instruction stream, that is, the execution order of the instructions, can be used to determine the closest flag instruction to the above first instruction in the flag instructions of each target instruction stream segment as the target flag instruction. It can be understood that the distance between the flag instruction and the first instruction of the instruction stream segment to be processed can be represented by the number of instructions spaced between the two. The more the number of spaced instructions, the farther the distance. Correspondingly, the fewer the number of spaced instructions, the closer the distance.

[0084] In another optional implementation, since different instruction areas of the software program correspond to different formats, each reference instruction stream fragment can also be screened based on the format of the instruction area. Specifically, first determine the target format corresponding to the instruction stream fragment to be processed, and then determine the reference instruction stream fragment that matches the target format among multiple reference instruction stream fragments. It can be understood that the matching with the target format mentioned in this embodiment refers to the reference instruction stream fragment corresponding to the same or similar format as the target format. Further, among the reference instruction stream fragments that match the aforementioned target format, determine at least one target instruction stream fragment that includes the first instruction of the instruction stream fragment to be processed. As for the specific implementation of determining the target instruction stream fragment, refer to the relevant content of the aforementioned embodiment, which will not be repeated here.

[0085] In another optional implementation, the reference instruction stream fragments may also be preliminarily screened based on the function features corresponding to the functions to which the instructions belong. Specifically, the function features of the target function to which any instruction in the instruction stream fragment to be processed belongs are first determined, wherein the specific implementation of determining the function features of any instruction may refer to the relevant technology and will not be described in detail here, based on the function features of the obtained target function, a reference instruction stream fragment matching the function features is determined among multiple reference instruction stream fragments, and further, among the reference instruction stream fragments matching the function features, at least one target instruction stream fragment including the first instruction of the instruction stream fragment to be processed is determined, as for the specific implementation of determining the target instruction stream fragment, the relevant contents of the aforementioned embodiments may be referred to and will not be repeated here.

[0086] S120, taking the target mark instruction as the starting instruction, determining in the to-be-processed instruction stream fragments the instructions that are inconsistent with the reference instruction stream at the same execution order, and obtaining abnormal instructions.

[0087] After determining the target flag instruction, that is, taking the target flag instruction as the starting instruction, starting from the target flag instruction, the instructions in the instruction stream segment to be processed are compared with the instructions at the same execution order in the reference instruction stream in sequence. Since the reference instruction stream is obtained by completely executing the sample program of the verified functional module, it can be used as a comparison standard. Therefore, if any instruction in the instruction stream segment to be processed is inconsistent with the instructions at the same execution order in the reference instruction stream, the instruction in the instruction stream segment to be processed is determined to be an abnormal instruction.

[0088] Based on the above comparison process, it can be known that the most important role of the target flag instruction determined through the above steps is to determine the starting point for comparing the instruction stream segment to be processed with the reference instruction stream segment, that is, taking the target flag instruction as the starting instruction. As mentioned above, the execution of the sample program by the functional module to be diagnosed may generate an instruction stream including up to billions of instructions. How to determine where to start the comparison among billions of instruction streams is extremely important in practical applications. Therefore, determining the target flag instruction is the key to improving the efficiency of determining abnormal instructions in this application.

[0089] It should be noted that, in combination with the screening process of the aforementioned target instruction stream fragment, it can be seen that the target instruction stream fragment may be located before the instruction stream fragment to be processed. Correspondingly, the flag instruction in the target instruction stream fragment may also be located before the aforementioned first instruction, and the comparison process is based on the target flag instruction as the starting instruction. This means that if the target flag instruction is located before the first instruction, it may be necessary to further supplement some instructions in the instruction stream fragment to be processed. Obviously, this will increase the amount of data in the comparison process. Therefore, when determining the target flag instruction, the flag instruction that is located after the aforementioned first instruction and closest to the first instruction can be preferentially selected as the target flag instruction.

[0090] In one possible implementation, the abnormal instruction may refer to Figure 3 The method provided by the illustrated embodiment is determined.

[0091] S1201. Extract a first instruction stream segment starting with a target mark instruction and including an abnormal instruction from the instruction stream segments to be processed.

[0092] In the case where the target flag instruction is located after the first instruction of the instruction stream segment to be processed, in order to further reduce the number of instructions to be compared, the first instruction stream segment starting with the target flag instruction and including the abnormal instruction is extracted from the instruction stream segment to be processed. Specifically, all instructions before the target flag instruction in the instruction stream segment to be processed are deleted, and the instructions after the target flag instruction are processed and trimmed based on the principle of including the abnormal instruction. It should be noted that the hardware simulation device can determine the approximate location of the fault site in the instruction stream segment to be processed, but cannot determine the abnormal instruction. Therefore, in this step, it is ensured that the fault site is included in the extracted first instruction stream segment, so that it can be determined that the abnormal instruction to be determined is included.

[0093] It should be further explained that, since the instructions before the target flag instruction in the instruction stream fragment to be processed need to be deleted, in order to avoid deleting the abnormal instructions to be determined, sufficient instruction margin should be reserved before the fault site when extracting the instruction stream fragment to be processed.

[0094] S1202: Extract from the reference instruction stream a second instruction stream fragment that starts with a target flag instruction and has a length greater than or equal to the first instruction stream fragment.

[0095] As mentioned above, the comparison between the instruction stream fragment to be processed and the reference instruction stream takes the target flag instruction as the starting instruction. Therefore, instructions are also extracted from the reference instruction stream with the target flag instruction as the starting instruction. At the same time, in order to ensure that the comparison of all instructions in the aforementioned first instruction stream fragment can be completed, the length of the second instruction stream fragment obtained in this step, that is, the number of instructions included, should be greater than or equal to the first instruction stream fragment.

[0096] S1203. In the first instruction stream fragment, determine instructions that are inconsistent with the second instruction stream fragment in the same execution order, and obtain abnormal instructions.

[0097] Referring to the aforementioned comparison process, each instruction in the first instruction stream fragment is compared with the instructions in the second instruction stream fragment with the same execution order. If the two are inconsistent, the instruction in the first instruction stream fragment is determined to be an abnormal instruction.

[0098] S130 , performing fault analysis on the function module to be diagnosed based on the abnormal instruction.

[0099] After determining the abnormal instruction, the fault analysis of the function module to be diagnosed can be performed based on the abnormal instruction. For example, the component that causes the abnormal execution of the instruction in the micro-architecture of the function module to be diagnosed can be determined based on the abnormal instruction, and then the RTL (Register Transfer Level) design of the function module to be diagnosed can be analyzed until the design defect is determined and the fault is eliminated. Of course, other fault analyses can also be performed on the function module to be diagnosed based on the abnormal instruction, which will not be listed here one by one. The specific implementation can be referred to the relevant technology, and this application does not make specific limitations on this.

[0100] To sum up, this method uses the target flag instruction as the starting instruction to compare the instruction stream fragment to be processed with the reference instruction stream, which can not only ensure the consistency of the starting position of the comparison process, but also improve the efficiency of determining the starting position because the target flag instruction is an instruction that appears less frequently. Using the reference instruction stream as the standard for locating abnormal instructions can ensure the reliability of the abnormal instruction locating process and avoid repeated positioning operations caused by positioning errors. Therefore, this method can effectively shorten the abnormal instruction positioning cycle and improve the diagnostic efficiency of the functional module.

[0101] The following introduces the optional creation process of the preset mapping relationship between the aforementioned reference instruction stream fragments and the flag instructions.

[0102] S200: Obtain a reference instruction stream generated by a verified hardware module executing a sample program normally.

[0103] For the definition of verified hardware modules and sample programs, as well as the specific process of obtaining reference instruction streams, please refer to the above Figure 1 The implementation of the relevant contents of S110 in the illustrated embodiment will not be repeated here.

[0104] S210: Determine that an instruction whose appearance number in the reference instruction stream is less than a preset threshold is a marker instruction.

[0105] The obtained reference instruction stream is screened, and instructions that appear less than a preset threshold in the reference instruction stream are used as flag instructions. As mentioned above, as a preferred implementation, the preset threshold can be 3, that is, instructions that appear less than 3 times are used as flag instructions. Of course, ideally, instructions that appear only once can be used as flag instructions. The larger the value selected for the preset threshold, the more instructions can be used as flag instructions, which will lead to a decrease in the reference when determining the starting position of the comparison based on the flag instruction. Therefore, in practical applications, it is necessary to set the preset threshold in combination with the specific number of instructions contained in the instruction stream fragment to be processed and the reference instruction stream.

[0106] S220, dividing the reference instruction stream into a plurality of reference instruction stream segments according to a preset step size, and determining a flag instruction included in each reference instruction stream segment.

[0107] After determining the flag instruction, the reference instruction stream can be divided into multiple reference instruction stream segments according to the preset step size. For example, the complete reference instruction stream can be divided according to the preset step size of 1 million instructions to obtain the corresponding reference instruction stream segments. In practical applications, the selection of the preset step size needs to be determined in combination with multiple factors including the total number of instructions in the reference instruction stream and the computing power of the device. This application does not limit the specific value of the preset step size.

[0108] After obtaining the reference instruction stream fragments, the flag instructions included in each reference instruction stream fragment are determined respectively. It can be understood that since the distribution of the flag instructions in the entire reference instruction stream is random, after the reference instruction stream is divided into multiple fragments, any reference instruction stream fragment may include at least one flag instruction or may not include any flag instruction.

[0109] S230: Based on each reference instruction stream fragment and a flag instruction included in each reference instruction stream fragment, create a preset mapping relationship between the flag instruction and the reference instruction stream fragment.

[0110] As mentioned above, for the reference instruction stream fragment including the flag instruction, a correspondence relationship between the flag instruction and the reference instruction stream fragment can be established. The set of these correspondence relationships is the preset mapping relationship provided in the present application.

[0111] As an optional implementation, in the process of dividing the reference instruction stream into multiple reference instruction stream fragments, each reference instruction stream fragment can be encoded in sequence according to the execution order of the instructions. For example, the first reference instruction stream fragment including 1 million instructions is encoded as 1, the second reference instruction stream fragment including 1 million instructions is encoded as 2, and so on, until the encoding of all reference instruction stream fragments is completed.

[0112] Furthermore, the correspondence between the reference instruction stream fragments and the flag instructions included therein is recorded in the form of an array. For example, if the flag instruction P1 appears in the reference instruction stream fragment of encoding 1, there is an array (P1, 1). Correspondingly, if the flag instruction P1 also appears in the reference instruction stream fragment of encoding 2, there is an array (P1, 2), and so on, until an array corresponding to all reference instruction stream fragments and flag instructions is created.

[0113] The set of these arrays is the preset mapping relationship between the flag instruction and the reference instruction stream fragment. It can be understood that for a certain sample program, the preset mapping relationship is prepared before the diagnosis analysis is performed on the diagnosis function module, and can be directly called in subsequent applications.

[0114] It should be noted that the mapping relationship between the flag instruction and the reference instruction stream fragment can also be reflected in other ways, which are not listed here one by one. Without exceeding the core idea of ​​the present application, they also fall within the scope of protection of the present application.

[0115] Furthermore, the present application also provides a fault diagnosis device, see Figure 5 As shown, the fault diagnosis device provided by the present application includes a loading module 10 and a diagnosis module 20, wherein:

[0116] The loading module 10 is used to load the function module to be diagnosed and control the function module to be diagnosed to execute a sample program;

[0117] The diagnosis module 20 is in communication with the loading module 10 and is used to execute the fault diagnosis method provided by any of the aforementioned embodiments.

[0118] Below, reference Figure 6 To describe the electronic device provided by the embodiment of the present invention, the electronic device provided by the embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0119] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 6 The communication connections shown for the processor 100, the communication interface 200, the memory 300, and the communication bus 400 are merely optional;

[0120] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0121] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0122] The processor 100 is specifically used to execute the application program in the memory to implement the steps of the fault diagnosis method described above.

[0123] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the fault diagnosis method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0124] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the fault diagnosis method according to various embodiments of the present application described in the above content of this specification.

[0125] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0126] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0127] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0128] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0129] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0130] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0131] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A fault diagnosis method, characterized in that: include: Obtaining a fragment of an instruction stream to be processed during the execution of a sample program by a function module to be diagnosed; Determine a target marker instruction closest to the first instruction of the instruction stream fragment to be processed from a plurality of marker instructions, wherein the marker instruction includes an instruction whose number of appearances in the reference instruction stream generated by normal execution of the sample program is less than a preset threshold; Taking the target flag instruction as a starting instruction, determining instructions in the to-be-processed instruction stream fragment that are inconsistent with the reference instruction stream at the same execution order, and obtaining abnormal instructions; Performing a fault analysis on the functional module to be diagnosed based on the abnormal instruction.

2. The method according to claim 1, characterized in that The step of determining a target flag instruction closest to the first instruction of the instruction stream fragment to be processed from among the plurality of flag instructions comprises: Determine at least one target instruction stream segment including the first instruction of the instruction stream segment to be processed from a plurality of reference instruction stream segments, wherein the plurality of reference instruction stream segments are obtained by dividing the reference instruction stream according to a preset step size; Respectively determining the flag instructions included in each of the target instruction stream fragments; Among the flag instructions included in each of the target instruction stream fragments, a target flag instruction closest to the first instruction is determined.

3. The method according to claim 2, characterized in that The step of determining at least one target instruction stream segment including the first instruction of the target instruction stream segment from among the plurality of reference instruction stream segments comprises: Obtaining the number of instructions of the sample program that have been executed by the to-be-diagnosed functional module before the to-be-processed instruction stream segment; Based on the number of instructions and the preset step size, at least one target instruction stream segment including the first instruction is determined from the plurality of reference instruction stream segments.

4. The method according to claim 3, characterized in that Each of the reference instruction stream fragments is encoded according to the instruction execution order; Based on the number of instructions and the preset step size, determining at least one target instruction stream segment including the first instruction from the plurality of reference instruction stream segments comprises: Determining a reference code based on a quotient of the instruction quantity and the preset step length; Determine a plurality of target codes based on the reference code and a preset screening window, wherein the preset screening window is used to limit the range of the target code and the plurality of target codes include the reference code; At least one target instruction stream segment including the first instruction is determined from the reference instruction stream segments corresponding to the target codes.

5. The method according to claim 2, characterized in that: The step of determining at least one target instruction stream segment including the first instruction of the instruction stream segment to be processed from a plurality of reference instruction stream segments comprises: Determine, among a plurality of reference instruction stream segments, a reference instruction stream segment that matches a target format corresponding to the instruction stream segment to be processed; Determine, among the reference instruction stream segments matching the target format, at least one target instruction stream segment including the first instruction of the instruction stream segment to be processed; or, Determine the function characteristics of the target function to which any instruction in the instruction stream fragment to be processed belongs; Determine, among a plurality of reference instruction stream segments, a reference instruction stream segment matching the function feature; At least one target instruction stream segment including the first instruction of the instruction stream segment to be processed is determined in the reference instruction stream segment matching the function feature.

6. The method according to claim 2, characterized in that The step of respectively determining the flag instructions included in each of the target instruction stream fragments comprises: According to a preset mapping relationship between the reference instruction stream fragment and the flag instruction, the flag instruction included in each of the target instruction stream fragments is determined.

7. The method according to claim 6, characterized in that Each of the reference instruction stream fragments is encoded according to the instruction execution order; The preset mapping relationship includes a mapping relationship between the encoding of each reference instruction stream fragment and a flag instruction.

8. The method according to claim 6, characterized in that The process of creating the preset mapping relationship includes: Acquire a reference instruction stream generated by the verified hardware module normally executing the sample program; Determine as a marker instruction an instruction whose number of occurrences in the reference instruction stream is less than the preset threshold; Dividing the reference instruction stream into a plurality of reference instruction stream segments according to a preset step length, and determining a flag instruction included in each of the reference instruction stream segments; Based on each of the reference instruction stream fragments and the flag instructions included in each of the reference instruction stream fragments, a preset mapping relationship between the flag instructions and the reference instruction stream fragments is created.

9. The method according to claim 1, characterized in that: Taking the target flag instruction as a starting instruction, determining instructions in the to-be-processed instruction stream fragment that are inconsistent with the reference instruction stream at the same execution order, and obtaining abnormal instructions, including: Extracting a first instruction stream segment starting with the target flag instruction and including the abnormal instruction from the instruction stream segments to be processed; Extracting from the reference instruction stream a second instruction stream fragment that uses the target flag instruction as a starting instruction and has a length greater than or equal to the first instruction stream fragment; In the first instruction stream fragment, instructions inconsistent with the second instruction stream fragment in the same execution order are determined to obtain abnormal instructions.

10. A fault diagnosis device, characterized in that: include: Loading modules and diagnostic modules, where The loading module is used to load the function module to be diagnosed and control the function module to be diagnosed to execute the sample program; The diagnosis module is communicatively connected with the loading module, and is used to execute the fault diagnosis method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the fault diagnosis method according to any one of claims 1 to 9 are implemented.

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