AXI bus channel back voltage duration monitoring circuit, method and chip

Abstract

The invention discloses an AXI bus channel back voltage duration monitoring circuit, method and chip, and belongs to the technical field of circuits, the AXI bus channel back voltage duration monitoring circuit comprises a register configuration module, a back voltage duration information statistics module and a delay information comparison module; wherein the register configuration module is used for performing write operation on a register required to be controlled and performing read operation on a state register; the back pressure duration information statistics module is used for counting back pressure duration information of commands of an AXI bus read address channel, a read data channel, a write address channel, a write data channel and a write response channel; and the delay information comparison module is used for counting the maximum back pressure duration, the minimum back pressure duration and the back pressure duration interval distribution, and reporting the interruption when the back pressure duration exceeds the threshold range. Monitoring, statistics and state feedback can be carried out on the back pressure duration of an AXI bus read address channel, a read data channel, a write address channel, a write data channel and a write response channel.

Description

Technical Field

[0001] The present invention belongs to the field of circuit technology, and in particular relates to an AXI bus channel back pressure duration monitoring circuit, method and chip. Background Art

[0002] With the rapid development of semiconductor technology, chip design is moving towards unprecedented complexity and integration, which is not only reflected in the surge in the number of transistors, but also in the diversification and high integration of internal chip functions. In this context, it is particularly important to ensure the correctness and reliability of chip functions, and state tracking, as a key means of verification and debugging, is becoming increasingly important.

[0003] 1. The significance of status tracking

[0004] State tracking can capture the status information of each module, register, signal and even data flow inside the chip in real time or on demand, providing developers with in-depth insights into chip behavior. This information is crucial for diagnosing problems, optimizing performance, and verifying the correctness of designs. Especially when an abnormality or failure occurs in the chip, quickly locating the source of the problem and understanding its mechanism can greatly shorten the time to market and reduce maintenance costs.

[0005] 2. Limitations of existing solutions

[0006] Detailed functions but poor versatility: Although IP-level debugging solutions such as ARM Coresight mentioned above can penetrate into the core processor for detailed status capture, their designs are often highly dependent on specific processor architectures or protocol standards and lack cross-platform and cross-architecture versatility.

[0007] Complex design and high cost: These advanced debugging functions often require complex hardware design and additional logic resources to implement, which increases the complexity of chip design and manufacturing costs. This contradiction is particularly prominent in resource-constrained embedded or low-power applications.

[0008] The circuit scale is large: In order to support comprehensive status tracking, a large number of monitoring points and buffer storage need to be deployed, which not only increases the chip area but also may affect the signal transmission speed and power consumption performance.

[0009] 3. Improvement direction and innovation trend

[0010] Software Defined Hardware (SDH) and Programmable Debugging: By introducing programmable logic or FPGA technology, the debugging function can be flexibly configured and expanded according to actual needs, improving the flexibility and versatility of the system. At the same time, advanced software tool chains are used to automate the debugging process and reduce the complexity and error rate of manual intervention.

[0011] Lightweight and high-performance design: Develop a more compact and efficient state tracking mechanism, such as event-based or on-demand capture, to reduce unnecessary monitoring overhead. At the same time, optimize data compression and transmission algorithms to ensure that key state information can still be captured under limited bandwidth and storage resources.

[0012] Multi-domain collaborative debugging: With the popularization of SoC (system-on-chip) design, cross-domain (such as processor, memory, peripherals, etc.) collaborative debugging has become a new challenge. Future debugging solutions will pay more attention to the integration and synchronization of cross-domain information, provide a unified debugging view and interface, and simplify the debugging process.

[0013] Security and privacy protection: In the process of state tracking, the security of sensitive data and user privacy must be strictly protected. Therefore, security measures such as encrypted transmission, access control, and data desensitization will become an indispensable part of future debugging solutions.

[0014] Conventional on-chip debug & trace solutions rely on IP, such as coresight of ARM processors, data packet-based information collection within the interconnect bus, etc., which are relatively more detailed in function, but lack versatility, and are complex in design and large in circuit scale.

[0015] The AXI (Advanced eXtensible Interface) bus is a widely used internal IP (intellectual property core) communication and interconnection standard in current chip design. It not only provides an efficient data transmission channel, but also provides designers with the ability to deeply observe and control the IP status through its rich signal set. The IP status can be obtained by observing the signal status on the bus, such as the timing of the master IP sending a command and whether the slave IP can receive commands from the master IP. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide an AXI bus channel back pressure duration monitoring circuit, method and chip to address the deficiencies in the above-mentioned prior art, so as to solve the technical problem that the master device and the slave device cannot know when the command issued by the master device is accepted by the slave device when communicating based on the AXI bus.

[0017] The present invention adopts the following technical solutions:

[0018] An AXI bus channel back pressure duration monitoring circuit includes a register configuration module, a back pressure duration information statistics module, and a delay information comparison module; wherein,

[0019] Register configuration module, used for writing operations to required control registers and reading operations to status registers;

[0020] The back pressure duration information statistics module is used to realize the statistics of the back pressure duration information of the AXI bus read address channel, read data channel, write address channel, write data channel and write response channel commands;

[0021] The delay information comparison module is used to count the maximum back pressure duration, the minimum back pressure duration, and the back pressure duration interval distribution, and report the interruption when the back pressure duration exceeds the threshold range;

[0022] Preferably, the register configuration module is used to receive commands from an external master device, and the interface between the register configuration module and the external master device is a standard APB bus interface or an interface defined by the user to meet functional requirements.

[0023] Preferably, the implementation process of the back pressure duration information statistics module is as follows:

[0024] The delay_reg signal stores the back pressure duration of each command in real time. When both valid and ready are 1, it remains 0, indicating that the back pressure duration of the command is 0.

[0025] Preferably, when valid is 1 and ready is 0, delay_reg is incremented by 1 at each rising edge of the clock, indicating that the back pressure duration of the corresponding command is incremented by 1.

[0026] Preferably, the maximum back pressure duration statistics are specifically as follows:

[0027] Each time wr_en is high, delay_reg is stored in delay_max, and the delay_reg value is compared with the delay_max value, and the larger value of the two is stored in the delay_max register;

[0028] The minimum back pressure duration statistics are as follows:

[0029] Each time wr_en is high, delay_reg is stored in delay_min, and the delay_reg value is compared with the delay_min value, and the larger value of the two is stored in the delay_min register;

[0030] The specific statistics of the back pressure duration interval distribution are as follows:

[0031] The back pressure duration information stored in delay_reg is compared with the "back pressure duration statistical interval information register group". If the back pressure duration meets the corresponding interval, the value of the back pressure duration distribution interval register is increased by 1. The external master device reads the back pressure duration distribution interval register group through the register configuration module to obtain the delay distribution of all commands.

[0032] Preferably, the interruption of reporting the back pressure duration exceeding the threshold range is specifically:

[0033] The delay information comparison module supports interrupt status feedback. If the back pressure duration of a command exceeds the threshold set by the interrupt trigger threshold register, an interrupt is triggered; the interrupt information is stored in the interrupt status register, and the external master device reads the interrupt status register through the register configuration module to know whether an interrupt occurs.

[0034] Preferably, the accumulated value of the back pressure duration distribution interval register group is equal to the value configured by the tracking command quantity register. When the two values ​​are not equal, the register configuration is modified.

[0035] Preferably, it also includes a status output function, and reports an interrupt when the back pressure duration exceeds a threshold range.

[0036] In a second aspect, an embodiment of the present invention provides an AXI bus channel back pressure duration monitoring method, comprising the following steps:

[0037] Count the back pressure duration of the AXI channel and the number of commands for collecting the back pressure duration information of the module; set the interval information of the back pressure duration, reserve ten groups of registers, each register defines a back pressure duration interval; set the threshold for reporting the back pressure duration interrupt; when the statistics of all command back pressure durations are completed, when the back pressure duration of a command exceeds the set back pressure duration reporting interrupt threshold, report an interrupt;

[0038] Read the number of commands in each back pressure duration interval; when all command back pressure duration statistics are completed, if the back pressure duration of a command exceeds the value defined in the interrupt trigger threshold register, the corresponding register is set to 1;

[0039] Get the minimum back pressure duration information of all commands by reading the minimum back pressure duration register;

[0040] By reading the maximum back pressure duration register, you can obtain the minimum back pressure duration information in all commands.

[0041] In a third aspect, a chip includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned AXI bus channel back pressure duration monitoring method when executing the computer program.

[0042] Compared with the prior art, the present invention has at least the following beneficial effects:

[0043] An AXI bus channel back pressure duration monitoring circuit comprises a register configuration module, a back pressure duration information statistics module and a delay information comparison module; the register configuration module is used for writing operations on required control registers and reading operations on status registers; the back pressure duration information statistics module is used for realizing statistics on command back pressure duration information of an AXI bus read address channel, a read data channel, a write address channel, a write data channel and a write response channel; the delay information comparison module is used for counting the maximum back pressure duration, the minimum back pressure duration and the back pressure duration interval distribution, and reporting an interrupt when the back pressure duration exceeds a threshold range; by real-time monitoring of the command back pressure duration of each channel (read address, read data, write address, write data and write response) of the AXI bus, congestion on the bus can be discovered and responded to in a timely manner. This helps to dynamically adjust data transmission strategies and avoid performance bottlenecks caused by bus congestion; based on the statistical maximum back pressure duration, minimum back pressure duration and back pressure duration interval distribution, the system can allocate bus bandwidth and priority more reasonably to ensure that data transmission of critical tasks is not affected, thereby improving overall system performance; when the back pressure duration exceeds the preset threshold, the circuit can trigger an interrupt and report it, so that the system can take timely countermeasures, such as adjusting task priority, increasing cache, etc., to avoid system crashes or data loss due to long-term bus congestion; the back pressure duration information statistics module can provide detailed back pressure duration data, including maximum and minimum back pressure duration and back pressure duration interval distribution. These data are crucial for system debugging and performance optimization, and can help developers quickly locate problems and take corresponding solutions. The register configuration module allows read and write operations on the required control registers and status registers, which allows users to flexibly configure the parameters and thresholds of the monitoring circuit according to actual needs to meet the needs of different application scenarios. By integrating the AXI bus channel back pressure duration monitoring circuit, system debuggers can more intuitively understand the data transmission on the bus, thereby speeding up the debugging progress and improving the debugging efficiency. The AXI bus channel back pressure duration monitoring circuit adopts an integrated design, integrating multiple functional modules into one circuit, reducing the occupation of hardware resources and wiring complexity. This helps to reduce the overall complexity and cost of system design. As the industry's widely used internal IP communication interconnection standard, the AXI bus has a high degree of standardization and compatibility in its interface. This allows the AXI bus channel back pressure duration monitoring circuit to be easily integrated and interoperable with various AXI bus-based IP cores, reducing the design difficulty and cost. Due to the wide application of the AXI bus in chip design, the AXI bus channel back pressure duration monitoring circuit has high reusability. Once the design is complete and verified, it can be reused in different projects, further reducing design costs and shortening design cycles.

[0044] Furthermore, the register configuration module is used to receive commands from an external master device, and the interface between the register configuration module and the external master device is a standard APB bus interface or an interface defined by the user to meet functional requirements.

[0045] Furthermore, when valid is 1 and ready is 0, delay_reg is incremented by 1 at each rising edge of the clock, indicating that the back pressure duration of the corresponding command is incremented by 1. This setting can calculate the back pressure duration of a command.

[0046] Furthermore, the maximum back pressure duration is counted to obtain the maximum back pressure duration information of the command, and the minimum back pressure duration is counted to obtain the minimum back pressure duration information of the command. The setting of the back pressure duration interval distribution can count the back pressure duration of each command in the commands that require back pressure duration into the corresponding interval.

[0047] Furthermore, the interruption of reporting the back pressure duration exceeding the threshold range can transmit the situation of the command back pressure duration being too long to the system through an interruption according to actual needs.

[0048] Furthermore, by modifying the register configuration, the back pressure duration of the interrupt reporting can be defined according to actual needs.

[0049] Furthermore, when the accumulated value of the back pressure duration distribution interval register group is equal to the value configured by the tracking command quantity register, it indicates that all command back pressure durations are distributed in the duration interval defined in the "back pressure duration statistical interval information register group".

[0050] A method for monitoring back pressure duration of an AXI bus channel is disclosed. When the back pressure duration exceeds a threshold range, an interrupt is reported. The system can learn through the interrupt whether the back pressure duration of a command exceeds a required range.

[0051] In summary, the present invention can monitor, count and provide status feedback on the back pressure duration of the AXI bus read address channel, read data channel, write address channel, write data channel and write response channel.

[0052] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 It is the circuit structure block diagram;

[0054] Figure 2 It is the timing diagram of the reverse voltage duration statistics circuit;

[0055] Figure 3 This is the statistical result chart;

[0056] Figure 4 A structural block diagram of a chip provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] In the description of the present invention, it should be understood that the terms “include” and “comprises” indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0059] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0060] It should be further understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0061] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0062] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0063] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0064] The present invention provides an AXI bus channel back pressure duration monitoring circuit, which monitors, counts and provides status feedback on the back pressure durations of an AXI bus read address channel, a read data channel, a write address channel, a write data channel and a write response channel. The back pressure duration is defined as the number of clock cycles between when a valid signal is valid and when a ready signal is valid. When valid is equal to 1, it is the timing start time. When both valid and ready are equal to 1, it is the timing end time.

[0065] Read address channel (AR): monitors ARVALID (valid address request) and ARREADY (address ready) signals. When ARVALID is 1 and ARREADY is 0, it indicates that back pressure occurs in the read address channel; when both ARVALID and ARREADY are 1, it indicates that the back pressure ends.

[0066] Read data channel (R): Although the read data channel itself does not directly generate back pressure (back pressure usually occurs in the read address channel), we can monitor the RVALID (valid read data) and RREADY (read data ready) signals to confirm whether the data is received in time. However, for direct monitoring of the back pressure duration, the focus is mainly on the read address channel.

[0067] Write address channel (AW): monitors AWVALID (valid write address request) and AWREADY (write address ready) signals. When AWVALID is 1 and AWREADY is 0, it indicates that back pressure occurs in the write address channel; when both AWVALID and AWREADY are 1, it indicates that the back pressure ends.

[0068] Write data channel (W): monitors WVALID (valid write data) and WREADY (write data ready) signals. Although the back pressure of the write data channel is less directly discussed, it may also occur in some cases (such as data width mismatch or insufficient processing capability of the receiving end). The monitoring method is similar to the write address channel.

[0069] Write response channel (B): monitors BVALID (valid write response) and BREADY (write response ready) signals. Although the write response channel does not usually directly reflect the back pressure of the write data channel, it is an important sign of the completion of the write operation. In some designs, the efficiency of the write operation may be indirectly evaluated based on the delay of the write response.

[0070] The timing mechanism is as follows:

[0071] Use an internal counter or timer to record the number of clock cycles from when the valid signal is valid (timing start time) to when the ready signal is also valid (timing end time). This number is the back pressure duration.

[0072] The counter or timer starts when the valid signal changes from 0 to 1, stops when both the valid and ready signals are 1, and saves the counting result.

[0073] The status feedback mechanism is as follows:

[0074] Threshold judgment: Compare the statistical back pressure duration with the preset threshold. If the back pressure duration of a channel exceeds the threshold, it is considered that the channel has a performance bottleneck or potential problem.

[0075] Interrupt reporting: When it is detected that the back pressure duration exceeds the threshold, an interrupt signal is triggered, and the abnormal information (including the back pressure duration exceeding the threshold, the channel where the abnormality occurs, etc.) is reported to the system monitoring software or debugging tool.

[0076] Status indication: In addition to interrupt reporting, real-time or historical status information of back pressure duration can be provided to the outside through status registers or LED indicators, so that developers or system administrators can monitor and debug.

[0077] There are three types of AXI bus channel back pressure duration:

[0078] 1. The back pressure duration is 0: when valid is valid, the corresponding channel ready signal is also valid;

[0079] 2. Back pressure duration is greater than 0: When valid is valid, the corresponding channel ready signal is invalid at the same clock cycle, and the back pressure duration is greater than or equal to one clock cycle;

[0080] 3. The back pressure duration is infinite: valid is valid, and the corresponding channel ready signal is always invalid.

[0081] See also Figure 1 The present invention discloses an AXI bus channel back pressure duration monitoring circuit, comprising a register configuration module, a back pressure duration information statistics module, and a delay information comparison and status output module.

[0082] The register configuration module is used to receive information sent by the external read / write register, and then connect to the MUX for channel selection, connect to the back pressure duration information statistics module through the tracking status reset register and the tracking command quantity register, and send the interval information and Track Enable to the delay information comparison module;

[0083] The MUX sends the channel selection to the back pressure duration information statistics module, and the back pressure duration information statistics module sends the Track_counters signal to the delay information comparison module;

[0084] The delay information comparison and status output module feeds back the interval distribution information, the maximum and minimum duration information, and the interrupt information to the register configuration module.

[0085] The register configuration module is used to implement the write operation of the control register required in the design and the read operation of the status register. The module accepts commands from the external master device, and the interface between the module and the external master device is a standard APB bus interface or an interface defined by the user to meet the functional requirements.

[0086] The register information is shown in the following table:

[0087]

[0088]

[0089] Back pressure duration information statistics module

[0090] See also Figure 2 The back pressure duration information statistics module is used to realize the statistics of the back pressure duration information of the AXI bus read address channel, read data channel, write address channel, write data channel and write response channel commands.

[0091] The following describes the detailed implementation of the back pressure duration information statistics module.

[0092] a. The register write enable signal wr_en is equal to 1 every time valid and ready are both 1, and the register is written;

[0093] c. delay_reg signal, which stores the back pressure duration of each command in real time. This signal remains 0 when valid and ready are both 1, indicating that the back pressure duration of this command is 0. When valid is 1 and ready is 0, delay_reg increases by 1 at each rising edge of the clock, indicating that the back pressure duration of the corresponding command increases by 1.

[0094] The delay information comparison module is used to count the maximum and minimum back pressure duration information of all commands, and supports interrupt reporting when the back pressure duration exceeds the threshold range, and can count the back pressure duration distribution intervals of all commands.

[0095] Implement the following functions:

[0096] a. Maximum back pressure duration statistics: Every time wr_en is high, delay_reg is stored in delay_max, and the delay_reg value is compared with the delay_max value, and the larger value of the two is stored in the delay_max register.

[0097] b. Minimum back pressure duration statistics: Every time wr_en is high, delay_reg is stored in delay_min, and the delay_reg value is compared with the delay_min value, and the larger value of the two is stored in the delay_min register.

[0098] c. Interrupt reporting when the back pressure duration exceeds the threshold range: The delay information comparison module supports interrupt status feedback. If the back pressure duration of a command exceeds the threshold set in the "interrupt trigger threshold register", an interrupt is triggered; the interrupt information is stored in the "interrupt status register", and the external master device reads the "interrupt status register" through the register configuration module to know whether there is an interrupt.

[0099] d. Back pressure duration interval distribution statistics: Compare the back pressure duration information stored in delay_reg with the "back pressure duration statistics interval information register group". If the back pressure duration meets the corresponding interval, the value of the "back pressure duration distribution interval register" is increased by 1. The current solution defines 9 groups of "back pressure duration statistics interval information register groups", totaling 11 duration intervals, of which the first duration interval is 0 and the 11th duration interval is infinite. The number of commands in each interval is stored in the "back pressure duration distribution interval register group". The external master device reads the "back pressure duration distribution interval register group" through the register configuration module to obtain the delay distribution of all commands.

[0100] The accumulated value of the "Back Pressure Duration Distribution Interval Register Group" is equal to the value configured in the "Tracking Command Quantity Register". If the two values ​​are not equal, it is because the back pressure duration of a command exceeds the value configured in all the "Back Pressure Duration Statistics Interval Information Register Groups". The register configuration needs to be modified according to the actual situation; the statistical results are as follows Figure 3 As shown, the horizontal axis represents the number of commands, and the vertical axis represents the back pressure duration. Through the present invention, statistics on the back pressure durations of all commands are achieved.

[0101] The working principle of the AXI bus channel back pressure duration monitoring circuit of the present invention is as follows:

[0102] The first step is to configure the following registers through the register configuration module:

[0103] AXI interface selection register determines which AXI channel back pressure duration is counted;

[0104] Track the command quantity register to determine how many commands the collection module can collect back pressure duration information statistics for;

[0105] Back pressure duration interval comparison information register group 0 to 9, set the interval information of the back pressure duration. Theoretically, it can be set from 0 delay to infinite delay. It is recommended to reserve ten groups of registers according to the actual application definition, and each register defines a back pressure duration interval;

[0106] The interrupt trigger threshold register sets the threshold for reporting the interrupt based on the back pressure duration. When the statistics of all command back pressure durations are completed, if the back pressure duration of a command exceeds this threshold, an interrupt is reported.

[0107] Step 2: The AXI interface sends commands and reads the following registers:

[0108] Back pressure duration distribution interval register group 0 to 8, read the number of commands in each back pressure duration interval;

[0109] Interrupt status register: when all command back pressure duration statistics are completed, if the back pressure duration of a command exceeds the value defined in the interrupt trigger threshold register, this register is set to 1.

[0110] Minimum back pressure duration register. By reading this register, the minimum back pressure duration information of all commands can be obtained;

[0111] Maximum back pressure duration register. By reading this register, you can obtain the minimum back pressure duration information in all commands.

[0112] Register Configuration Module

[0113] Function: This module is responsible for configuring the control registers required by the monitoring circuit and reading the status registers. The monitoring parameters (such as reverse voltage duration threshold, monitoring channel selection, etc.) are set to the control registers through write operations, and the working status and statistical information of the monitoring circuit are obtained from the status registers through read operations.

[0114] Implementation method: Communicate with the registers inside the chip through the AXI bus interface to configure parameters and read status.

[0115] Back pressure duration information statistics module

[0116] Function: This module monitors the command backpressure duration of each channel (read address, read data, write address, write data, write response) of the AXI bus in real time. When a channel on the bus experiences backpressure (i.e. the downstream processing speed cannot keep up with the upstream sending speed), the module will record the time from the start to the end of the backpressure.

[0117] Implementation:

[0118] Whether the channel is in a back pressure state is determined by monitoring specific signals on the AXI bus (such as a READY signal, a VALID signal, etc.).

[0119] Use an internal counter or timer to record the duration of backpressure.

[0120] The counted back pressure duration information is stored in an internal register or cache for subsequent processing.

[0121] Delay information comparison module

[0122] Function: This module further processes and analyzes the data collected by the back pressure duration information statistics module. It counts the maximum back pressure duration, the minimum back pressure duration, and the back pressure duration interval distribution, and determines whether there is abnormal back pressure based on the preset threshold.

[0123] Implementation:

[0124] Get raw data from the back pressure duration information statistics module.

[0125] Use algorithms to sort, group, and count data, and calculate the maximum and minimum back pressure durations and the back pressure duration interval distribution.

[0126] The statistical results are compared with the preset threshold. If it is found that the back pressure duration exceeds the threshold range, an interrupt is triggered and the abnormal information is reported.

[0127] Exception handling and reporting

[0128] When the delay information comparison module detects that the back pressure duration exceeds the preset threshold, an interrupt signal will be triggered immediately. The interrupt signal can be captured and processed by the interrupt controller inside the chip, and then trigger the corresponding exception handling process (such as adjusting task priority, increasing cache resources, etc.).

[0129] At the same time, abnormal information (including the back pressure duration exceeding the threshold, the channel where the abnormality occurred, etc.) will also be reported to the system monitoring software or debugging tools, so that developers can locate the problem in time and take corresponding solutions.

[0130] The invention also provides a chip.

[0131] Figure 4It is a structural block diagram of a chip according to an embodiment of the present invention.

[0132] like Figure 4 As shown, the chip 1000 includes the AXI bus channel back-voltage duration monitoring circuit 10 of the above embodiment.

[0133] The chip of the embodiment of the present invention realizes comprehensive monitoring and analysis of the back pressure duration of each channel of the AXI bus through the AXI bus channel back pressure duration monitoring circuit of the above embodiment; it can count the back pressure duration information, analyze the data and report abnormal interrupts in real time, providing a powerful tool for chip designers to optimize system performance and improve stability and reliability.

[0134] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0135] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0136] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0137] like Figure 3 As shown, the present invention can realize the statistics of the back pressure duration of the AXI bus interface command, and a histogram can be made based on the statistical results, so that the different back pressure duration information of all commands can be intuitively seen.

[0138] In summary, the present invention provides an AXI bus channel back pressure duration monitoring circuit, method and chip, which monitor, count and provide status feedback on the back pressure duration of the AXI bus read address channel, read data channel, write address channel, write data channel and write response channel, aiming to comprehensively and accurately monitor the back pressure duration in the key channels of the AXI bus (including the read address channel, read data channel, write address channel, write data channel and write response channel), so as to achieve efficient data transmission status monitoring and performance optimization.

[0139] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0140] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0141] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0142] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0143] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0144] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0145] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0146] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0147] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0148] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0149] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. An AXI bus channel back pressure duration monitoring circuit, characterized in that: It includes register configuration module, back pressure duration information statistics module and delay information comparison module; among them, Register configuration module, used for writing operations to required control registers and reading operations to status registers; The back pressure duration information statistics module is used to realize the statistics of the back pressure duration information of the AXI bus read address channel, read data channel, write address channel, write data channel and write response channel commands; The delay information comparison module is used to count the maximum back pressure duration, the minimum back pressure duration, and the back pressure duration interval distribution, and report the interruption when the back pressure duration exceeds the threshold range.

2. The AXI bus channel back pressure duration monitoring circuit according to claim 1, characterized in that: The register configuration module is used to receive commands from an external master device, and the interface between the register configuration module and the external master device is a standard APB bus interface or an interface defined by the user to meet functional requirements.

3. The AXI bus channel back pressure duration monitoring circuit according to claim 1, characterized in that: Implementation process of the back pressure duration information statistics module: The delay_reg signal stores the back pressure duration of each command in real time. When both valid and ready are 1, it remains 0, indicating that the back pressure duration of the command is 0.

4. The AXI bus channel back pressure duration monitoring circuit according to claim 3, characterized in that: When valid is 1 and ready is 0, delay_reg is incremented by 1 at each rising edge of the clock, indicating that the backpressure duration of the corresponding command is incremented by 1.

5. The AXI bus channel back pressure duration monitoring circuit according to claim 1, characterized in that: The maximum back pressure duration statistics are as follows: Each time wr_en is high, delay_reg is stored in delay_max, and the delay_reg value is compared with the delay_max value, and the larger value of the two is stored in the delay_max register; The minimum back pressure duration statistics are as follows: Each time wr_en is high, delay_reg is stored in delay_min, and the delay_reg value is compared with the delay_min value, and the larger value of the two is stored in the delay_min register; The specific statistics of the back pressure duration interval distribution are as follows: The back pressure duration information stored in delay_reg is compared with the "back pressure duration statistical interval information register group". If the back pressure duration meets the corresponding interval, the value of the back pressure duration distribution interval register is increased by 1. The external master device reads the back pressure duration distribution interval register group through the register configuration module to obtain the delay distribution of all commands.

6. The AXI bus channel back pressure duration monitoring circuit according to claim 5, characterized in that: The specific interruption when the back pressure duration exceeds the threshold range is: The delay information comparison module supports interrupt status feedback. If the back pressure duration of a command exceeds the threshold set by the interrupt trigger threshold register, an interrupt is triggered; the interrupt information is stored in the interrupt status register, and the external master device reads the interrupt status register through the register configuration module to know whether an interrupt occurs.

7. The AXI bus channel back pressure duration monitoring circuit according to claim 1, characterized in that: The accumulated value of the back pressure duration distribution interval register group is equal to the value configured in the tracking command quantity register. When the two values ​​are not equal, modify the register configuration.

8. The AXI bus channel back pressure duration monitoring circuit according to claim 1, characterized in that: It also includes a status output function, which reports an interrupt when the back pressure duration exceeds the threshold range.

9. A method for monitoring the back pressure duration of an AXI bus channel, characterized in that: The AXI bus channel back pressure duration monitoring circuit according to any one of claims 1 to 8 comprises the following steps: Count the back pressure duration of the AXI channel and the number of commands for collecting the back pressure duration information of the module; set the interval information of the back pressure duration, reserve ten groups of registers, each register defines a back pressure duration interval; set the threshold for reporting the back pressure duration interrupt; when the statistics of all command back pressure durations are completed, when the back pressure duration of a command exceeds the set back pressure duration reporting interrupt threshold, report an interrupt; Read the number of commands in each back pressure duration interval; when all command back pressure duration statistics are completed, if the back pressure duration of a command exceeds the value defined in the interrupt trigger threshold register, the corresponding register is set to 1; Get the minimum back pressure duration information of all commands by reading the minimum back pressure duration register; By reading the maximum back pressure duration register, you can obtain the minimum back pressure duration information in all commands.

10. A chip, characterized in that: include: An AXI bus channel back-voltage duration monitoring circuit according to any one of claims 1 to 8.

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