Data processing method, related equipment and storage medium
Through the simulation controller of the hardware simulation device, the test data is preloaded to the server memory, which solves the problem of long loading time for large amounts of data in the prior art and improves the efficiency of software testing.
Patent Information
- Application Number
- CN202411256583.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2024-12-27
AI Technical Summary
In the prior art, when testing software programs, a large amount of test data is loaded into the memory model through a hardware emulator, resulting in too long time consumption and seriously affecting the testing efficiency.
Through the simulation controller of the hardware simulation device, the test data is preloaded into the server memory. When the memory model does not store the test data, the test data is directly obtained from the server memory to avoid loading the data in the memory model.
It significantly saves the time required to load test data, improves the efficiency of software testing, and effectively utilizes test time.
Smart Images
Figure CN119201705A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a data processing method, related equipment and storage medium. Background Art
[0002] In the prior art, when testing software programs that need to interact with memory for data, the test data required for the test is often stored in a memory model. For example, for a program executed by a processor core, its test process needs to frequently access the SRAM (Static Random-Access Memory) model to complete the reading and writing operations of the test data.
[0003] The inventors have discovered that, in the prior art, when testing software programs, test data is loaded into a memory model through the built-in function of the hardware emulator. This method can meet the requirements for test data with a smaller amount of data. However, for test data with a huge amount of data, especially when batch testing of software programs is required and the amount of test data required for each software program is relatively large, loading the test data into the memory model will consume a lot of time, which will seriously affect the testing efficiency of the software program. Summary of the invention
[0004] In view of this, the present application is dedicated to providing a data processing method, related equipment and storage medium to solve the problem in the prior art that it takes too long to load test data into a memory model, which seriously affects the efficiency of software program testing.
[0005] In a first aspect, the present application provides a data processing method, which is applied to a hardware simulation device, wherein the hardware simulation device includes a memory model and a simulation controller, wherein the simulation controller is communicatively connected to a server, and the method includes the following steps performed by the simulation controller:
[0006] Obtaining a read access instruction of an upper controller, the upper controller being used to run a test program, the read access instruction indicating a target memory space of the memory model;
[0007] Determining whether test data is stored in the target memory space;
[0008] If the test data is not stored in the target memory space, obtaining the test data preloaded in the memory of the server;
[0009] If the test data is stored in the target memory space, the test data in the target memory space is acquired.
[0010] In an optional implementation, after obtaining the test data preloaded in the memory of the server, the method further includes:
[0011] Feedback the test data to the upper controller;
[0012] The test data is stored in the target memory space.
[0013] In an optional implementation, after storing the test data in the target memory space, the method further includes:
[0014] The target memory space is marked as storing test data.
[0015] In an optional embodiment, the method further includes:
[0016] Obtaining a write access instruction of the upper controller, wherein the write access instruction indicates a target memory space of the memory model and carries data to be written;
[0017] The data to be written is stored in the target memory space.
[0018] In an optional implementation, before obtaining the read access instruction of the upper controller, the method further includes:
[0019] In response to a reset instruction, configuring a memory space corresponding to the memory model in a memory of the server;
[0020] The test data of the test program is loaded into the memory space.
[0021] In an optional embodiment, the method further includes:
[0022] Marking each memory space in the memory model as not storing test data;
[0023] A notification signal is sent, where the notification signal is used to indicate that the upper controller can send the read access instruction.
[0024] In an optional implementation, the hardware emulation device further includes a status register;
[0025] The sending of the notification signal comprises:
[0026] A value indicating that the upper controller can send the read access instruction is written into the status register to trigger the notification signal.
[0027] In an optional implementation, the hardware emulation device further includes a flag register group, the flag register group includes a plurality of flag registers, and the flag registers correspond to the memory space one by one;
[0028] Determining whether the target memory space stores test data includes:
[0029] Obtaining a current value stored in a target flag register corresponding to the target memory space;
[0030] If the current value includes a value indicating that the target memory space stores test data, determining that test data is stored in the target memory space;
[0031] If the current value includes a value indicating that the target memory space does not store the test data, it is determined that the target memory space does not store the test data.
[0032] In an optional implementation, obtaining the test data preloaded in the memory of the server includes:
[0033] Call the preset server access interface;
[0034] The test data preloaded in the memory of the server is obtained through the preset server access interface.
[0035] In a second aspect, the present application further provides a hardware simulation device, including: a memory model and a simulation controller, wherein:
[0036] The simulation controller is respectively connected to the memory model and the server for communication, and the server is used for loading test data;
[0037] The simulation controller is used to execute the data processing method as described in any one of the first aspects of the present application.
[0038] In a third aspect, the present application provides a software testing system, comprising: a server and a hardware simulation device as provided in the second aspect of the present application, wherein a simulation controller of the hardware simulation device is communicatively connected to the server.
[0039] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the data processing method as described in any one of the first aspects of the present application are implemented.
[0040] Based on the above content, the data processing method provided by the present application is applied to a hardware simulation device including a memory model and a simulation controller. The simulation controller is communicatively connected to a server, and the memory of the server is preloaded with test data. The simulation controller responds to a read access instruction of an upper-level controller to determine whether test data is stored in a target memory space of the memory model indicated by the read access instruction. If not, the test data preloaded in the memory of the server is obtained. If so, the test data in the target memory space is obtained. The present method preloads the test data into the server memory space. Compared with the prior art of loading test data in a memory model and directly accessing the memory space to obtain test data, the present method provides test data by the server when the memory model does not store test data, thereby saving the time required to load test data and greatly improving software testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0042] Figure 1 It is a structural block diagram of a hardware simulation device provided by an embodiment of the present invention.
[0043] Figure 2 It is a flow chart of a data processing method provided by an embodiment of the present invention.
[0044] Figure 3 It is a structural block diagram of another hardware simulation device provided by an embodiment of the present invention.
[0045] Figure 4 It is a flowchart of another data processing method provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0047] As mentioned above, when testing software programs that need to interact with memory for data, the prior art often stores the test data required for the test in a memory model. During the testing of the software program, the software program accesses the memory model according to the execution requirements to obtain the test data, verifies whether the memory can be normally accessed for data reading and writing operations, and then verifies whether the software program can be normally executed. For example, for a processor core, there are many programs executed by it, some of which not only need to frequently access SRAM during actual application, but also the execution of the program depends on the test data pre-loaded in the SRAM during the initialization process. If the pre-loading of the test data fails or is wrong, it will affect the normal operation of the program. Therefore, for the testing of such software programs, it is necessary to pre-configure the SRAM model on the test equipment and initialize the test data stored in the SRAM model to meet the test requirements of frequent access to the SRAM model during the test process to complete the test data reading and writing operations.
[0048] The inventors have found that in the prior art, when testing software programs, most of the test data is loaded into the memory model through the built-in function of the hardware emulator. This method can meet the requirements for test data with a small amount of data. However, for test data with a huge amount of data, especially when batch testing of software programs is required and the amount of test data required for each software program is relatively large, loading the test data into the memory model will consume a lot of time, which not only wastes the hardware resources of the software testing equipment, but also seriously affects the testing efficiency of the software program.
[0049] In order to solve the above technical problems, the present application provides a hardware simulation device, combined with Figure 1 As shown, the hardware simulation device 10 provided by the present application includes a memory model 110 , a simulation controller 120 and an upper-layer controller 130 , wherein the simulation controller 120 is also communicatively connected with the server 20 .
[0050] Specifically, the hardware simulation device 10 is loaded with a memory model 110. In the present application, the memory model 110 can be used to store test data required for testing software programs. It should be noted that in the hardware simulation device provided in the present application and the data processing method applied to the hardware simulation device, the memory model 110 can be used to store test data, but the test data is not necessarily stored therein. If the test data is not stored in the memory model, it is necessary to cooperate with the server 20 to provide the test data for the upper-level controller 130. This process will be specifically expanded in the subsequent content and will not be described in detail here.
[0051] In actual applications, the memory model 110 may vary based on different test requirements and software program types. In an optional implementation, the memory model 110 may be an SRAM model. In another optional implementation, the memory model 110 may be an HDD (Hard Disk Drive) model. Of course, other types of memory models are also possible, which are not listed here one by one.
[0052] The simulation controller 120 is connected to the server 20 in communication, and on this basis, is also connected to the upper controller 130 and the memory model 110. The specific functions of the simulation controller 120 will be detailed in the subsequent content and will not be described in detail here.
[0053] The upper controller 130 can be used to load and run the test program, and based on the function of the test program, initiate a read / write access instruction of the test data to the simulation controller 120 to write the test data into the memory model 110, or read the test data in the memory model 110. In an optional embodiment, the upper controller 130 may include a processor core. It can be understood that in this case, the memory model 110 is usually an SRAM model. Further, in order to realize the communication between the processor core and the simulation controller 120, an AXI (Advanced eXtensible Interface) controller can also be integrated in the upper controller 130, and the AXI controller is used as the communication medium between the processor core and the simulation controller 120. As for the specific implementation method of the communication between the upper controller 130 and the simulation controller 120, it can be realized by referring to the relevant technology, and this application does not make specific limitations on this.
[0054] The server 20 is used to preload the test data required by the test software before the test starts, and provide the test data to the upper-level controller 130 when the corresponding test data is not stored in the memory model 110. It can be understood that compared with the prior art of loading a large amount of test data in the memory model 110, the present application preloads the test data through the server 20, which can save the time required for the memory model 110 to load the test data. Moreover, loading the test data in the memory is much more efficient than loading the test data in the memory model. As for the specific implementation process of the server 20 storing the test data, and the specific implementation method of the simulation controller 120 communicating with the server 20, they are all expanded in detail in the subsequent content and will not be described in detail here.
[0055] Furthermore, the present application provides a data processing method, which is applied to the hardware simulation device provided by the present application, and specifically to the simulation controller in the hardware simulation device. The method preloads the test data into the server memory space. Compared with the prior art of loading the test data in the memory model and directly accessing the memory space to obtain the test data, the method provides the test data by the server when the memory model does not store the test data, thereby saving the time required to load the test data and greatly improving the software testing efficiency.
[0056] Based on the above, see Figure 2 As shown, the data processing method provided by the present application includes the following steps.
[0057] S100, obtaining a read access instruction from an upper-layer controller.
[0058] As mentioned above, the upper controller runs the test program, and based on the running requirements or functions of the test program, initiates a read access instruction to the simulation controller to obtain the test data required for the test. Furthermore, in actual applications, since there is a lot of test data, it may be stored in different memory spaces. Therefore, the read and write access instructions sent by the upper controller can also indicate the target memory space of the memory model to obtain the test data stored in the target memory space.
[0059] After obtaining the read access instruction, the simulation controller parses the read access instruction and determines the target memory space that the upper-level controller wants to access based on the parsing result. In a possible implementation, the read access instruction carries the spatial address of the target memory space. The simulation controller parses the obtained read access instruction to extract the spatial address of the target memory space therein, and then determines the target memory space that the upper-level controller wants to access.
[0060] In actual applications, the test data can be the running data required for the test program to run, or it can be the execution result of the context part of the test program. Of course, it can also be other data that may be used in the program testing process. They are not listed here one by one. The specific details are subject to the actual test requirements. This application does not limit the specific composition of the test data.
[0061] S110, determine whether the target memory space stores test data, if not, execute S120, if yes, execute S130.
[0062] As mentioned above, the test data may not be stored in the memory model. Therefore, after the simulation controller determines the target memory space, it first determines whether the test data is stored in the target memory space. If no test data is stored therein, S120 is executed to obtain the test data preloaded in the server memory. On the contrary, if test data is stored in the target memory space, S130 is executed to obtain the test data in the target memory space.
[0063] In a possible implementation, the hardware simulation device further includes a flag register group, the flag register group includes a plurality of flag registers, and the flag registers correspond one-to-one to the memory space of the memory model, and each flag register is used to indicate whether test data is stored in the corresponding memory space. Based on this, the simulation controller obtains the current value stored in the target flag register corresponding to the target memory space, and if the current value is a value indicating that the target memory space stores test data, such as 1, it is determined that test data is stored in the target memory space; on the contrary, if the current value obtained is a value indicating that the target memory space does not store test data, such as 0, it is determined that the target memory space does not store test data.
[0064] Taking an SRAM with a capacity of 8GB as an example, any memory space thereof can store 128 bits of data. Therefore, a total of 1024×1024×512 flag registers are required to indicate whether test data is stored in the corresponding memory space. When the current value of any flag register is 1, it indicates that test data is stored in the corresponding memory space. On the contrary, if the current value of the flag register is 0, it indicates that test data is not stored in the corresponding memory space.
[0065] As for the setting and resetting process of each flag register, it will be expanded in subsequent content and will not be described in detail here.
[0066] S120: Acquire test data preloaded in the memory of the server.
[0067] When it is determined based on the above steps that the target memory space does not store test data, it means that the target memory space has not been accessed. As mentioned above, the server's memory is preloaded with test data. Therefore, in this case, the simulation controller obtains the test data preloaded in the server's memory.
[0068] It should be noted that the memory area in the server used to store test data is pre-configured before the test begins, and is specifically used to store test data. In addition, the memory area is further divided into memory spaces corresponding to the aforementioned memory spaces. Based on this, in the actual test data acquisition process, the simulation controller needs to access the memory space corresponding to the target memory space in the server memory area to obtain the correct test data. As for the specific implementation of configuring the memory area in the server memory and loading the test data therein, it will be expanded in the subsequent content and will not be described in detail here.
[0069] In an optional embodiment, a correspondence between a storage space address and a memory space address can be established. After the simulation controller obtains the space address of the target memory space through the aforementioned steps, the simulation controller can determine the target memory space address corresponding to the target memory space address based on the correspondence, thereby accessing the corresponding target memory space and obtaining the test data stored therein.
[0070] In actual applications, the communication between the simulation controller and the server can be achieved through a preset access interface. Based on this, the simulation controller can call the preset server access interface to obtain the test data preloaded in the server's memory through the preset server access interface.
[0071] In an optional implementation, the simulation controller and memory model in the hardware simulation device are implemented based on SV (SystemVerilog, a hardware description language used to describe digital circuits and system-level design) and programmable logic devices, and obtaining the test data in the server memory space can be implemented through a calling function edited by a software programming language, such as a test data calling function edited by C language. In this case, in order to realize the simulation controller calling the test data calling function on the server side, the aforementioned preset server interface can be implemented based on a DPI (Direct Programming Interface) interface, and the simulation controller obtains the test data in the server's memory space by calling the DPI interface used to obtain test data.
[0072] As a preferred embodiment, after obtaining the test data in the server memory space, the simulation controller feeds back the obtained test data to the upper controller so that the upper controller continues to execute the test program based on the obtained test data. More importantly, the simulation controller will further store the test data in the target memory space indicated by the read access instruction, and at the same time, mark the target memory space as storing test data. Following the previous example, the simulation controller writes 1 to the flag register corresponding to the target memory space, indicating that test data is stored in the target memory space. Such a setting can ensure that the upper controller directly accesses the target memory space when obtaining the test data in the target memory space next time, instead of obtaining the test data stored in the server memory space by calling the preset server access interface. It can be understood that the data processing method provided by the present application gradually loads the test data into the memory model as the test process advances, rather than centrally loading into the memory model, so there is no need to spend time loading the test data separately, because the test data can be provided in time through the server, it will not affect the test efficiency, and the test time can be effectively utilized to improve the test efficiency.
[0073] S130: Acquire test data in the target memory space.
[0074] When it is determined based on the above steps that the target memory space stores test data, it means that the target memory space has been accessed. In this case, the simulation controller directly accesses the target memory space in the memory model and obtains the test data therein.
[0075] Furthermore, the simulation controller feeds back the obtained test data to the upper-level controller, so that the upper-level controller continues to execute the test program based on the obtained test data.
[0076] It should be noted that, when the test data is not stored in the memory model, it takes some extra time to obtain the test data in the server memory. However, through the method provided by the aforementioned embodiment, in each process of obtaining test data, a judgment will be made as to whether the test data is stored in the memory model. The server will only be accessed when the required test data is not stored in the memory model. Such a setting can minimize the number of server accesses and reduce the extra time consumed by accessing the server. In addition, the method preloads the test data into the server memory space. Compared with the prior art of loading the test data in the memory model and directly accessing the memory space to obtain the test data, the method provides the test data by the server when the test data is not stored in the memory model. In comparison, it can still save the time required to load the test data, thereby greatly improving the software testing efficiency.
[0077] In actual applications, the test program run by the upper-level controller may also write data to the memory space. Based on this, in a possible implementation, the simulation controller obtains the write access instruction of the upper-level controller. Similar to the aforementioned read access instruction, the write access instruction can indicate the target memory space of the memory model and carry the data to be written. As for the way in which the write access instruction indicates the target memory space, it can be to carry the space address corresponding to the target memory space. Furthermore, since the data is written to the memory model, whether other data is stored in the target memory space does not affect the writing process. Therefore, the data to be written can be directly stored in the target memory space. Of course, before writing the data, it is also possible to refer to the aforementioned content to determine whether the test data is stored in the target memory space, so as to accurately know the actual state of the target memory space. The specific judgment process can refer to the aforementioned content and will not be repeated here.
[0078] After the data to be written is stored in the target memory space, the target memory space is marked as storing test data. Following the previous example, the simulation controller writes 1 to the flag register corresponding to the target memory space to indicate that test data is stored in the target memory space. This setting ensures that the upper-level controller directly accesses the target memory space when acquiring test data in the target memory space next time, rather than acquiring test data stored in the server memory space by calling the preset server access interface.
[0079] In actual applications, the testing of software programs may be carried out in batches. After completing the testing of one software program, another software program will be tested immediately. The test data required by different software programs is likely to be different. Therefore, after completing the testing of one software program, it is necessary to reset the hardware simulation device, clear the memory model and the test data stored in the server memory, and prepare the test data required for the next software program. In addition, before the test data is ready, the upper-level controller cannot initiate an access request to the memory model.
[0080] To meet the above application requirements, this application also provides another hardware simulation device, see Figure 3 As shown, based on the hardware emulation device provided in the previous embodiment, the hardware emulation device provided in this embodiment further includes: a status register 140 and a flag register group 150. The role of the flag register group 150 has been mentioned in the previous content, and the role of the status register 140 will be detailed in the subsequent content, which will not be described in detail here.
[0081] Furthermore, the present application also provides another data processing method, which is applied to Figure 3 The hardware simulation device provided in the embodiment shown is specifically applied to a simulation controller in the hardware simulation device. Figure 4 As shown, the data processing method provided in this embodiment includes the following steps.
[0082] S200. In response to a reset instruction, a memory area corresponding to the memory model is configured in the memory of the server.
[0083] As mentioned above, after completing the test of a software program, it is necessary to reset the hardware simulation device provided in this embodiment. In a possible implementation, the hardware simulation device is provided with a reset switch ( Figure 3 The user can issue a reset instruction by operating the reset switch. Of course, in practical applications, the reset instruction can also be issued to the hardware simulation device in other ways, which will not be described in detail here, and the specific way of providing the reset instruction is not limited in this application.
[0084] The simulation controller responds to the reset instruction, that is, configures a memory area corresponding to the memory model in the memory of the server. Referring to the foregoing content, the simulation controller obtains the test data in the server memory through the preset server access interface. Based on this, the present application provides a preset memory configuration interface, and the simulation controller configures the memory area corresponding to the memory model in the server memory by calling the preset memory configuration interface. Specifically, the configuration of the memory area corresponding to the memory model in the server memory can be implemented by a calling function edited by a software programming language, such as a memory configuration function edited by C language. Furthermore, the preset memory configuration interface is implemented based on the DPI interface technology. The simulation controller calls the memory configuration function on the server side by calling the preset memory configuration interface to configure the aforementioned memory area in the server's memory.
[0085] It is understandable that in order to avoid excessive occupation of server memory and to establish a one-to-one correspondence between memory space and storage space, the capacity of the memory area is preferably consistent with the capacity of the memory model. Of course, the memory area can also be greater than or equal to the capacity of the memory model. In this case, it is only necessary to ensure a one-to-one correspondence between the memory space required to be accessed during the test and the memory space.
[0086] S210: Load test data of the test program into the memory area.
[0087] After the memory area of the server is configured, it is necessary to further load the test data of the test program into the memory area. The process of the simulation controller controlling the server to load the test data can be implemented by referring to the aforementioned process of configuring the memory area in the server and obtaining the test data in the memory space, that is, by setting the server access interface and presetting the functions required to load the test data in the server for the interface to call, etc., which will not be described in detail here.
[0088] S220: Mark each memory space in the memory model as not storing test data.
[0089] As mentioned above, before testing the next software program, the test data stored in the memory model needs to be cleared, and each memory space in the memory model needs to be marked as not storing test data.
[0090] Using the previous example, the memory model is an SRAM model with a storage space of 8GB. Any memory space can store 128 bits of data. Therefore, a total of 1024×1024×512 flag registers are required to indicate whether the corresponding memory space stores test data. When the current value of any flag register is 1, it indicates that the corresponding memory space stores test data. On the contrary, if the current value of the flag register is 0, it indicates that the corresponding memory space does not store test data. Based on this, the simulation controller responds to the reset signal, that is, Figure 3 As shown, all flag registers in the flag register group 150 are written with 0 to indicate that no test data is stored in the memory model.
[0091] In actual applications, the number of flag registers that can be reset simultaneously by the simulation controller in any cycle is limited. For example, 1024×32 flag registers can be reset simultaneously, which means that multiple cycles are required to complete the reset of all flag registers. In this embodiment, 1024×16 cycles are required to complete the reset of all flag registers. In a possible implementation, a counter ( Figure 3 Before starting the reset of the flag register, the counter is cleared to zero. After that, each time a cycle of the flag register reset operation is completed, the counter is incremented by one until the count value reaches 1024×16, completing the reset operation of all flag registers, that is, marking all memory spaces in the memory model as not storing test data.
[0092] S230: Send a notification signal.
[0093] Before the memory model reset operation is completed, the upper controller is not allowed to initiate an access request to the memory model. In this application, a notification signal is sent to the upper controller to inform the upper controller that the memory model reset is completed, that is, the notification signal described in this embodiment is used to indicate that the upper controller can send an access instruction.
[0094] Combination Figure 3As shown, the hardware simulation device provided by the present application is configured with a status register. As an optional implementation, the simulation controller writes 0 to the status register in response to a reset signal, and, before the memory model reset operation is completed, the status register is maintained to store a value of 0 to indicate that the memory model has not been reset and the upper-level controller is prohibited from initiating access instructions. Accordingly, after completing the memory model reset operation, the simulation controller writes a value indicating that the upper-level controller can send an access instruction, such as 1, to the status register, thereby triggering a notification signal, and the upper-level controller can initiate an access instruction for the memory model in response to the notification signal.
[0095] S240, obtaining a read access instruction from an upper-layer controller.
[0096] In an optional implementation, this step can refer to Figure 2 The implementation of the relevant contents of S100 in the illustrated embodiment will not be repeated here.
[0097] S250, determine whether the target memory space stores test data, if not, execute S260, if yes, execute S270.
[0098] In an optional implementation, this step can refer to Figure 2 The implementation of the relevant contents of S110 in the illustrated embodiment will not be repeated here.
[0099] S260. Acquire test data preloaded in the memory of the server.
[0100] In an optional implementation, this step can refer to Figure 2 The implementation of the relevant contents of S120 in the illustrated embodiment will not be repeated here.
[0101] S270: Acquire test data in the target memory space.
[0102] In an optional implementation, this step can refer to Figure 2 The implementation of the relevant contents of S130 in the illustrated embodiment will not be repeated here.
[0103] To sum up, based on the data processing method provided in the previous embodiment, the processing method provided in this embodiment can be applied to batch program testing. After each software program is tested, the hardware simulation device is reset, and at the same time, memory space is configured on the server side and test data is loaded, thereby meeting the batch testing requirements of the software program.
[0104] It should be noted that Figure 4 Steps S200 to S230 in the embodiment shown, i.e., the reset process of the hardware simulation device, can also be applied to Figure 2In the illustrated embodiment, the hardware simulation device is reset before software testing is performed.
[0105] It should also be noted that after executing S230, the upper-level controller can also initiate a write access instruction. The same as the relevant content in the aforementioned embodiment, the write access instruction can indicate the target memory space of the memory model and carry the data to be written. Furthermore, since the data is written to the memory model, whether other data is stored in the target memory space does not affect the writing process. Therefore, the data to be written can be directly stored in the target memory space. Of course, before writing the data, it is also possible to refer to the aforementioned content to determine whether the test data is stored in the target memory space, so as to accurately know the actual state of the target memory space. The specific judgment process can refer to the aforementioned content and will not be repeated here.
[0106] After the data to be written is stored in the target memory space, the target memory space is marked as storing test data. Following the previous example, the simulation controller writes 1 to the flag register corresponding to the target memory space to indicate that test data is stored in the target memory space. This setting ensures that the upper-level controller directly accesses the target memory space when acquiring test data in the target memory space next time, rather than acquiring test data stored in the server memory space by calling the preset server access interface.
[0107] Furthermore, the present application also provides a software testing system, including: a server and a hardware simulation device as provided in any of the aforementioned embodiments, wherein a simulation controller of the hardware simulation device is communicatively connected to the server.
[0108] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored, and when the one or more instructions are executed by one or more processors, the processors execute the data processing method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.
[0109] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are executed by a processor, the processor executes the steps of the data processing method according to various embodiments of the present application described in the above content of this specification.
[0110] The computer program product may be written in any combination of one or more programming languages to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages such as Java, C++, etc., and conventional procedural programming languages such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.
[0111] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.
[0112] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.
[0113] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.
[0114] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.
[0115] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.
[0116] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.
Claims
1. A data processing method, characterized in that: Applied to a hardware simulation device, the hardware simulation device includes a memory model and a simulation controller, the simulation controller is communicatively connected to a server, and the method includes the following steps performed by the simulation controller: Obtaining a read access instruction of an upper controller, the upper controller being used to run a test program, the read access instruction indicating a target memory space of the memory model; Determining whether test data is stored in the target memory space; If the test data is not stored in the target memory space, obtaining the test data preloaded in the memory of the server; If the test data is stored in the target memory space, the test data in the target memory space is acquired.
2. The method according to claim 1, characterized in that After obtaining the test data preloaded in the memory of the server, the method further includes: Feedback the test data to the upper controller; The test data is stored in the target memory space.
3. The method according to claim 2, characterized in that After storing the test data in the target memory space, the method further includes: The target memory space is marked as storing test data.
4. The method according to claim 1, characterized in that: The method further comprises: Obtaining a write access instruction of the upper controller, wherein the write access instruction indicates a target memory space of the memory model and carries data to be written; The data to be written is stored in the target memory space.
5. The method according to any one of claims 1 to 4, characterized in that: Before obtaining the read access instruction of the upper controller, the method further includes: In response to a reset instruction, configuring a memory area corresponding to the memory model in a memory of the server; The test data of the test program is loaded into the memory area.
6. The method according to claim 5, characterized in that The method further comprises: Marking each memory space in the memory model as not storing test data; A notification signal is sent, where the notification signal is used to indicate that the upper controller can send the read access instruction.
7. The method according to claim 6, characterized in that The hardware emulation device also includes a status register; The sending of the notification signal comprises: A value indicating that the upper controller can send the read access instruction is written into the status register to trigger the notification signal.
8. The method according to claim 1, characterized in that The hardware emulation device further includes a flag register group, the flag register group includes a plurality of flag registers, and the flag registers correspond to the memory space one by one; Determining whether the target memory space stores test data includes: Obtaining a current value stored in a target flag register corresponding to the target memory space; If the current value includes a value indicating that the target memory space stores test data, determining that test data is stored in the target memory space; If the current value includes a value indicating that the target memory space does not store the test data, it is determined that the target memory space does not store the test data.
9. The method according to claim 1, characterized in that: Obtaining test data preloaded in the memory of the server, including: Call the preset server access interface; The test data preloaded in the memory of the server is obtained through the preset server access interface.
10. A hardware simulation device, characterized in that: It includes: a memory model and a simulation controller, wherein: The simulation controller is respectively connected to the memory model and the server for communication, and the server is used for loading test data; The simulation controller is used to execute the data processing method according to any one of claims 1 to 9.
11. A software testing system, characterized in that: include: A server and the hardware simulation device as claimed in claim 10, wherein the simulation controller of the hardware simulation device is communicatively connected to the server.
12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the data processing method according to any one of claims 1 to 9 are implemented.