Low-power-consumption digital operation circuit and digital operation system

Abstract

The invention provides a low-power-consumption digital operation circuit and a digital operation system. The circuit comprises an operation function selection module used for determining an operation mode of current operation; the symbol judgment module is used for judging the positive and negative properties of the first input data and the second input data, carrying out symbol removal operation on the first input data and the second input data, outputting first operation data and second operation data which are unsigned, and adjusting the positive and negative properties of an operation result according to a judgment result to form an output result; and the operation module is used for operating the first operation data and the second operation data according to the operation mode and outputting an operation result. According to the invention, de-symbolization operation is carried out on the input data, corresponding operation processing is carried out on the unsigned operation data according to the current operation mode, and symbol adjustment is carried out on the operation result in combination with the positive and negative judgment result of the input data, so that the digital operation circuit does not need to carry out symbol operation during operation, and the power consumption requirement is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of digital computing technology, and in particular to a low-power digital computing circuit and a digital computing system. Background Art

[0002] With the advancement of intelligence, my country has successively put into trial a series of domestically produced intelligent wind turbine systems. In these intelligent systems, filters, fast Fourier transforms, discrete cosine transforms, etc. are required, so the system needs to be equipped with a large number of units with multiplication and division operations. However, the setting of a large number of multipliers and dividers leads to increased system power consumption and reduced performance. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a low-power digital operation circuit and a digital operation system to solve the problem of high power consumption of multipliers and dividers in the prior art.

[0004] The embodiment of the present disclosure adopts the following technical scheme: a low-power digital operation circuit, comprising: an operation function selection module, used to determine the operation mode of the current operation; a sign judgment module, used to judge the positive or negative nature of the first input data and the second input data, perform a sign removal operation on the first input data and the second input data, and output unsigned first operation data and second operation data, wherein the first input data, the second input data, the first operation data and the second operation data are all binary numbers; an operation module, used to operate the first operation data and the second operation data according to the operation mode, and output an operation result; the sign judgment module is also used to adjust the positive or negative nature of the operation result according to the judgment result to form an output result.

[0005] In some embodiments, the sign judgment module is specifically used to: detect the sign bit of the input data; when the value of the sign bit is 0, output the judgment result that the input data is a positive number; when the value of the sign bit is 1, output the judgment result that the input data is a negative number.

[0006] In some embodiments, the sign judgment module is specifically used to: when the first input data and the second input data are both positive numbers, assign a value of 0 to the sign bit of the calculation result; when any one of the first input data and the second input data is a negative number, assign a value of 1 to the sign bit of the calculation result; when the first input data and the second input data are both negative numbers, assign a value of 0 to the sign bit of the calculation result.

[0007] In some embodiments, the sign judgment module is specifically used to: extract data of all numerical bits of the first input data as unsigned first operation data; extract data of all numerical bits of the second input data as unsigned second operation data.

[0008] In some embodiments, the operation mode includes at least any one of the following: reciprocal operation, multiplication operation, and division operation.

[0009] In some embodiments, the operation module at least includes: a reciprocal operation unit and a multiplication operation unit; wherein the reciprocal operation unit is used to, when the operation mode is a reciprocal operation, perform a reciprocal solution operation on the first operation data to obtain the reciprocal of the first operation data as the operation result; when the operation mode is a division operation, perform a reciprocal solution operation on the operation data serving as the divisor to obtain a reciprocal solution result; the multiplication operation unit is used to, when the operation mode is a multiplication operation, calculate the first product of the first operation data and the second operation data, and use the first product as the operation result; when the operation mode is a division operation, calculate the second product of the operation data serving as the dividend and the reciprocal solution result, and use the second product as the operation result.

[0010] In some embodiments, the reciprocal operation unit performs the reciprocal solution operation through a vector mode of a coordinate rotation digital calculation algorithm.

[0011] In some embodiments, the multiplication operation unit includes at least a partial product generation unit and a partial accumulation and addition unit; wherein the partial product generation unit includes at least M groups of shifters and selectors, the shifter of the nth group is used to shift the first operation data left by n-1 bits, and perform an n-1-bit 0-fill operation after the left-shifted first operation data; the selector of the nth group is used to select one group of data from the 0 value and the left-shifted first operation data according to the n-1-th bit value of the second operation data as the partial product result of the nth bit, wherein the second operation data has a total of N bits, n=1,2,...,N, and N is less than or equal to M; the partial accumulation and addition unit includes at least an adder, which is used to perform a sum operation on all the partial product results to obtain the operation result.

[0012] In some embodiments, the value of M is an integer power of 2.

[0013] The embodiment of the present disclosure also provides a digital computing system, comprising at least one low-power digital computing circuit as described above.

[0014] The beneficial effects of the disclosed embodiment are: using the sign judgment module to de-sign the input data, outputting unsigned operation data, and performing corresponding operation processing on the unsigned operation data according to the operation mode of the current operation, combining the sign judgment module to judge the positive and negative of the input data, and adjusting the sign of the operation result, so that the digital operation circuit does not need to perform sign operation during operation, reducing the power consumption requirement of the operation. Further combined with the design of the reciprocal operation unit and the multiplication operation unit in the operation module, only the shifter, selector and adder are needed to realize the multiplication and division calculation, the circuit is simple to realize, and the power consumption is further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0016] Figure 1 It is a structural schematic diagram of a low-power digital operation circuit in the first embodiment of the present disclosure;

[0017] Figure 2 This is a schematic diagram of the structure of the computing module in the first embodiment of the present disclosure;

[0018] Figure 3 Schematic diagram of the structure of the multiplication unit in the first embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.

[0020] With the advancement of intelligence, my country has successively put into trial a series of domestically produced intelligent wind turbine systems. In these intelligent systems, filters, fast Fourier transforms, discrete cosine transforms, etc. are required, so the system needs to be equipped with a large number of units with multiplication and division operations. However, the setting of a large number of multipliers and dividers leads to increased system power consumption and reduced performance.

[0021] In order to solve the above problems, the first embodiment of the present disclosure provides a low-power digital operation circuit, and its structural schematic diagram is as follows: Figure 1 As shown, it mainly includes the following modules: a mutually coupled operation function selection module 10, a symbol judgment module 20 and an operation module 30. Figure 2 and Figure 3 The low power consumption digital operation circuit of this embodiment is described in detail.

[0022] Specifically, the operation function selection module 10 is mainly used to determine the operation mode of the current operation. In this embodiment, the operation mode mainly includes any one of the following: reciprocal operation, multiplication operation, and division operation. Other devices connected to the digital operation circuit of this embodiment select the operation mode to be performed according to actual operation requirements. The operation function selection module 10 can output different pulse signals or binary data according to different operation modes to indicate the specific operation mode of the operation module 30 for this operation.

[0023] The symbol judgment module 20 has at least two data input terminals, which are respectively used to input two input data that need to be calculated this time from other devices that are connected to the digital operation circuit of this embodiment. The input data has a sign, which may be a positive number or a negative number. After receiving the above two input data, the symbol judgment module 20 judges its positive and negative nature and outputs the judgment result. Specifically, the operations implemented in this embodiment are all binary number operations, which can be digital signals converted from analog signals, or binary data output by other devices. After receiving the above input data, the symbol judgment module 20 detects the value of its sign bit. When the value of the sign bit is 0, the judgment result that the input data is a positive number is output. If the value of the sign bit is 1, the judgment result that the input data is a negative number is output. Corresponding to the two input data, their positive and negative natures are judged respectively, and when the operation result is finally output in combination with the judgment result, the sign bit of the operation result is adjusted.

[0024] In some embodiments, the de-signification operation implemented by the sign judgment module 20 can specifically be to extract all the numerical bit data of the first input data as unsigned first operation data A for output, and to extract all the numerical bit data of the second input data as unsigned second operation data B for output; or, since the sign bit value of a positive number is 0 and the sign bit value of a negative number is 1, the sign judgment module 20 can also perform an inversion processing on a negative number with a sign bit value of 1, and after setting its sign bit value to 0, allow it to participate in subsequent operations as a positive number, so as to avoid the increase in the operation bit width caused by the participation of the sign bit in the operation, thereby reducing power consumption.

[0025] The operation module 30 is a module that mainly implements data operation and outputs the operation result. It specifically performs the operation of the first operation data A and the second operation data B output by the symbol judgment module 20 according to the current operation mode determined by the operation function selection module 10. Specifically, Figure 2 The schematic diagram of the structure of the operation module 30 in this embodiment is shown, which at least includes a reciprocal operation unit 31 and a multiplication operation unit 32, wherein the reciprocal operation unit 31 is mainly used to perform a reciprocal solution operation on the input operation data, so that the output result is the reciprocal of the input data. In the operation mode corresponding to the reciprocal operation, the reciprocal operation unit 31 can use the input first operation data A as the data to be processed, perform a reciprocal solution operation on it, and output the reciprocal of the first operation data A obtained as the operation result, at this time, the content of the second operation data B input can be directly ignored, regardless of whether it has a valid value; in the operation mode corresponding to the multiplication operation, the reciprocal operation unit 31 does not perform data processing; in the operation mode corresponding to the division operation, the reciprocal operation unit 31 performs a reciprocal solution operation on the operation data as the divisor to obtain a reciprocal solution result, and inputs the reciprocal solution result into the multiplication operation unit 32 to complete the implementation of subsequent operations.

[0026] In some embodiments, the inverse calculation unit 31 can complete the inverse solution and calculation through the vector mode in the coordinate rotation digital computer (CORDIC) algorithm. In a linear system, the angle of the i-th rotation is θ i =2 -i ,thereby So θ can be decomposed into a series of 2 -i When θ1 is set to 0 and y is set to 1, θ can be obtained in vector mode through multiple iterations. n =1 / x1, that is, the result of the inverse solution operation is the inverse of the input data x1, 1 / x1.

[0027] The multiplication unit 32 of this embodiment is mainly used to calculate the first product of the first operation data A and the second operation data B when the operation mode is multiplication operation, and use the first product as the operation result; when the operation mode is division operation, calculate the second product of the operation data as the dividend and the inverse solution result, and use the second product as the operation result.

[0028] Figure 3 FIG. 3 shows a schematic diagram of the structure of the multiplication operation unit 32 of this embodiment, which mainly includes a partial product generation unit 321 and a partial accumulation and addition unit 322. The partial product generation unit includes at least M groups of shifters ( Figure 3The specific shifter mark is not shown in the figure) and the selector, the shifter of the nth group is used to shift the first operation data A to the left by n-1 bits, and perform an n-1-bit 0-filling operation after the first operation data A after the left shift; the selector of the nth group is used to select one of the sets of data from the 0 value and the first operation data A after the left shift according to the n-1-bit value of the second operation data B as the partial product result of the n-1th bit; it should be noted that in this embodiment, the second operation data B is limited to a total of N bits, n = 1, 2, ..., N, and N is less than or equal to M, and M and N are both positive integers. Correspondingly, the partial accumulation and addition unit 322 includes at least an adder, which is mainly used to perform a sum operation on all partial product results to obtain the operation result. It should be noted that in this embodiment, the value of M is usually set to the zth power of 2, and z is a positive integer, so as to facilitate the subsequent partial accumulation and addition operation.

[0029] In actual implementation, the adders included in the partial accumulation and addition unit 322 are binary adders, and the number of the adders is set with reference to the value of M, which is usually M-1. Figure 3 As shown in the structural diagram, the adders are configured in layers, with the number of layers being z layers, with the layer closest to the selector being the first layer, and the first layer including at least M / 2 adders, each of which is used to perform the partial product result of the outputs of two adjacent and non-overlapping selectors in the partial product generating unit 321; the number of adders in the second layer is half of that in the previous layer, and is used to perform the summation of the outputs of two adjacent and non-overlapping adders in the first layer, and so on, until the z-th layer adder, which has only one adder, is used to perform the summation of the outputs of the two adders in the z-1th layer, and the summation result output by the adder in the z-th layer is output as the operation result of the multiplication operation unit 32. It should be noted that, in the process of performing the summation, the partial accumulation and addition unit 322 can directly perform the calculation of the sum value and the implementation of the saturation operation based on the addition operation rule of binary data, which is not specifically described in this embodiment.

[0030] based on Figure 3 The structural design of the multiplication unit shown in the figure enables the entire multiplication process to be realized with only a shifter, a selector and an adder, without the need for complex multiplication or division operations, effectively saving the power consumption of the operation unit. In addition, since the operation data are all unsigned data, the addition result of the multiplication unit only needs to be expanded by 1 bit at most to be output, without the need for additional judgment, further saving power consumption.

[0031] The following is a description of the process of multiplication operation performed by the multiplication operation unit 32 with reference to a specific example. For example, if the first operation data A of this operation is 1010 and the second operation data B is 0111, the first group of shifters does not perform a left shift operation on A, and the value of the 0th bit of B is 1, then the result output by the selector is the value of A, i.e., 1010; the second group of shifters shifts A left by 1 bit and fills it with 0, then the data input to the second group of selectors is 10100 and 0, the value of the 1st bit of B is 1, then the result output by the selector is 10100; similarly, the third group of shifters shifts A left by 2 bits and fills it with 0, the selector inputs 101000 and 0, the value of the 2nd bit of B is 1, then the selector outputs 101000; finally, the fourth group of shifters shifts A left by 3 bits and fills it with 0, the selector inputs 1010000 and 0, at this time the value of the 3rd bit of B is 0, then the partial product result output by the selector is 0. Then, the two adders in the first layer are used to sum the output data of the first group of selectors and the second group of selectors, and the output data of the third group of selectors and the fourth group of selectors, respectively, to obtain the sum values ​​11110 and 101000. Finally, the adder in the second and last layer is used to sum 11110 and 101000, and the result is 1000110. It is verified by decimal numbers. The decimal number of the first operation data A is 10, the decimal number of the second operation data B is 7, and the decimal number of 1000110 is 70, which is exactly the product of 10 and 7.

[0032] Finally, based on the operation result output by the operation module 30, the sign judgment module 20 adjusts the sign of the operation result according to the judgment result of the positivity of the input data to obtain the final output result. Specifically, when both the first input data and the second input data are positive numbers, the sign bit of the operation result is assigned a value of 0, that is, the output result is a positive number; when any one of the first input data and the second input data is a negative number, the sign bit of the operation result is assigned a value of 1, that is, the output result is a negative number; when both the first input data and the second input data are negative numbers, negative and negative equals positive, and the sign judgment module 20 also assigns a value of 0 to the sign bit of the operation result, so that the output result is a positive number.

[0033] This embodiment uses a sign judgment module to de-sign the input data, outputs unsigned operation data, and performs corresponding operation processing on the unsigned operation data according to the operation mode of the current operation. Combined with the sign judgment module's judgment result on the positivity of the input data, the operation result is sign-adjusted, so that the digital operation circuit does not need to perform sign operations during operation, thereby reducing the power consumption requirements of the operation. Further combined with the design of the reciprocal operation unit and the multiplication operation unit in the operation module, only shifters, selectors and adders are needed to realize multiplication and division calculations, the circuit is simple to implement, and power consumption is further reduced. The low-power digital operation circuit of this embodiment has a simple structure and can independently complete multiplication, division or reciprocal operations. When several identical circuits are combined, multiplication and division composite operations can be completed.

[0034] The second embodiment of the present disclosure provides a digital operation system, which can be used as a data processing operation system in a smart wind turbine or other smart scenes. The system includes at least one low-power digital operation circuit of the first embodiment of the present disclosure, so as to complete the multiplication and division operations of data with low power consumption. In actual implementation, multiple low-power digital operation circuits of the first embodiment of the present disclosure can be configured in the system to complete the compound operation of multiplication and division.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A low power consumption digital operation circuit, characterized in that: include: An operation function selection module is used to determine the operation mode of the current operation; a sign judgment module, used for judging the positive and negative of the first input data and the second input data, performing a sign removal operation on the first input data and the second input data, and outputting unsigned first operation data and second operation data, wherein the first input data, the second input data, the first operation data and the second operation data are all binary numbers; A calculation module, used for calculating the first calculation data and the second calculation data according to the calculation mode, and outputting a calculation result; The sign judgment module is further used to adjust the positive or negative sign of the operation result according to the judgment result to form an output result.

2. The low power consumption digital operation circuit according to claim 1, characterized in that: The symbol judgment module is specifically used for: Detect the sign bit of the input data; When the value of the sign bit is 0, outputting a judgment result that the input data is a positive number; When the value of the sign bit is 1, a judgment result indicating that the input data is a negative number is output.

3. The low power consumption digital operation circuit according to claim 2, characterized in that: The symbol judgment module is specifically used for: When both the first input data and the second input data are positive numbers, assigning a value of 0 to the sign bit of the operation result; When any one of the first input data and the second input data is a negative number, assigning a value of 1 to the sign bit of the operation result; When both the first input data and the second input data are negative numbers, a value of 0 is assigned to the sign bit of the operation result.

4. The low power consumption digital operation circuit according to claim 2, characterized in that: The symbol judgment module is specifically used for: Extracting data of all numerical bits of the first input data as the first unsigned operation data; Data of all numerical bits of the second input data are extracted as unsigned second operation data.

5. The low power consumption digital operation circuit according to any one of claims 1 to 4, characterized in that: The operation mode includes at least any one of the following: reciprocal operation, multiplication operation, and division operation.

6. The low power consumption digital operation circuit according to claim 5, characterized in that: The operation module at least includes: a reciprocal operation unit and a multiplication operation unit; wherein, The reciprocal operation unit is used to, when the operation mode is the reciprocal operation, perform a reciprocal solution operation on the first operation data to obtain the reciprocal of the first operation data as the operation result; when the operation mode is the division operation, perform a reciprocal solution operation on the operation data used as the divisor to obtain the reciprocal solution result; The multiplication operation unit is used to, when the operation mode is a multiplication operation, calculate the first product of the first operation data and the second operation data, and use the first product as the operation result; when the operation mode is a division operation, calculate the second product of the operation data as the dividend and the inverse solution result, and use the second product as the operation result.

7. The low power consumption digital operation circuit according to claim 6, characterized in that: The reciprocal calculation unit completes the reciprocal solution operation through the vector mode of the coordinate rotation digital calculation algorithm.

8. The low power consumption digital operation circuit according to claim 6, characterized in that: The multiplication operation unit at least includes a partial product generation unit and a partial accumulation and addition unit; wherein, The partial product generating unit comprises at least M groups of shifters and selectors, wherein the shifter of the nth group is used to shift the first operation data left by n-1 bits, and perform an n-1-bit 0-filling operation after the first operation data after the left shift; the selector of the nth group is used to select one group of data from the 0 value and the first operation data after the left shift according to the value of the n-1th bit of the second operation data as the partial product result of the nth bit, wherein the second operation data has a total of N bits, n=1, 2, ..., N, and N is less than or equal to M; The partial accumulation and addition unit at least includes an adder, which is used to perform a sum operation on all the partial product results to obtain the operation result.

9. The low power consumption digital operation circuit according to claim 8, characterized in that: The value of M is an integer power of 2.

10. A digital computing system, characterized in that: The method comprises at least one low power consumption digital operation circuit according to any one of claims 1 to 9.

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