Transistor parameter acquisition method and device, terminal equipment and medium
By constructing a curve of dissipated power and transconductance maximum value and substrate temperature and transconductance maximum value, the ratio of dissipated power and channel temperature of HEMT is calculated, which solves the problem of low accuracy in the prior art and improves the test results. reliability.
Patent Information
- Application Number
- CN202310763716.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-26
- Publication Date
- 2024-12-27
AI Technical Summary
The prior art has low accuracy in determining the ratio (Rth) between dissipated power and channel temperature in high electron mobility transistors (HEMTs), mainly due to the current collapse effect caused by the pulse IV test method, which leads to a decrease in drain-source current.
By obtaining multiple graphs of the transistor performing pulse IV tests at multiple different dissipative power and substrate temperatures, the first curve between dissipative power and transconductance maximum and the substrate temperature and transconductance maximum are constructed. The second curve calculates the ratio of the dissipated power of the transistor to the channel temperature to avoid the current collapse effect.
The accuracy of determining the ratio of dissipated power to channel temperature is improved, the influence of current collapse effect is avoided, and the reliability of test results is enhanced.
Smart Images
Figure CN119203459A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of data processing technology, and in particular, relates to a method, device, terminal equipment and medium for obtaining parameters of a transistor. Background Art
[0002] High electron mobility transistor (HEMT) is widely used in many microwave power electronic devices due to its high power density. At the same time, the self-heating effect caused by its high power density will also significantly affect many characteristics of HEMT, such as DC current voltage and continuous wave S parameters. As a key parameter to characterize the self-heating effect, the ratio of dissipated power to channel temperature (Rth) plays an important role in the thermal analysis and modeling of HEMT. Its accuracy directly affects the accuracy of the HEMT model. Therefore, how to determine Rth is one of the focuses in this field.
[0003] The prior art generally determines the ratio between the above dissipated power and the channel temperature by a pulse IV test method. However, the pulse IV test method will produce a current collapse (CC) effect, causing a significant decrease in the drain-source current, thereby reducing the accuracy of determining the above ratio. Summary of the invention
[0004] The embodiments of the present application provide a method, apparatus, terminal device and medium for obtaining parameters of a transistor, which improve the accuracy of determining the ratio between dissipated power and channel temperature.
[0005] In a first aspect, an embodiment of the present application provides a method for obtaining parameters of a transistor, comprising:
[0006] Obtaining a plurality of first pulse IV curves obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and obtaining a plurality of second pulse IV curves obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; the substrate temperature refers to the temperature of a structure used to carry the transistor for heating;
[0007] Determine, according to the plurality of first pulse IV curves, a first transconductance maximum value corresponding to each of the dissipated powers, and generate a first curve according to the first transconductance maximum value corresponding to each of the dissipated powers, wherein the first curve is used to represent the relationship between the dissipated power and the transconductance maximum value;
[0008] Determine the second transconductance maximum value corresponding to each substrate temperature according to the plurality of second pulse IV curves, and generate a second curve according to the second transconductance maximum value corresponding to each substrate temperature, wherein the second curve is used to represent the relationship between the substrate temperature and the transconductance maximum value;
[0009] The ratio of the power dissipation of the transistor to the channel temperature is calculated according to the first curve and the second curve.
[0010] Optionally, the step of obtaining a plurality of first pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and obtaining a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures, comprises:
[0011] When it is detected that the temperature of the structure reaches a first temperature, obtaining a temperature set of the structure within a set time period;
[0012] If the difference between each temperature value in the temperature set and the first temperature is less than or equal to a first threshold, a pulse IV test is performed on the transistor to obtain the plurality of first pulse IV curve graphs and the plurality of second pulse IV curve graphs.
[0013] Optionally, the obtaining of a plurality of first pulse IV curves obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers comprises:
[0014] When it is detected that the substrate temperature is a second temperature and the current drain-source static bias voltage of the transistor is a set voltage, adjusting the gate-source static bias voltage of the transistor;
[0015] Determining the current dissipated power of the transistor according to the adjusted gate-source static bias voltage;
[0016] Under the current dissipated power, a pulse IV test is performed on the transistor to obtain a first pulse IV curve graph under the current dissipated power.
[0017] Optionally, the obtaining of a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures includes:
[0018] Obtaining a turn-off voltage of the transistor;
[0019] Adjusting the gate-source static bias voltage of the transistor according to the turn-off voltage to obtain a target gate-source voltage; the target gate-source voltage is less than the turn-off voltage;
[0020] When it is detected that the current drain-source static bias voltage of the transistor is the set voltage, a pulse IV test is performed on the transistor at the multiple different substrate temperatures to obtain the multiple second pulse IV curve graphs.
[0021] Optionally, determining the first transconductance maximum value corresponding to each of the dissipated powers according to the plurality of first pulse IV curves includes:
[0022] Obtaining a first drain-source static bias voltage of the transistor for pulse IV testing under the plurality of different dissipation powers;
[0023] Determining a first drain-source voltage of the plurality of first pulse IV curves according to the first drain-source static bias voltage; the first drain-source voltage being greater than the first drain-source static bias voltage;
[0024] For each of the first pulse IV curve graphs, a first transconductance set of the first pulse IV curve graph at the first drain-source voltage is obtained, and a maximum value in the first transconductance set is determined as the first transconductance maximum value at the dissipation power corresponding to the first pulse IV curve graph; wherein the first transconductance set includes multiple transconductance values at the first drain-source voltage.
[0025] Optionally, determining the second transconductance maximum value corresponding to each substrate temperature according to the plurality of second pulse IV curves includes:
[0026] Obtaining a second drain-source static bias voltage of the transistor for pulse IV testing at the plurality of different substrate temperatures;
[0027] Determining a second drain-source voltage of the plurality of second pulse IV curves according to the second drain-source static bias voltage; the second drain-source voltage being greater than the second drain-source static bias voltage;
[0028] For each of the second pulse IV curve graphs, a second transconductance set of the second pulse IV curve graph at the second drain-source voltage is obtained, and a maximum value in the second transconductance set is determined as the second transconductance maximum value at the substrate temperature corresponding to the second pulse IV curve graph; wherein the second transconductance set includes multiple transconductance values at the second drain-source voltage.
[0029] Optionally, the calculating, according to the first curve and the second curve, to obtain a ratio of the power dissipation of the transistor to the channel temperature includes:
[0030] calculating a first slope of the first curve and a second slope of the second curve;
[0031] The ratio is obtained by calculation according to the first slope, the second slope, and the ambient temperature of the region where the transistor is located.
[0032] In a second aspect, an embodiment of the present application provides a transistor parameter acquisition device, comprising:
[0033] A first acquisition unit is used to acquire a plurality of first pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and to acquire a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; the substrate temperature refers to the temperature of a structure used to carry the transistor for heating;
[0034] A first generating unit, configured to determine a first transconductance maximum value corresponding to each of the dissipated powers according to the plurality of first pulse IV curve graphs, and to generate a first curve according to the first transconductance maximum value corresponding to each of the dissipated powers, wherein the first curve is used to represent a relationship between the dissipated power and the transconductance maximum value;
[0035] A second generating unit, configured to determine a second transconductance maximum value corresponding to each substrate temperature according to the plurality of second pulse IV curve graphs, and to generate a second curve according to the second transconductance maximum value corresponding to each substrate temperature, wherein the second curve is used to represent a relationship between the substrate temperature and the transconductance maximum value;
[0036] The first calculation unit is used to calculate the ratio of the dissipated power of the transistor to the channel temperature according to the first curve and the second curve.
[0037] In a third aspect, an embodiment of the present application provides a terminal device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for obtaining transistor parameters as described in any one of the first aspects above is implemented.
[0038] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for obtaining transistor parameters as described in any one of the above-mentioned first aspects is implemented.
[0039] In a fifth aspect, an embodiment of the present application provides a computer program product. When the computer program product is run on a terminal device, the terminal device can execute the transistor parameter acquisition method described in any one of the above-mentioned first aspects.
[0040] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:
[0041] An embodiment of the present application provides a method for obtaining parameters of a transistor, which comprises obtaining a plurality of first pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and obtaining a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; the substrate temperature refers to the temperature of a structure used to carry the transistor for heating; according to the plurality of first pulse IV curve graphs, determining a first transconductance maximum value corresponding to each dissipation power, and generating a first curve according to the first transconductance maximum value corresponding to each dissipation power, the first curve being used to represent the relationship between the dissipation power and the transconductance maximum value; according to the plurality of second pulse IV curve graphs, determining a second transconductance maximum value corresponding to each substrate temperature, and generating a second curve according to the second transconductance maximum value corresponding to each substrate temperature, the second curve being used to represent the relationship between the substrate temperature and the transconductance maximum value; according to the first curve and the second curve, calculating the ratio of the dissipation power of the transistor to the channel temperature. Compared with the prior art, after the transistor is pulsed IV tested, the method provided in the present application can construct a first curve of dissipated power and transconductance maximum value based on multiple first transconductance maximum values extracted from multiple first pulse IV curve diagrams, and construct a second curve of substrate temperature and transconductance maximum value based on multiple second transconductance maximum values extracted from multiple second pulse IV curve diagrams. Since the size of the transconductance reflects the control effect of the gate-source voltage on the drain-source current, the ratio of the dissipated power and the channel temperature determined by the above-mentioned first curve and the second curve avoids the current collapse effect and improves the accuracy of determining the above-mentioned ratio. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0043] Figure 1 is a flowchart of a method for obtaining transistor parameters according to an embodiment of the present application;
[0044] Figure 2 is a flowchart of a method for obtaining transistor parameters according to another embodiment of the present application;
[0045] Figure 3 is a first curve schematic diagram provided by an embodiment of the present application;
[0046] Figure 4 is a flowchart of a method for obtaining transistor parameters provided in yet another embodiment of the present application;
[0047] Figure 5 is a schematic diagram of a first transconductance curve extracted from a first pulse IV curve diagram provided by an embodiment of the present application;
[0048] Figure 6 is a second curve schematic diagram provided by an embodiment of the present application;
[0049] Figure 7 is a flowchart of a method for obtaining transistor parameters provided by another embodiment of the present application;
[0050] Figure 8 is a flowchart of a method for obtaining transistor parameters provided by another embodiment of the present application;
[0051] Fig. 9 is a DC IV curve diagram provided by an embodiment of the present application;
[0052] Fig.10 is an S parameter curve diagram of a transistor provided in an embodiment of the present application;
[0053] Fig.11 is a curve diagram of a transistor provided by an embodiment of the present application at a maximum efficiency point and a maximum power point;
[0054] Fig.12 It is a structural schematic diagram of a transistor parameter acquisition device provided in an embodiment of the present application;
[0055] Fig.13 It is a structural diagram of a terminal device provided in one embodiment of the present application. DETAILED DESCRIPTION
[0056] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.
[0057] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.
[0058] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0059] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.
[0060] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.
[0061] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0062] It should be noted that in all the embodiments of the present application, the transistor may be a high electron mobility transistor (HEMT).
[0063] See also Figure 1 , Figure 1 This is a flowchart of a method for obtaining transistor parameters provided by an embodiment of the present application. In the embodiment of the present application, the execution subject of the method for obtaining transistor parameters is a terminal device.
[0064] like Figure 1 As shown, a transistor parameter acquisition method provided in an embodiment of the present application may include S101 to S104, which are described in detail as follows:
[0065] In S101, a plurality of first pulse IV curve graphs are obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and a plurality of second pulse IV curve graphs are obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; the substrate temperature refers to the temperature of a structure used to support the transistor for heating.
[0066] In practical applications, the terminal equipment can perform pulse IV testing on the transistor by controlling the pulse IV testing system.
[0067] In an embodiment of the present application, before controlling the pulse IV test system to perform a pulse IV test on the transistor, the terminal device can set the test pulse width of the pulse IV test system to 200ns and the duty cycle to 0.01% to avoid the influence of the thermal effect generated by the pulse IV test system itself during the pulse IV test on the pulse IV test of the transistor.
[0068] In order to obtain the ratio between the dissipated power and the channel temperature of the transistor, the terminal device can control the pulse IV test system to perform pulse IV tests on the transistor at multiple different dissipated powers, and control the pulse IV test system to perform pulse IV tests on the transistor at multiple different substrate temperatures. The multiple different dissipated powers and the multiple different substrate temperatures can be determined according to actual needs and are not limited here.
[0069] It should be noted that the substrate temperature refers to the temperature of the structure used to carry the transistor for heating. For example, if the transistor is placed on a platform, the structure refers to the platform and the substrate temperature refers to the platform temperature; if the transistor is placed on a tray, the structure refers to the tray and the substrate temperature refers to the tray temperature.
[0070] After the temperature of the structure is stabilized, since the structure is used to support the transistor, the temperature of the structure will be transmitted to the transistor. Based on this, the channel temperature of the transistor is the substrate temperature.
[0071] Dissipation power, also known as the maximum allowable collector dissipation power PCM, refers to the maximum collector dissipation power when the transistor parameter change does not exceed the specified allowable value.
[0072] In one embodiment of the present application, whether performing pulse IV tests on transistors at multiple different dissipation powers or controlling a pulse IV test system to perform pulse IV tests on transistors at multiple different substrate temperatures, it is necessary to ensure that the substrate temperature remains stable to improve the accuracy of the first pulse IV curve graph and the second pulse IV curve graph obtained. The terminal device can perform the following steps: Figure 2 Steps S201 to S202 shown execute step S101, which are described in detail as follows:
[0073] In S201, when it is detected that the temperature of the structure reaches a first temperature, a temperature set of the structure within a set time period is acquired.
[0074] In this embodiment, the first temperature can be set according to actual needs and is not limited here.
[0075] In some possible embodiments, when it is necessary to perform pulse IV tests on a transistor at a plurality of different dissipation powers, the first temperature may be set to the ambient temperature of the region where the transistor is located.
[0076] In some other possible embodiments, when it is necessary to perform pulse IV tests on the transistor at multiple different substrate temperatures respectively, the first temperature may be set according to the test substrate temperature at which the transistor is subjected to the pulse IV test at this time.
[0077] Based on this, in this embodiment, after detecting that the temperature of the structure reaches the first temperature, the terminal device obtains the temperature set of the structure within a set time period. The set time period can be set according to actual needs and is not limited here.
[0078] The temperature set includes the temperature values of the structure at each time within a set time period.
[0079] After obtaining the temperature set, the terminal device may sequentially calculate the difference between each temperature value in the temperature set and the first temperature, and compare each difference with the first threshold value one by one. The first threshold value may be set according to actual needs and is not limited here.
[0080] In one embodiment of the present application, when the terminal device detects that the difference between each temperature value in the temperature set and the first temperature is greater than a target difference of a first threshold, it indicates that the temperature of the structure is not in a stable state and still fluctuates. Therefore, the terminal device can continue to obtain a set of temperature values of the structure within a set time period after the temperature value corresponding to the target difference is reached to detect whether the temperature of the structure is in a stable state.
[0081] In another embodiment of the present application, when the terminal device detects that the difference between each temperature value in the temperature set and the first temperature is less than or equal to the first threshold, step S202 may be executed.
[0082] In S202 , if the difference between each temperature value in the temperature set and the first temperature is less than or equal to a first threshold, a pulse IV test is performed on the transistor to obtain the plurality of first pulse IV curve graphs and the plurality of second pulse IV curve graphs.
[0083] In this embodiment, when the terminal device detects that the difference between each temperature value in the temperature set and the first temperature is less than or equal to the first threshold, it indicates that the temperature of the structure is in a stable state. Therefore, the terminal device can perform a pulse IV test on the transistor to obtain multiple first pulse IV curve graphs and multiple second pulse IV curve graphs.
[0084] It is understandable that when performing pulse IV tests on transistors at different dissipation powers, the terminal device can directly perform pulse IV tests on the transistors at multiple different dissipation powers respectively when detecting that the difference between each temperature value in the temperature set and the first temperature is less than or equal to the first threshold value, so as to obtain multiple first pulse IV curves. That is to say, when performing pulse IV tests on transistors at multiple different dissipation powers respectively, the substrate temperature remains unchanged.
[0085] When performing a pulse IV test on a transistor at different substrate temperatures, the terminal device can perform a pulse IV test on the transistor at the first temperature when it is detected that the difference between each temperature value in the temperature set and the first temperature is less than or equal to the first threshold value to obtain a second pulse IV curve graph at the first temperature. Thereafter, the terminal device can adjust the above-mentioned first temperature, and after detecting that the temperature of the structure reaches the adjusted first temperature, return to execute steps S201 to S202 until multiple second pulse IV test curve graphs are obtained.
[0086] In another embodiment of the present application, in order to further improve the accuracy of the acquired first pulse IV curve graph, the terminal device may specifically perform the following steps, which are described in detail as follows:
[0087] When it is detected that the substrate temperature is a second temperature and the current drain-source static bias voltage of the transistor is a set voltage, adjusting the gate-source static bias voltage of the transistor;
[0088] Determining the current dissipated power of the transistor according to the adjusted gate-source static bias voltage;
[0089] Under the current dissipated power, a pulse IV test is performed on the transistor to obtain a first pulse IV curve graph under the current dissipated power.
[0090] In this embodiment, the second temperature may be set to the ambient temperature of the region where the transistor is located.
[0091] The set voltage can be set according to actual needs and is not limited here. For example, the set voltage can be set to 10V.
[0092] It should be noted that, in order to implement pulse IV testing on transistors at multiple different dissipation powers, the terminal device may adjust the gate-source static bias voltage of the transistor to obtain multiple different dissipation powers of the transistor.
[0093] In this embodiment, after adjusting the gate-source static bias voltage of the transistor, the terminal device can determine the current dissipated power under the adjusted gate-source static bias voltage, and perform a pulse IV test on the transistor under the current dissipated power to obtain a first pulse IV curve under the current dissipated power.
[0094] Based on this, the terminal device can obtain first pulse IV curve graphs corresponding to multiple different dissipation powers.
[0095] In another embodiment of the present application, in order to further improve the accuracy of the acquired second pulse IV curve, the terminal device may specifically perform the following steps, which are described in detail as follows:
[0096] Obtaining a turn-off voltage of the transistor;
[0097] Adjusting the gate-source static bias voltage of the transistor according to the turn-off voltage to obtain a target gate-source voltage; the target gate-source voltage is less than the turn-off voltage;
[0098] When it is detected that the current drain-source static bias voltage of the transistor is the set voltage, a pulse IV test is performed on the transistor at the multiple different substrate temperatures to obtain the multiple second pulse IV curve graphs.
[0099] In this embodiment, the off voltage value is the voltage value when the transistor is turned off.
[0100] When pulse IV tests are performed on transistors at multiple different substrate temperatures, in order to avoid the influence of the transistor's dissipated power on the test results, the terminal device can adjust the transistor's dissipated power to zero. Therefore, the terminal device can adjust the transistor's gate-source static bias voltage according to the turn-off voltage to obtain a target gate-source voltage, and the target gate-source voltage is less than the turn-off voltage to make the transistor's dissipated power zero.
[0101] Based on this, in this embodiment, when the terminal device detects that the current drain-source static bias voltage of the transistor is a set voltage, it can perform a pulse IV test on the transistor at multiple substrate temperatures to obtain multiple second pulse IV curve graphs.
[0102] In S102, the first transconductance maximum value corresponding to each of the dissipated powers is determined according to the multiple first pulse IV curves, and a first curve is generated according to the first transconductance maximum value corresponding to each of the dissipated powers, wherein the first curve is used to represent the relationship between the dissipated power and the transconductance maximum value.
[0103] In an embodiment of the present application, for any first pulse IV curve graph, the terminal device can extract multiple first transconductances from the first pulse IV curve graph, and compare the multiple first transconductances one by one to obtain the maximum value of the first transconductance, thereby obtaining the maximum value of the first transconductance under the dissipation power corresponding to the first pulse IV curve graph.
[0104] Based on this, the terminal device can obtain the first transconductance maximum values corresponding to each of the multiple dissipation powers, and generate a first curve according to the first transconductance maximum values corresponding to each of the dissipation powers.
[0105] For example, see Figure 3 , Figure 3 is a first curve diagram provided by an embodiment of the present application. Figure 3 As shown, the hollow circles represent the first transconductance maximum values at different dissipation powers determined by a plurality of first pulse IV curves, and the solid lines represent the linear fitting results of the first transconductance maximum values at different dissipation powers.
[0106] In one embodiment of the present application, in order to further avoid the influence of the current collapse effect on the ratio value, the terminal device can specifically Figure 4 Steps S301 to S303 shown determine the first transconductance maximum value, as detailed below:
[0107] In S301, a first drain-source static bias voltage of the transistor in pulse IV testing under the plurality of different dissipation powers is obtained.
[0108] In S302, a first drain-source voltage of the plurality of first pulse IV curves is determined according to the first drain-source static bias voltage; the first drain-source voltage is greater than the first drain-source static bias voltage.
[0109] In S303, for each of the first pulse IV curve graphs, a first transconductance set of the first pulse IV curve graph at the first drain-source voltage is obtained, and a maximum value in the first transconductance set is determined as a first transconductance maximum value at a dissipation power corresponding to the first pulse IV curve graph; wherein the first transconductance set includes multiple transconductance values at a first drain-source voltage.
[0110] It should be noted that the first drain-source static bias voltage of the transistor in pulse IV tests under a plurality of different dissipation powers is the same.
[0111] In this embodiment, in order to avoid the influence of the current collapse effect, the terminal device can determine the first drain-source voltage of the plurality of first pulse IV curves according to the first drain-source static bias voltage.
[0112] It should be noted that the first drain-source voltage is greater than the first drain-source static bias voltage.
[0113] In some possible embodiments, the difference between the first drain-source voltage and the first drain-source static bias voltage is greater than a set value, wherein the set value can be set to any value between [5, 20].
[0114] For example, see Figure 5 , Figure 5 is a schematic diagram of a first transconductance curve extracted from a first pulse IV curve diagram provided by an embodiment of the present application. Figure 5 As shown, the schematic diagram of the first transconductance curve is the first transconductance curve corresponding to each other under different static bias voltages (including the first drain-source static bias voltage and the gate-source static bias voltage) when the first drain-source voltage is 15V and the substrate temperature is 25°C. Curve A is used to characterize the first transconductance curve when the gate-source static bias voltage is 0V and the first drain-source static bias voltage is 0V, curve B is used to characterize the first transconductance curve when the gate-source static bias voltage is -3V and the first drain-source static bias voltage is 5V, curve C is used to characterize the first transconductance curve when the gate-source static bias voltage is -3V and the first drain-source static bias voltage is 10V, and curve D is used to characterize the first transconductance curve when the gate-source static bias voltage is -3V and the first drain-source static bias voltage is 20V.
[0115] In this embodiment, after determining the first drain-source voltage, the terminal device can obtain all first transconductances under the first drain-source voltage from the first pulse IV curve for any first pulse IV curve, that is, obtain the first transconductance set under the first drain-source voltage. Afterwards, the terminal device can compare multiple transconductance values in the first transconductance set one by one to determine the maximum value in the first transconductance set, and determine the maximum value as the first transconductance maximum value under the dissipated power corresponding to the first pulse IV curve. The first transconductance set includes multiple transconductance values under the first drain-source voltage.
[0116] Based on this, the terminal device can obtain the first transconductance maximum value corresponding to each dissipated power.
[0117] In S103, the second transconductance maximum value corresponding to each substrate temperature is determined according to the multiple second pulse IV curves, and a second curve is generated according to the second transconductance maximum value corresponding to each substrate temperature, wherein the second curve is used to represent the relationship between the substrate temperature and the transconductance maximum value.
[0118] In an embodiment of the present application, for any second pulse IV curve graph, the terminal device can extract multiple second transconductances from the second pulse IV curve graph, and compare the multiple second transconductances one by one to obtain the second transconductance maximum value, thereby obtaining the second transconductance maximum value at the substrate temperature corresponding to the second pulse IV curve graph.
[0119] The terminal device can obtain the second transconductance maximum values corresponding to each of the multiple substrate temperatures, and generate a second curve according to the second transconductance maximum value corresponding to each substrate temperature.
[0120] For example, see Figure 6 , Figure 6 is a second curve diagram provided by an embodiment of the present application. Figure 6 As shown, the hollow circles represent the second transconductance maximum values at different substrate temperatures determined by a plurality of second pulse IV curves, and the solid lines represent the linear fitting results of the second transconductance maximum values at different substrate temperatures.
[0121] In one embodiment of the present application, in order to further avoid the influence of the current collapse effect on the ratio value, the terminal device can specifically Figure 7 Steps S401 to S403 shown determine the second transconductance maximum value, as detailed below:
[0122] In S401, a second drain-source static bias voltage of the transistor is obtained when a pulse IV test is performed on the transistor at the plurality of different substrate temperatures.
[0123] In S402, a second drain-source voltage of the plurality of second pulse IV curves is determined according to the second drain-source static bias voltage; the second drain-source voltage is greater than the second drain-source static bias voltage.
[0124] In S403, for each of the second pulse IV curve graphs, a second transconductance set of the second pulse IV curve graph at the second drain-source voltage is obtained, and the maximum value in the second transconductance set is determined as the second transconductance maximum value at the substrate temperature corresponding to the second pulse IV curve graph; wherein the second transconductance set includes multiple transconductance values at the second drain-source voltage.
[0125] It should be noted that the second drain-source static bias voltage of the transistor during the pulse IV test at a plurality of different substrate temperatures is the same.
[0126] In this embodiment, in order to avoid the influence of the current collapse effect, the terminal device can determine the second drain-source voltage of the plurality of second pulse IV curves according to the second drain-source static bias voltage.
[0127] It should be noted that the second drain-source voltage is greater than the second drain-source static bias voltage.
[0128] In some possible embodiments, the difference between the second drain-source voltage and the second drain-source static bias voltage is greater than a set value, wherein the set value can be set to any value between [5, 20].
[0129] In this embodiment, after determining the second drain-source voltage, the terminal device can obtain all second transconductances under the second drain-source voltage from the second pulse IV curve for any second pulse IV curve, that is, obtain the second transconductance set under the second drain-source voltage. Afterwards, the terminal device can compare multiple transconductance values in the second transconductance set one by one to determine the maximum value in the second transconductance set, and determine the maximum value as the second transconductance maximum value at the substrate temperature corresponding to the second pulse IV curve. The second transconductance set includes multiple transconductance values under the second drain-source voltage.
[0130] Based on this, the terminal device can obtain the second transconductance maximum value corresponding to each substrate temperature.
[0131] In S104, a ratio of the power dissipation of the transistor to the channel temperature is calculated according to the first curve and the second curve.
[0132] In the embodiment of the present application, since the first curve is used to represent the relationship between the dissipated power and the maximum transconductance, and the second curve is used to represent the relationship between the substrate temperature and the maximum transconductance, and the temperature of the structure is the channel temperature of the transistor after stabilization, the terminal device can calculate the ratio of the dissipated power of the transistor to the channel temperature through the first curve and the second curve.
[0133] In one embodiment of the present application, the terminal device can specifically Figure 8 S501-S502 shown determine the above ratio, which is described in detail as follows:
[0134] In S501 , a first slope of the first curve and a second slope of the second curve are calculated.
[0135] In S502, the ratio is calculated according to the first slope, the second slope, and the ambient temperature of the region where the transistor is located.
[0136] In this embodiment, the terminal device can determine that there is a linear relationship between the dissipated power and the first transconductance maximum value through the first curve. Therefore, the terminal device can calculate the first slope of the first curve according to the specific values corresponding to the dissipated power and the first transconductance maximum value.
[0137] The terminal device can determine that there is a linear relationship between the substrate temperature and the second transconductance maximum value through the second curve. Therefore, the terminal device can calculate the second slope of the second curve according to the specific values corresponding to the substrate temperature and the second transconductance maximum value.
[0138] Afterwards, the terminal device may calculate the ratio between the dissipated power and the channel temperature of the transistor according to the first slope, the second slope, and the ambient temperature of the region where the transistor is located.
[0139] Specifically, the above ratio can be calculated according to the following formula:
[0140]
[0141] Among them, R th It represents the ratio between the power dissipation of the transistor and the channel temperature, P diss represents the power dissipation of the transistor, T c Represents the channel temperature of the transistor, T amb Indicates the ambient temperature of the area where the transistor is located.
[0142] From the above, it can be seen that a method for obtaining parameters of a transistor provided in an embodiment of the present application is obtained by obtaining a plurality of first pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; the substrate temperature refers to the temperature of a structure used to carry the transistor for heating; according to the plurality of first pulse IV curve graphs, a first transconductance maximum value corresponding to each dissipation power is determined, and according to the first transconductance maximum value corresponding to each dissipation power, a first curve is generated, and the first curve is used to represent the relationship between the dissipation power and the transconductance maximum value; according to the plurality of second pulse IV curve graphs, a second transconductance maximum value corresponding to each substrate temperature is determined, and according to the second transconductance maximum value corresponding to each substrate temperature, a second curve is generated, and the second curve is used to represent the relationship between the substrate temperature and the transconductance maximum value; according to the first curve and the second curve, the ratio of the dissipation power of the transistor to the channel temperature is calculated. Compared with the prior art, after the transistor is pulsed IV tested, the method provided in the present application can construct a first curve of dissipated power and transconductance maximum value according to multiple first transconductance maximum values extracted from multiple first pulse IV curve diagrams, and construct a second curve of substrate temperature and transconductance maximum value according to multiple second transconductance maximum values extracted from multiple second pulse IV curve diagrams. Since the size of the transconductance reflects the control effect of the gate-source voltage on the drain-source current, the ratio of the dissipated power and the channel temperature determined by the first curve and the second curve avoids the influence of the current collapse effect, thereby improving the accuracy of determining the above ratio.
[0143] In one embodiment of the present application, in order to verify the accuracy of the ratio determined above at the circuit level, an Angelov large signal model suitable for the transistor is first established, and then various parameters of the transistor are tested in combination with the ratio.
[0144] For example, see Fig. 9 , Fig. 9 : is a DC IV curve diagram provided by an embodiment of the present application. Fig. 9 As shown, when the drain-source voltage of the transistor is [0, 35V] and the gate-source voltage is [-3, 1V], the solid line is the IV curve obtained by simulating the transistor according to the above ratio, and the hollow circle is the IV result obtained by actually measuring the transistor. Fig. 9 It can be seen that Fig. 9 The solid line in FIG. 1 accurately fits the negative slope of the actual measured IV data, thereby illustrating the accuracy of the determination of the above ratio.
[0145] In practical applications, since self-heating also affects the S parameters of the transistor, please refer to Fig.10 , Fig.10 is an S parameter curve diagram of a transistor provided in an embodiment of the present application. Fig.10 As shown in (a) and (b), at the two self-heating bias points of the transistor (drain-source voltage is 12V, gate-source voltage is 0.4V and drain-source voltage is 18V, gate-source voltage is -0.4V), the solid lines are the S parameter curves obtained by simulating the transistor according to the above ratio, and the hollow circles are the S parameter results obtained by actually measuring the transistor. Fig.10 It can be seen that Fig.10 The good consistency between the solid line and the hollow circle in further illustrates the accuracy of the determination of the above ratio.
[0146] See also Fig.11 , Fig.11 is a curve diagram of a transistor provided in an embodiment of the present application at the maximum efficiency point and the maximum power point. Fig.11 As shown in (a), when the drain-source static bias voltage of the transistor is 15V, the gate-source static bias voltage is -1.1V, and the RF frequency is 4GHz, the solid line L1 is the conversion power gain curve at the maximum efficiency point obtained by simulating the test of the transistor according to the above ratio, the solid line L2 is the output power curve at the maximum efficiency point obtained by simulating the test of the transistor according to the above ratio, the solid line L3 is the power added efficiency curve at the maximum efficiency point obtained by simulating the test of the transistor according to the above ratio, the hollow circle A1 is the conversion power gain result of the actual measurement of the transistor at the maximum efficiency point, the hollow circle A2 is the output power result of the actual measurement of the transistor at the maximum efficiency point, and the hollow circle A3 is the power added efficiency result of the actual measurement of the transistor at the maximum efficiency point. Fig.11As shown in (b), when the drain-source static bias voltage of the transistor is 15V, the gate-source static bias voltage is -1.1V, and the RF frequency is 4GHz, the solid line L4 is the conversion power gain curve at the maximum power point obtained by simulating the test of the transistor according to the above ratio, the solid line L5 is the output power curve at the maximum power point obtained by simulating the test of the transistor according to the above ratio, the solid line L6 is the power added efficiency curve at the maximum power point obtained by simulating the test of the transistor according to the above ratio, the hollow circle A4 is the conversion power gain result of the actual measurement of the transistor at the maximum power point, the hollow circle A5 is the output power result of the actual measurement of the transistor at the maximum power point, and the hollow circle A6 is the power added efficiency result of the actual measurement of the transistor at the maximum power point. Fig.11 It can be seen that Fig.11 The good consistency between the solid line and the hollow circle in further illustrates the accuracy of the determination of the above ratio.
[0147] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0148] Corresponding to the method for obtaining parameters of a transistor described in the above embodiment, Fig.12 The structure diagram of a transistor parameter acquisition device provided by an embodiment of the present application is shown. For the convenience of explanation, only the part related to the embodiment of the present application is shown. Fig.12 The transistor parameter acquisition device 800 includes: a first acquisition unit 81, a first generation unit 82, a second generation unit 83 and a first calculation unit 84.
[0149] in:
[0150] The first acquisition unit 81 is used to obtain multiple first pulse IV curve graphs obtained by performing pulse IV tests on the transistor at multiple different dissipation powers, and to obtain multiple second pulse IV curve graphs obtained by performing pulse IV tests on the transistor at multiple different substrate temperatures; the substrate temperature refers to the temperature of the structure used to support the transistor for heating.
[0151] The first generating unit 82 is used to determine the first transconductance maximum value corresponding to each of the dissipated powers according to the multiple first pulse IV curve diagrams, and generate a first curve according to the first transconductance maximum value corresponding to each of the dissipated powers, wherein the first curve is used to represent the relationship between the dissipated power and the transconductance maximum value.
[0152] The second generating unit 83 is used to determine the second transconductance maximum value corresponding to each substrate temperature according to the multiple second pulse IV curve diagrams, and to generate a second curve according to the second transconductance maximum value corresponding to each substrate temperature, wherein the second curve is used to represent the relationship between the substrate temperature and the transconductance maximum value.
[0153] The first calculation unit 84 is used for calculating the ratio of the dissipated power of the transistor to the channel temperature according to the first curve and the second curve.
[0154] In one embodiment of the present application, the first acquisition unit 81 specifically includes: a second acquisition unit and a first testing unit.
[0155] The second acquisition unit is used to acquire a temperature set of the structure within a set time period after detecting that the temperature of the structure reaches a first temperature.
[0156] The first test unit is used to perform a pulse IV test on the transistor to obtain the multiple first pulse IV curve graphs and the multiple second pulse IV curve graphs if the difference between each temperature value in the temperature set and the first temperature is less than or equal to a first threshold.
[0157] In one embodiment of the present application, the first acquisition unit 81 specifically includes: a first adjustment unit, a first determination unit and a second testing unit.
[0158] The first adjustment unit is used to adjust the gate-source static bias voltage of the transistor when it is detected that the substrate temperature is a second temperature and the current drain-source static bias voltage of the transistor is a set voltage.
[0159] The first determining unit is used to determine the current dissipated power of the transistor according to the adjusted gate-source static bias voltage.
[0160] The second test unit is used to perform a pulse IV test on the transistor under the current dissipated power to obtain a first pulse IV curve diagram under the current dissipated power.
[0161] In one embodiment of the present application, the first acquisition unit 81 specifically includes: a third acquisition unit, a second adjustment unit and a third test unit.
[0162] The third acquisition unit is used to acquire the turn-off voltage of the transistor.
[0163] The second adjustment unit is used to adjust the gate-source static bias voltage of the transistor according to the shutdown voltage to obtain a target gate-source voltage; the target gate-source voltage is smaller than the shutdown voltage.
[0164] The third test unit is used to perform a pulse IV test on the transistor at the multiple different substrate temperatures to obtain the multiple second pulse IV curve graphs when it is detected that the current drain-source static bias voltage of the transistor is a set voltage.
[0165] In one embodiment of the present application, the first generating unit 82 specifically includes: a fourth acquiring unit, a second determining unit and a third determining unit. Among them:
[0166] The fourth acquisition unit is used to acquire a first drain-source static bias voltage of the transistor when performing a pulse IV test under the multiple different dissipation powers.
[0167] The second determination unit is used to determine the first drain-source voltage of the plurality of first pulse IV curves according to the first drain-source static bias voltage; the first drain-source voltage is greater than the first drain-source static bias voltage.
[0168] The third determination unit is used to obtain, for each of the first pulse IV curve graphs, a first transconductance set of the first pulse IV curve graph at the first drain-source voltage, and determine a maximum value in the first transconductance set as a first transconductance maximum value at a dissipation power corresponding to the first pulse IV curve graph; wherein the first transconductance set includes multiple transconductance values at the first drain-source voltage.
[0169] In one embodiment of the present application, the second generating unit 83 specifically includes: a fifth acquiring unit, a fourth determining unit and a fifth determining unit. Among them:
[0170] The fifth acquisition unit is used to acquire a second drain-source static bias voltage of the transistor when the pulse IV test is performed at the multiple different substrate temperatures.
[0171] The fourth determination unit is used to determine the second drain-source voltage of the plurality of second pulse IV curves according to the second drain-source static bias voltage; the second drain-source voltage is greater than the second drain-source static bias voltage.
[0172] The fifth determination unit is used to obtain, for each of the second pulse IV curve graphs, a second transconductance set of the second pulse IV curve graph at the second drain-source voltage, and determine the maximum value in the second transconductance set as the second transconductance maximum value at the substrate temperature corresponding to the second pulse IV curve graph; wherein the second transconductance set includes multiple transconductance values at the second drain-source voltage.
[0173] In one embodiment of the present application, the first calculation unit 84 specifically includes: a second calculation unit and a third calculation unit. Among them:
[0174] The second calculation unit is used to calculate a first slope of the first curve and a second slope of the second curve.
[0175] The third calculation unit is used to calculate the ratio according to the first slope, the second slope and the ambient temperature of the area where the transistor is located.
[0176] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.
[0177] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.
[0178] Fig.13 This is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application. Fig.13 As shown, the terminal device 9 of this embodiment includes: at least one processor 90 ( Fig.13 Only one is shown in the figure) a processor, a memory 91, and a computer program 92 stored in the memory 91 and executable on the at least one processor 90, and when the processor 90 executes the computer program 92, the steps in the above-mentioned parameter acquisition method embodiment of any of the transistors are implemented.
[0179] The terminal device may include, but is not limited to, a processor 90 and a memory 91. Those skilled in the art will appreciate that Fig.13 It is only an example of the terminal device 9 and does not constitute a limitation on the terminal device 9. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, for example, it may also include input and output devices, network access devices, etc.
[0180] The processor 90 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.
[0181] In some embodiments, the memory 91 may be an internal storage unit of the terminal device 9, such as the memory of the terminal device 9. In other embodiments, the memory 91 may also be an external storage device of the terminal device 9, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the terminal device 9. Further, the memory 91 may also include both the internal storage unit of the terminal device 9 and an external storage device. The memory 91 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 91 may also be used to temporarily store data that has been output or is to be output.
[0182] An embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.
[0183] An embodiment of the present application provides a computer program product. When the computer program product runs on a terminal device, the terminal device can implement the steps in the above-mentioned method embodiments when executing the computer program product.
[0184] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the terminal device, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.
[0185] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0186] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A method for obtaining transistor parameters, characterized in that: include: Acquire a plurality of first pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and acquire a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; The substrate temperature refers to the temperature of the structure used to support the transistor for heating; Determine, according to the plurality of first pulse IV curves, a first transconductance maximum value corresponding to each of the dissipated powers, and generate a first curve according to the first transconductance maximum value corresponding to each of the dissipated powers, wherein the first curve is used to represent the relationship between the dissipated power and the transconductance maximum value; Determine the second transconductance maximum value corresponding to each substrate temperature according to the plurality of second pulse IV curves, and generate a second curve according to the second transconductance maximum value corresponding to each substrate temperature, wherein the second curve is used to represent the relationship between the substrate temperature and the transconductance maximum value; The ratio of the power dissipation of the transistor to the channel temperature is calculated according to the first curve and the second curve.
2. The transistor parameter acquisition method according to claim 1, characterized in that: The method of obtaining a plurality of first pulse IV curves obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and obtaining a plurality of second pulse IV curves obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures, comprises: When it is detected that the temperature of the structure reaches a first temperature, obtaining a temperature set of the structure within a set time period; If the difference between each temperature value in the temperature set and the first temperature is less than or equal to a first threshold, a pulse IV test is performed on the transistor to obtain the plurality of first pulse IV curve graphs and the plurality of second pulse IV curve graphs.
3. The transistor parameter acquisition method according to claim 1, characterized in that: The obtaining transistor performs a plurality of first pulse IV curves obtained by performing pulse IV tests at a plurality of different dissipation powers, including: When it is detected that the substrate temperature is a second temperature and the current drain-source static bias voltage of the transistor is a set voltage, adjusting the gate-source static bias voltage of the transistor; Determining the current dissipated power of the transistor according to the adjusted gate-source static bias voltage; Under the current dissipated power, a pulse IV test is performed on the transistor to obtain a first pulse IV curve graph under the current dissipated power.
4. The transistor parameter acquisition method according to claim 1, characterized in that: The step of obtaining a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures comprises: Obtaining a turn-off voltage of the transistor; Adjusting the gate-source static bias voltage of the transistor according to the turn-off voltage to obtain a target gate-source voltage; the target gate-source voltage is less than the turn-off voltage; When it is detected that the current drain-source static bias voltage of the transistor is the set voltage, a pulse IV test is performed on the transistor at the multiple different substrate temperatures to obtain the multiple second pulse IV curve graphs.
5. The transistor parameter acquisition method according to claim 1, characterized in that: The determining, according to the plurality of first pulse IV curves, the first transconductance maximum value corresponding to each of the dissipated powers, comprises: Obtaining a first drain-source static bias voltage of the transistor for pulse IV testing under the plurality of different dissipation powers; Determining a first drain-source voltage of the plurality of first pulse IV curves according to the first drain-source static bias voltage; the first drain-source voltage being greater than the first drain-source static bias voltage; For each of the first pulse IV curve graphs, a first transconductance set of the first pulse IV curve graph at the first drain-source voltage is obtained, and a maximum value in the first transconductance set is determined as the first transconductance maximum value at the dissipation power corresponding to the first pulse IV curve graph; wherein the first transconductance set includes multiple transconductance values at the first drain-source voltage.
6. The transistor parameter acquisition method according to claim 1, characterized in that: Determining the second transconductance maximum value corresponding to each substrate temperature according to the plurality of second pulse IV curves includes: Obtaining a second drain-source static bias voltage of the transistor for pulse IV testing at the plurality of different substrate temperatures; Determining a second drain-source voltage of the plurality of second pulse IV curves according to the second drain-source static bias voltage; the second drain-source voltage being greater than the second drain-source static bias voltage; For each of the second pulse IV curve graphs, a second transconductance set of the second pulse IV curve graph at the second drain-source voltage is obtained, and a maximum value in the second transconductance set is determined as the second transconductance maximum value at the substrate temperature corresponding to the second pulse IV curve graph; wherein the second transconductance set includes multiple transconductance values at the second drain-source voltage.
7. The method for obtaining transistor parameters according to any one of claims 1 to 6, characterized in that: The calculating, according to the first curve and the second curve, to obtain a ratio of the power dissipation of the transistor to the channel temperature comprises: calculating a first slope of the first curve and a second slope of the second curve; The ratio is calculated according to the first slope, the second slope, and the ambient temperature of the region where the transistor is located.
8. A transistor parameter acquisition device, characterized in that: include: A first acquisition unit is used to acquire a plurality of first pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different dissipation powers, and to acquire a plurality of second pulse IV curve graphs obtained by respectively performing pulse IV tests on the transistor at a plurality of different substrate temperatures; The substrate temperature refers to the temperature of the structure used to support the transistor for heating; A first generating unit, configured to determine a first transconductance maximum value corresponding to each of the dissipated powers according to the plurality of first pulse IV curve graphs, and to generate a first curve according to the first transconductance maximum value corresponding to each of the dissipated powers, wherein the first curve is used to represent a relationship between the dissipated power and the transconductance maximum value; A second generating unit, configured to determine a second transconductance maximum value corresponding to each substrate temperature according to the plurality of second pulse IV curve graphs, and to generate a second curve according to the second transconductance maximum value corresponding to each substrate temperature, wherein the second curve is used to represent a relationship between the substrate temperature and the transconductance maximum value; The first calculation unit is used to calculate the ratio of the dissipated power of the transistor to the channel temperature according to the first curve and the second curve.
9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method for obtaining transistor parameters as claimed in any one of claims 1 to 7 is implemented.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for obtaining transistor parameters as claimed in any one of claims 1 to 7 is implemented.