Row address decoding circuit, memory and chip

Abstract

The present application provides a row address decoding circuit, a memory and a chip, wherein the row address decoding circuit includes: a decoding module, which is used to decode an address signal into a row address and output a decoding signal; a driving module, which is used to convert the decoding signal output by the decoding module into a row selection signal; an isolation module, whose input end is coupled to the output end of the decoding module, and whose output end is coupled to the input end of the driving module, wherein the isolation module is disconnected when the power supply voltage of the driving module is higher than a first preset threshold value, and the isolation module is turned on when the power supply voltage of the driving module is lower than the first preset threshold value. The present application provides a technical solution for effectively isolating low-voltage devices and high-voltage devices.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a row address decoding circuit, a memory, and a chip. Background Art

[0002] The current memory cell row selection bias voltage is low voltage in data reading and programming mode, and high voltage in erase mode, for example, ~12V. Therefore, the row address decoding circuit needs to use a high voltage device to drive the row selection in erase mode.

[0003] However, the pre-decoding circuit in the row address decoding circuit generally works in a low voltage domain and uses low voltage devices. How to balance the reliability of low voltage devices and high voltage devices to achieve row address decoding is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a row address decoding circuit and a technical solution for effectively isolating low-voltage devices and high-voltage devices.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect, a row address decoding circuit is provided, which includes: a decoding module, which is used to decode an address signal into a row address and output a decoding signal; a driving module, which is used to convert the decoding signal output by the decoding module into a row selection signal; an isolation module, whose input end is coupled to the output end of the decoding module and whose output end is coupled to the input end of the driving module, wherein the isolation module is disconnected when the power supply voltage of the driving module is higher than a first preset threshold value, and the isolation module is turned on when the power supply voltage of the driving module is lower than the first preset threshold value.

[0007] Optionally, the isolation module includes: an N-type enhancement field effect transistor, the drain of the N-type enhancement field effect transistor is coupled to the output end of the decoding module, the source of the N-type enhancement field effect transistor is coupled to the input end of the driving module, and the gate of the N-type enhancement field effect transistor is connected to the isolation control signal.

[0008] Optionally, the turn-on threshold voltage of the N-type enhancement mode field effect transistor is a negative value.

[0009] Optionally, when the power supply voltage of the driving module is higher than the first preset threshold and lower than the second preset threshold, the voltage of the isolation control signal is the first voltage; when the power supply voltage of the driving module is higher than the second preset threshold, the voltage of the isolation control signal is the second voltage and the ground terminal of the driving module is connected to the power supply voltage, the second preset threshold is greater than the first preset threshold, and the second voltage is greater than the first voltage.

[0010] Optionally, the first voltage is a ground voltage, and the second voltage is between the ground voltage and a power supply voltage.

[0011] Optionally, the row address decoding circuit further includes: an isolation control module, used to generate an isolation control signal, wherein the isolation control signal is used to control the on or off of the isolation module.

[0012] Optionally, the isolation control circuit includes:

[0013] A gating unit, wherein a first end of the gating unit is grounded, and a second end of the gating unit is connected to an operating voltage, and is used to selectively output a ground voltage or an operating voltage as the isolation control signal.

[0014] Optionally, the operating voltage is a power supply voltage or a second voltage, and the second voltage is greater than the ground voltage and less than the power supply voltage.

[0015] Optionally, the gating unit includes:

[0016] A first switch, wherein a first end of the first switch is connected to the power supply voltage; a second switch, wherein a first end of the second switch is connected to the second voltage; a PMOS tube, wherein a source of the PMOS tube is coupled to the second end of the first switch and the second end of the second switch, and a gate of the PMOS tube is connected to a mode control signal; and an NMOS tube, wherein a source of the NMOS tube is grounded, a gate of the NMOS tube is connected to the mode control signal, a drain of the NMOS tube is coupled to a drain of the PMOS tube, and outputs the isolation control signal.

[0017] In a second aspect, the present application further discloses a memory, which includes the row address decoding circuit.

[0018] In a third aspect, the present application further discloses a chip, which includes the row address decoding circuit.

[0019] In a fifth aspect, the present application also discloses a terminal device, wherein the row address decoding circuit of the terminal device either includes the memory or includes the chip.

[0020] Compared with the prior art, the technical solution of this application has the following beneficial effects:

[0021] Since the decoding module is a low-voltage device, the driving module works in a high-voltage mode in the erasing mode and in a low-voltage mode in the non-erasing mode, the decoding module and the driving module are selectively isolated by setting an isolation module in the technical solution of the present application. The isolation module is disconnected when the power supply voltage of the driving module is higher than the first preset threshold, and the isolation module is turned on when the power supply voltage of the driving module is lower than the first preset threshold, thereby realizing the selective isolation of the decoding module and the driving module and ensuring the reliability of the address decoding circuit.

[0022] Furthermore, the isolation module is an N-type enhanced field effect transistor, and the conduction threshold voltage of the N-type enhanced field effect transistor is a negative value. When the isolation module in the technical solution of the present application is turned on, it can losslessly transmit the selected and unselected levels of the row address, so there is no need to design a larger size. Under the premise of not increasing the area cost, the row address decoding circuit function is guaranteed, the isolation between high and low voltage devices is effectively realized, and the address decoding transmission speed is improved.

[0023] Furthermore, when the power supply voltage of the driving module is higher than the second preset threshold, the voltage of the isolation control signal is the second voltage and the ground terminal of the driving module is connected to the power supply voltage, the second preset threshold is greater than the first preset threshold, and the second voltage is greater than the first voltage. The technical file of this application can effectively avoid the occurrence of more reasonable circuit leakage by cooperating with gate control when turning off isolation, achieve better isolation, and further ensure the reliability of the address decoding circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a structural diagram of a row address decoding circuit provided in an embodiment of the present application;

[0025] Figure 2 is a structural diagram of another row address decoding circuit provided in an embodiment of the present application;

[0026] Figure 3 is a specific structural diagram of a row address decoding circuit provided in an embodiment of the present application;

[0027] Figure 4 It is a signal timing diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] As described in the background technology, the pre-decoding circuit in the row address decoding circuit generally works in the low voltage domain and uses low voltage devices. How to balance the reliability of low voltage devices and high voltage devices to achieve row address decoding is a technical problem that needs to be solved urgently.

[0029] In the technical solution of the present application, the decoding module and the driving module are selectively isolated by setting an isolation module. The isolation module is disconnected when the power supply voltage of the driving module is higher than the first preset threshold, and the isolation module is turned on when the power supply voltage of the driving module is lower than the first preset threshold, thereby realizing the selective isolation of the decoding module and the driving module, avoiding the withstand voltage problem of the device, and ensuring the reliability of the address decoding circuit.

[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] The embodiment of the present invention provides a row address decoding circuit, referring to Figure 1 The row address decoding circuit includes: a decoding module 101, an isolation module 102 and a driving module 103.

[0032] The input end of the decoding module 101 inputs an address signal, and the decoding module 101 is used to decode the address signal into a row address and output a decoding signal. The driving module 103 is used to convert the decoding signal output by the decoding module 101 into a row selection signal.

[0033] In this embodiment, the isolation module 102 is coupled between the decoding module 101 and the driving module 103 and can be selectively turned on. When the isolation module 102 is turned on, the decoding signal of the decoding module 101 is output to the driving module 103 through the isolation module 102; when the isolation module 102 is turned off, the decoding signal of the decoding module 101 will no longer be output to the driving module 103 through the isolation module 102, and the driving module 103 converts the latched decoding signal to obtain a row selection signal.

[0034] Specifically, the isolation module 102 is disconnected when the power supply voltage of the driving module 103 is higher than the first preset threshold, and the isolation module 102 is connected when the power supply voltage of the driving module 103 is lower than the first preset threshold.

[0035] In a non-limiting embodiment, the power supply voltage connected to the decoding module 101 is VDD, and the power supply voltage connected to the driving module 103 is VPP. For example, the power supply voltage VDD is a 2.5 volt (V) domain power supply. In the erase mode, the power supply voltage VPP is a high voltage, for example, the power supply voltage VPP is greater than or equal to 8V. In the non-erasing mode, for example, in the read mode and the write mode, the power supply voltage VDD is equal to the power supply voltage VPP.

[0036] It should be noted that the first preset threshold can be set according to the actual application scenario. For example, the first preset threshold is 8V, or any other feasible value, and the present application does not impose any limitation on this.

[0037] In the embodiment of the present application, in the erasing mode, the isolation module 102 is used to isolate the decoding module 101 from the driving module 103, thereby avoiding the voltage resistance problem of the device and ensuring the reliability of the address decoding circuit.

[0038] In a non-limiting embodiment, the isolation module 102 may include an N-type enhancement type (native) field effect transistor, the drain of the N-type enhancement type field effect transistor is coupled to the output end of the decoding module 101, the source of the N-type enhancement type field effect transistor is coupled to the input end of the driving module 103, and the gate of the N-type enhancement type field effect transistor is connected to the isolation control signal.

[0039] In this embodiment, the N-type enhancement mode field effect transistor is turned on or off by an isolation control signal. The isolation control signal can be an external input signal or a signal generated inside the memory.

[0040] Furthermore, the turn-on threshold voltage of the N-type enhancement mode field effect transistor is a negative value.

[0041] Since the conduction threshold voltage of the N-type enhancement field effect transistor is a negative value, the low level and high level corresponding to the selected and unselected row address decoding can be transmitted to the subsequent high-voltage drive circuit without loss, thereby realizing the address decoding function.

[0042] This is because the N-type enhancement field effect transistor is turned on when the gate-source voltage is higher than the turn-on threshold voltage Vt, and is turned off otherwise. When the N-type enhancement field effect transistor is turned on, the isolation control signal of its gate is high level, for example, the voltage of the isolation control signal is VDD. When the voltage to be transmitted is 0 level, VDD-0>Vt, so 0 level can be transmitted losslessly; when the voltage to be transmitted is VDD, vgs=VDD-VDD=0, because the turn-on threshold voltage Vt<0, the voltage VDD can also be transmitted losslessly.

[0043] Since both low and high levels in the row address decoding circuit of the present application can be transmitted losslessly, there is no need to increase the size of the transmission device, thereby reducing the area of ​​the row address decoding circuit and thus reducing the power consumption of the address decoding circuit.

[0044] Furthermore, since the conduction threshold voltage of the N-type enhancement field effect transistor is a negative value, the N-type enhancement field effect transistor may have a problem of not being able to turn off, resulting in leakage. In order to avoid this leakage problem, in the embodiment of the present application, when the power supply voltage of the driving module 103 is higher than the first preset threshold and lower than the second preset threshold, the voltage of the isolation control signal is the first voltage; when the power supply voltage of the driving module 103 is higher than the second preset threshold, the voltage of the isolation control signal is the second voltage and the ground terminal of the driving module is connected to the power supply voltage, the second preset threshold is greater than the first preset threshold, and the second voltage is greater than the first voltage.

[0045] In the embodiment of the present application, when the power supply voltage of the driving module 103 is high voltage, the voltage of the isolation control signal and the ground terminal voltage of the driving module are raised to control the gate-source voltage difference of the N-type enhancement field effect transistor to be less than the turn-on threshold voltage, thereby achieving the purpose of turning off the N-type enhancement field effect transistor, avoiding leakage of the N-type enhancement field effect transistor, and playing an effective isolation role.

[0046] In a non-limiting example, see Figure 2 , Figure 2 FIG. 1 shows another structure of a row address decoding circuit. The row address decoding circuit may further include an isolation control module 104 .

[0047] The isolation control module 104 is used to generate an isolation control signal, and the isolation control signal is used to control the on or off of the isolation module 102. The isolation control module 104 can input a mode control signal, and the mode control signal can specifically control the working mode of the row address decoding circuit. The working mode of the row address decoding circuit is selected from the following modes: erase mode, read modulus, and write mode.

[0048] In a specific implementation, in the erasing mode, the isolation control module 104 generates an isolation control signal to control the isolation module 102 to be turned off, and the isolation module 102 isolates the decoding module 101 from the driving module 103, and the isolation control signal is at a low level. In the non-erasing mode, the isolation control module 104 generates an isolation control signal to control the isolation module 102 to be turned on, and the isolation module 102 connects the decoding module 101 with the driving module 103. The isolation module 102 can transmit a high level or a low level without loss, and the isolation control signal is at a high level.

[0049] In a specific embodiment, the isolation control circuit 104 may include a gating unit (not shown). A first terminal of the gating unit is grounded, and a second terminal of the gating unit is connected to an operating voltage, for selectively outputting a ground voltage or an operating voltage as an isolation control signal.

[0050] Specifically, the operating voltage is the power supply voltage VDD or the second voltage VDD18, and the second voltage VDD18 is greater than the ground voltage and less than the power supply voltage VDD. For example, the power supply voltage VDD is 2.5V, and the second voltage VDD18 is 1.8V.

[0051] In a specific application scenario, the row address decoding circuit is included in a memory, and the memory can be specifically a flash memory. The memory is a dual power supply design, wherein the dual power supply design is based on a power supply voltage VDD and a second voltage VDD18, the power supply voltage VDD is a 2.5V domain power supply, and the second voltage VDD18 is a 1.8V domain power supply.

[0052] In a non-limiting example, see Figure 3 , Figure 3 The specific structure of a row address decoding circuit is shown, wherein the isolation module 102 is an N-type enhancement field effect transistor N0.

[0053] The isolation control module 104 includes a first switch T0, a second switch T1, a PMOS tube M1 and an NMOS tube N1. The first end of the first switch T0 is connected to the power supply voltage VDD, and the first end of the second switch T1 is connected to the second voltage VDD18. The source of the PMOS tube M1 is coupled to the second end of the first switch T0 and the second end of the second switch T1, and the gate of the PMOS tube M1 is connected to the mode control signal VM. The source of the NMOS tube N1 is grounded, the gate of the NMOS tube N1 is connected to the mode control signal, the drain of the NMOS tube N1 is coupled to the drain of the PMOS tube M1, and the isolation control signal VN0 is output.

[0054] The working process of the row address decoding circuit is described below in combination with the timing of each signal.

[0055] Specifically, refer to Figure 4 In the address decoding stage of the read-erase mode, the power supply voltage VPP of the driving module 103 is equal to the power supply voltage VDD of the decoding module 101, the ground voltage xgnd of the driving module 103 and the decoding module 101 is 0 level, T0 is turned on, T1 is turned off, and the mode control signal VM is low level 0V. At this time, the PMOS tube M1 is turned on, the NMOS tube N1 is turned off, and the isolation control signal VN0 is high level VDD. The gate-source voltage difference of the N-type enhancement field effect tube is greater than the turn-on threshold voltage, the N-type enhancement field effect tube N0 is turned on, and the decoding module 101 outputs the decoding signal to the driving module 103.

[0056] When the erase mode enters the high-voltage stage, the N-type enhancement field effect transistor N0 will be turned off to play an isolation role. Specifically, the high-voltage stage is divided into two stages: high-voltage stage 1 and high-voltage stage 2. Among them, the voltage value of the power supply voltage VPP of the driving module 103 in the high-voltage stage 2 is higher than the voltage value of the power supply voltage VPP in the high-voltage stage 1, and the N-type enhancement field effect transistor N0 is more likely to leak, so the leakage problem needs to be solved in the high-voltage stage 2.

[0057] Specifically, in the high voltage stage 1, when the power supply voltage VPP is greater than the power supply voltage VDD and VPP<=8V, the ground voltage xgnd is kept at 0 level, and the mode control signal VM is the power supply voltage VDD. At this time, the PMOS tube M1 is turned off, the NMOS tube N1 is turned on, the isolation control signal VN0 is a low level 0V, the gate-source voltage difference of the N-type enhancement field effect tube is less than the turn-on threshold voltage, and the N-type enhancement field effect tube N0 is turned off.

[0058] Specifically, in the high-voltage stage 2, when the power supply voltage VPP is greater than 8V, for example, when it reaches 12V, in order to ensure the reliability of the high-voltage device, the ground voltage xgnd will be switched to the power supply voltage VDD, and the isolation control signal VN0 will be raised accordingly to implement protection. In order to effectively turn off the N-type enhancement field effect transistor N0, the first switch T0 is turned off, the second switch T1 is turned on, and the mode control signal VM is a low level 0V. At this time, the PMOS tube M1 is turned on, the NMOS tube N1 is turned off, and the isolation control signal VN0 is VDD18. Since the gate voltage of the N-type enhancement field effect transistor N0 is lower than the xgnd level, even if its threshold is a negative value, the N-type enhancement field effect transistor N0 can be completely turned off, effectively avoiding leakage from the power supply voltage VPP to xgnd, thereby achieving effective isolation.

[0059] In the embodiment of the present application, when the power supply voltage of the driving module 103 is high voltage, the voltage of the isolation control signal VN0 and the ground terminal voltage xgnd of the driving module are raised to control the gate voltage of the N-type enhancement field effect transistor to be lower than the xgnd level, thereby achieving the purpose of turning off the N-type enhancement field effect transistor, avoiding leakage of the N-type enhancement field effect transistor, and playing an effective isolation role.

[0060] It should be noted that the decoding module referred to in this application can be a logic unit, and the specific structure can refer to the decoding circuit (or called a row address decoder) in an existing memory; similarly, the driving module referred to in this application can refer to the driving circuit in an existing memory, and this application does not limit the specific structure.

[0061] The embodiment of the present application also discloses a memory, which includes the aforementioned row address decoding circuit. Specifically, the memory includes a memory array, each row of the memory array is coupled to a row address decoding circuit, and a large number of row address decoding circuits exist in the memory.

[0062] Since the area of ​​the row address decoding circuit in the embodiment of the present application is relatively small, when the row address decoding circuit is repeatedly called in a large number of times in the memory, the area of ​​the memory can be further reduced, thereby reducing the power consumption of the memory.

[0063] In a specific example, the memory may be an embedded super flash (ESF), which is not limited in the present application.

[0064] The embodiment of the present application further discloses a chip, which includes the aforementioned row address decoding circuit. Alternatively, the chip includes the aforementioned memory.

[0065] As mentioned above, the row address decoding circuit or memory has a small area and consumes little power, which is helpful for designing a low-power chip.

[0066] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0067] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0068] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0069] The "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.

[0070] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means.

[0071] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0072] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0073] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0074] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0075] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute some steps of the method described in each embodiment of the present application.

[0076] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims.

Claims

1. A row address decoding circuit, characterized in that: include: A decoding module, used for decoding the address signal into a row address and outputting a decoding signal; A driving module, used for converting the decoded signal output by the decoding module into a row selection signal; an isolation module, wherein an input end is coupled to an output end of the decoding module, an output end is coupled to an input end of the driving module, the isolation module is disconnected when a power supply voltage of the driving module is higher than a first preset threshold, and the isolation module is turned on when the power supply voltage of the driving module is lower than the first preset threshold; The isolation module comprises: An N-type enhancement type field effect transistor, wherein the drain of the N-type enhancement type field effect transistor is coupled to the output end of the decoding module, the source of the N-type enhancement type field effect transistor is coupled to the input end of the driving module, and the gate of the N-type enhancement type field effect transistor is connected to the isolation control signal; When the power supply voltage of the driving module is higher than the first preset threshold and lower than the second preset threshold, the voltage of the isolation control signal is the first voltage; when the power supply voltage of the driving module is higher than the second preset threshold, the voltage of the isolation control signal is the second voltage and the ground terminal of the driving module is connected to the power supply voltage, the second preset threshold is greater than the first preset threshold, and the second voltage is greater than the first voltage.

2. The row address decoding circuit according to claim 1, characterized in that: The conduction threshold voltage of the N-type enhancement mode field effect transistor is a negative value.

3. The row address decoding circuit according to claim 1, characterized in that: The first voltage is a ground voltage, and the second voltage is between the ground voltage and a power supply voltage.

4. The row address decoding circuit according to claim 1, characterized in that: Also includes: The isolation control module is used to generate an isolation control signal, and the isolation control signal is used to control the on or off of the isolation module.

5. The row address decoding circuit according to claim 4, characterized in that: The isolation control module comprises: A gating unit, wherein a first end of the gating unit is grounded, and a second end of the gating unit is connected to an operating voltage, and is used to selectively output a ground voltage or an operating voltage as the isolation control signal.

6. The row address decoding circuit according to claim 5, characterized in that: The operating voltage is a power supply voltage or a second voltage, and the second voltage is greater than the ground voltage and less than the power supply voltage.

7. The row address decoding circuit according to claim 6, characterized in that: The gating unit comprises: a first switch, wherein a first end of the first switch is connected to the power supply voltage; a second switch, wherein a first end of the second switch is connected to the second voltage; A PMOS tube, a source of the PMOS tube is coupled to the second end of the first switch and the second end of the second switch, and a gate of the PMOS tube is connected to a mode control signal; An NMOS tube, wherein the source of the NMOS tube is grounded, the gate of the NMOS tube is connected to the mode control signal, the drain of the NMOS tube is coupled to the drain of the PMOS tube, and outputs the isolation control signal.

8. A memory, characterized in that: The invention comprises the row address decoding circuit as claimed in any one of claims 1 to 7.

9. A chip, characterized in that: The invention comprises the row address decoding circuit as claimed in any one of claims 1 to 7.

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