Semiconductor structure and preparation method thereof, functional chip and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a functional chip and electronic equipment, and relates to the technical field of semiconductor structures. The preparation method of the semiconductor structure comprises the following steps: providing a semiconductor layer group, wherein the semiconductor layer group comprises a first dielectric layer, a semiconductor layer, a conductive structure and an electronic element; and removing part of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction, and exposing the end face of one side, far away from the electronic element, of the conductive structure. And forming a protection structure on one side, far away from the first dielectric layer, of the conductive structure, and enabling the orthographic projection of the protection structure on the semiconductor layer to cover the orthographic projection of the exposed end surface of the conductive structure on the semiconductor layer. And etching a part of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction by taking the protection structure as a mask. According to the embodiment of the invention, the protection structure is arranged, so that the residual conductive metal particles can be reduced, and the electrical reliability of the semiconductor layer is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of semiconductor structures, and in particular, to a semiconductor structure and a method for preparing the same, a functional chip, and an electronic device. Background Art

[0002] A chip generally includes a semiconductor structure, which may include a semiconductor layer and a conductive structure made of a metal material. In the related art, when preparing a semiconductor structure, the conductive structure may easily cause metal contamination to the semiconductor layer, thereby affecting the electrical reliability of the semiconductor structure. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor structure and a method for preparing the same, a functional chip, and an electronic device for improving the electrical performance of the semiconductor structure.

[0004] In order to achieve the above purpose, the following technical solutions are provided:

[0005] On the one hand, an embodiment of the present application provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure includes providing a semiconductor layer group, the semiconductor layer group includes a first dielectric layer, a semiconductor layer, a conductive structure and an electronic component. The semiconductor layer includes a first surface and a second surface arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer. One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component, and the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer. Along a first direction, a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer to expose the end face of the conductive structure away from the electronic component. The first direction intersects with the surface of the semiconductor layer. A protective structure is formed on the side of the conductive structure away from the first dielectric layer, and the positive projection of the protective structure on the semiconductor layer covers the positive projection of the exposed end face of the conductive structure on the semiconductor layer. Using the protective structure as a mask, a portion of the semiconductor layer is etched from one side of the second surface of the semiconductor layer along the first direction. Remove the protective structure.

[0006] In an embodiment of the present application, a protective structure is formed on a side of the conductive structure away from the first dielectric layer, and the orthographic projection of the protective structure on the semiconductor layer covers the orthographic projection of the exposed end face of the conductive structure (that is, the end face of the conductive structure away from the electronic component) on the semiconductor layer, so that the protective structure can shield and cover the end face of the conductive structure away from the electronic component.

[0007] In this way, the protective structure can be used as a mask. When etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction, the etching ion beam will not bombard the end face of the conductive structure away from the electronic component, thereby reducing the risk of metal particles falling on the second surface of the semiconductor layer due to splashing of the conductive structure under the action of the etching ion beam when etching a portion of the semiconductor layer. This can reduce the residual conductive metal particles, reduce the metal contamination of the semiconductor layer caused by the conductive structure, and improve the electrical reliability of the semiconductor structure.

[0008] Furthermore, after etching a portion of the semiconductor layer, the protective structure is removed to prevent the protective structure from affecting subsequent processing techniques.

[0009] In some possible implementations, the semiconductor layer group further includes a second dielectric layer, and the second dielectric layer covers the conductive structure. Using the protective structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction also includes: etching the first part of the second dielectric layer. The first part of the second dielectric layer covers the outer peripheral side of the conductive structure away from the end of one side of the electronic component, and is away from the conductive structure along the second direction. The second direction is parallel to the surface of the semiconductor layer. Such an arrangement can reduce the risk of the semiconductor layer and the second dielectric layer adhering to each other, causing the semiconductor layer to remain on the surface of the second dielectric layer away from the conductive structure, thereby improving the reliability of the method for preparing the semiconductor structure. In addition, the remaining part of the second dielectric layer (the second part of the second dielectric layer) can protect the outer peripheral side of the conductive structure away from the end of one side of the electronic component. That is, the protection structure can protect the end face of the conductive structure away from the electronic component, and the remaining second dielectric layer can protect the peripheral side of the end of the conductive structure away from the electronic component, thereby preventing the etching ion beam from bombarding the end of the conductive structure away from the electronic component (including the end face and the peripheral side) when etching the semiconductor layer, reducing the metal contamination of the semiconductor layer caused by the conductive structure, and improving the electrical reliability of the semiconductor structure.

[0010] In some possible implementations, the edge of the orthographic projection of the protection structure on the semiconductor layer is located between the orthographic projection of the surface of the second dielectric layer away from the conductive structure on the semiconductor layer and the orthographic projection of the surface of the second dielectric layer close to the conductive structure on the semiconductor layer. With such an arrangement, the protection structure can protect the end surface of the conductive structure away from the electronic component and the second part of the second dielectric layer, and the first part of the second dielectric layer can be etched away, thereby reducing the risk of the semiconductor layer adhering to the second dielectric layer and causing the semiconductor layer to remain on the surface of the second dielectric layer away from the conductive structure, thereby improving the reliability of the method for preparing the semiconductor structure.

[0011] In some possible implementations, forming a protective structure on a side of the conductive structure away from the first dielectric layer includes: forming a photoresist layer on a side of the semiconductor layer away from the first dielectric layer. Patterning the photoresist layer by exposure and development to form the protective structure. With such a configuration, no complicated preparation method is required, and on the basis of improving the electrical performance of the semiconductor structure, the preparation process of the semiconductor structure is simplified, thereby reducing the preparation cost of the semiconductor structure.

[0012] In some implementations, before forming a photoresist layer on the side of the semiconductor layer away from the first dielectric layer, the method includes: forming an isolation layer on one side of the second surface of the semiconductor layer, the isolation layer covering the exposed end faces of the semiconductor layer and the conductive structure. Before etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protective structure as a mask, the method also includes: etching the portion of the semiconductor layer covered by the isolation layer using the protective structure as a mask. With such an arrangement, the isolation layer can isolate the end face of the photoresist layer from the side of the conductive structure away from the electronic component, thereby avoiding contact between the photoresist layer and the end face of the conductive structure away from the electronic component, thereby avoiding contamination of the end face of the conductive structure away from the electronic component by the photoresist layer, and improving the electrical reliability of the semiconductor structure. In addition, before etching a portion of the semiconductor layer, the portion of the semiconductor layer covered by the isolation layer is etched so that the semiconductor layer can be exposed, thereby avoiding the influence of the isolation layer on subsequent processes.

[0013] In some possible implementations, after removing the protective structure, the method further includes: forming a third dielectric layer, the third dielectric layer covering the second surface of the semiconductor layer and encapsulating the end of the conductive structure protruding from the semiconductor layer. A portion of the third dielectric layer and the isolation layer are removed along the first direction to expose the end face of the conductive structure away from the electronic component. In this way, the end face of the conductive structure away from the electronic component can be exposed, so that other components (such as external components or other semiconductor structures) can be electrically connected to the semiconductor structure through the conductive structure. In addition, the third dielectric layer can play a role of electrical isolation, thereby improving the reliability of the semiconductor structure when electrically connected to other components.

[0014] In some possible implementations, the number of conductive structures is multiple, and the multiple conductive structures include a first conductive structure and a second conductive structure. Before removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction to expose the end face of the conductive structure away from the electronic component, the distance between the end face of the first conductive structure away from the electronic component and the second surface of the semiconductor layer is not equal to the distance between the end face of the second conductive structure away from the electronic component and the second surface of the semiconductor layer. Removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction to expose the end face of the conductive structure away from the electronic component includes: removing a portion of the semiconductor layer and a portion of the conductive structure from one side of the second surface of the semiconductor layer along the first direction to expose the end face of the first conductive structure and the second conductive structure away from the electronic component. The end face exposed by the first conductive structure is flush with the end face exposed by the second conductive structure. Such an arrangement enables other external components to be electrically connected to the first conductive structure and the second conductive structure, and enables different semiconductor structures to be electrically connected through the first conductive structure and the second conductive structure to meet different needs. In addition, the exposed end surface of the first conductive structure is flush with the exposed end surface of the second conductive structure, which can improve the structural regularity of the semiconductor structure and improve the processing convenience of the semiconductor structure in subsequent processes.

[0015] On the other hand, an embodiment of the present application provides a semiconductor structure. The semiconductor structure includes a semiconductor layer group and a third dielectric layer. The semiconductor layer group includes a first dielectric layer, a semiconductor layer, a second dielectric layer, a conductive structure and an electronic component. The semiconductor layer includes a first surface and a second surface arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer. One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component. The second dielectric layer covers the conductive structure. The third dielectric layer is arranged adjacent to the second surface of the semiconductor layer. One end of the conductive structure away from the electronic component passes through the semiconductor layer and the third dielectric layer, and the end face of the conductive structure away from the electronic component is exposed to the third dielectric layer. Among them, the second dielectric layer includes a first sub-section and a second sub-section, the first sub-section is located between the third dielectric layer and the conductive structure, and the second sub-section is located between the semiconductor layer and the conductive structure. The thickness of the first sub-section is less than the thickness of the second sub-section. In this way, the risk of the surface of the first sub-section away from the conductive structure adhering to the semiconductor layer can be reduced, and the electrical reliability of the semiconductor structure is improved.

[0016] In another aspect, an embodiment of the present application provides a functional chip, the functional chip comprising at least one semiconductor structure. The semiconductor structure is the semiconductor structure described above; or the semiconductor structure is manufactured according to the method for manufacturing the semiconductor structure described above.

[0017] The functional chip provided in the embodiments of the present application includes the semiconductor structure as described above; or, the semiconductor structure in the functional chip provided in the embodiments of the present application is manufactured according to the preparation method of the semiconductor structure as described above; therefore, the functional chip provided in the embodiments of the present application has all the above-mentioned beneficial effects, which will not be repeated here.

[0018] In some possible implementations, when the functional chip includes at least two semiconductor structures, the at least two semiconductor structures include a first semiconductor structure and a second semiconductor structure. The exposed end surface of the conductive structure in the first semiconductor structure is bonded to the exposed end surface of the conductive structure in the second semiconductor structure. In this way, when the first semiconductor structure and the second semiconductor structure are stacked, the electronic components in the first semiconductor structure can be electrically connected to the electronic components in the second semiconductor structure, thereby realizing interlayer interconnection of the bonded wafer, so that the functional chip can become a 3D IC.

[0019] In another aspect, an embodiment of the present application provides an electronic device, which includes a bus and the above-mentioned function chip, wherein the function chip is electrically connected to the bus.

[0020] The electronic device provided by the embodiment of the present application includes the functional chip as described above, and therefore has all the above-mentioned beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic block diagram of the structure of an electronic device provided in some embodiments of the present application;

[0022] Figure 2 A flowchart of the steps of a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0023] Figure 3 A schematic diagram of the structure of a semiconductor layer group provided in some embodiments of the present application;

[0024] Figure 4 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0025] Figure 5 Electron microscope images of semiconductor structures provided for some embodiments of the present application;

[0026] Figure 6 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0027] Figure 7 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0028] Figure 8 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0029] Fig. 9 Electron microscope images of conductive structures provided for some embodiments of the present application;

[0030] Fig.10 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0031] Fig.11 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0032] Fig.12 A schematic diagram of the structure of a functional chip provided in some embodiments of the present application;

[0033] Fig.13 for Fig. 9 A partial magnified image of the middle M1 region;

[0034] Fig.14 Schematic diagram of the curve of the effective diffusion coefficient of copper changing with temperature;

[0035] Fig.15 It is a schematic diagram of the diffusion depth curve of different metals in the same medium;

[0036] Fig.16 A flowchart of steps of a method for preparing a semiconductor structure provided in some other embodiments of the present application;

[0037] Fig.17 Schematic diagrams of the structures of semiconductor layer groups in some other embodiments of the present application;

[0038] Fig.18 Schematic diagrams of the structures of semiconductor layer groups in some other embodiments of the present application;

[0039] Fig.19 Schematic diagrams of the structures of semiconductor layer groups in some other embodiments of the present application;

[0040] Fig. 20 for Fig.19 A partial magnified image of the middle M2 region;

[0041] Fig.21 A positional relationship diagram of an edge of an orthographic projection of a protection structure on a semiconductor layer and an orthographic projection of a second dielectric layer on the semiconductor layer provided in some embodiments of the present application;

[0042] Fig. 22 A flowchart of steps of a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0043] Fig.23 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0044] Fig.24 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0045] Fig.25 A schematic diagram of the structure of a semiconductor layer group provided in some other embodiments of the present application;

[0046] Fig.26 A schematic diagram of the structure of a semiconductor structure provided for some embodiments of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0048] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0049] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0050] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0053] Figure 1 A schematic block diagram of the structure of an electronic device provided for some embodiments of the present application.

[0054] like Figure 1 As shown, an embodiment of the present application provides an electronic device 300. For example, the electronic device 300 may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, etc.; the electronic device 300 may also be a personal computer (English full name: Personal Computer, English abbreviation: PC), a server, a workstation, etc.

[0055] In some examples, such as Figure 1 As shown, the electronic device 300 may include a bus 301 and a function chip 200 , and the function chip 200 may be electrically connected to the bus 301 .

[0056] It can be understood that the bus 301 is a common communication trunk for transmitting information between different functional components of the electronic device 300. The function chip 200 is electrically connected to the bus 301 so that signals can be transmitted between the function chip 200 and the bus 301. Figure 1 As shown, the electronic device 300 may also include other functional components 302, which are electrically connected to the bus 301. In this way, signals can be transmitted between the functional chip 200 and other functional components 302 through the bus 301, so that the electronic device 300 can achieve different functions.

[0057] In some examples, the function chip 200 can implement at least one of a storage function and a computing function, and in other examples, the function chip 200 can also implement functions other than the storage function and the computing function. It can be understood that the embodiments of the present application do not further limit the functions that the function chip 200 can implement.

[0058] In some examples, the function chip 200 may be a 3D IC (full name in English: Three-Dimensional Integrated Circuit, Chinese name: three-dimensional integrated circuit). For example, the function chip 200 may be at least one of an application processor (full name in English: Application Processor, English abbreviation: AP), a graphics processing unit (full name in English: Graphics Processing Unit, English abbreviation: GPU), a central processing unit (full name in English: Central Processing Unit, English abbreviation: CPU), a random access memory (full name in English: Random Access Memory, English abbreviation: RAM), a read-only memory (full name in English: Read Only Memory, English abbreviation: ROM), a communication chip, and a power management chip. The electronic device 300 may include one function chip 200, or may include multiple function chips 200.

[0059] In some examples, the function chip 200 may include at least one semiconductor structure 100 . For example, the function chip 200 may include only one semiconductor structure 100 ; the function chip 200 may also include two, three, four or more semiconductor structures 100 .

[0060] When the function chip 200 includes a plurality of semiconductor structures 100, at least two semiconductor structures 100 among the plurality of semiconductor structures 100 may be electrically connected. For example, the at least two semiconductor structures 100 may be electrically connected by bonding. Compared with electrically connecting at least two semiconductor structures 100 by wires, electrically connecting at least two semiconductor structures 100 by bonding reduces the routing complexity of the function chip 200 and can shorten the distance between the at least two electrically connected semiconductor structures 100.

[0061] Figure 2 A flow chart of the steps of a method for preparing a semiconductor structure provided in some embodiments of the present application. Figure 3 A schematic structural diagram of a semiconductor layer group provided in some embodiments of the present application. Figure 4 Schematic diagram of the structure of semiconductor layer groups provided in other embodiments of the present application. Figure 5Electron microscope images of semiconductor structures provided for some embodiments of the present application.

[0062] The following is an example of a method for preparing the semiconductor structure 100. In some examples, such as Figure 2 As shown, the method for preparing the semiconductor structure 100 includes:

[0063] Step S101, providing a semiconductor layer group, the semiconductor layer group includes a first dielectric layer, a semiconductor layer, a conductive structure and an electronic component. The semiconductor layer includes a first surface and a second surface arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer. One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component, and the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer.

[0064] For example, Figure 3 As shown, the semiconductor layer group 110 may include a first dielectric layer 111, a semiconductor layer 112, a conductive structure 113, and an electronic component 114. The material of the first dielectric layer 111 may be an oxide (English name: oxide), such as silicon dioxide (chemical formula: SiO2); or, the material of the first dielectric layer 111 may also be a nitride (English name: nitrides), such as silicon nitride (chemical formula: SiN); or, the material of the first dielectric layer 111 may also be a combination of one or more other high dielectric constant insulating materials.

[0065] For example, the first dielectric layer 111 may include a plurality of stacked sub-layers (see Figure 3 ), the electronic component 114 may be located in a plurality of stacked sub-layers. The materials of different sub-layers may be the same or different.

[0066] In some examples, the material of semiconductor layer 112 may include silicon (chemical formula: Si). For example, semiconductor layer 112 may be pure silicon or doped silicon.

[0067] like Figure 3 and Figure 4 As shown, the semiconductor layer 112 may include a first surface P1 and a second surface P2 that are arranged opposite to each other, and the first surface P1 and the second surface P2 may be smooth planes. The first dielectric layer 111 is located on one side of the first surface P1 of the semiconductor layer 112 and is arranged adjacent to the first surface P1. For example, the first dielectric layer 111 may contact the first surface P1 of the semiconductor layer 112.

[0068] It is understandable that the electronic component 114 may be a component having functions of storage, calculation, switching, digital-to-analog conversion, analog-to-digital conversion, etc. There may be multiple electronic components 114, and the functions of the multiple electronic components 114 may be the same or different.

[0069] like Figure 3 and Figure 4 As shown, one end of the conductive structure 113 is located in the first dielectric layer 111 and is electrically connected to the electronic component 114, so that a signal can be transmitted between the electronic component 114 and the conductive structure 113. It can be understood that the conductive structure 113 and the electronic component 114 can be directly electrically connected, or the conductive structure 113 and the electronic component 114 can be connected through other conductive traces (such as conductive traces and metal interconnect structures, Figure 3 and Figure 4 (not shown) and other structures are electrically connected.

[0070] In some examples, the conductive structures 113 and the electronic components 114 may be electrically connected in a one-to-one correspondence; in other examples, one conductive structure 113 may be electrically connected to multiple electronic components 114; or, multiple conductive structures 113 may be electrically connected to one electronic component 114.

[0071] like Figure 3 and Figure 4 As shown, the extension direction of the conductive structure 113 may intersect with the surface of the semiconductor layer 112 (including the first surface P1 and the second surface P2), so that the other end of the conductive structure 113 can pass through the first surface P1 of the semiconductor layer 112 and extend into the semiconductor layer 112. For example, the extension direction of the conductive structure 113 may be perpendicular to the surface of the semiconductor layer 112.

[0072] In some examples, the conductive structure 113 may be formed by TSV (Through Silicon Via, Chinese name: Through Silicon Via) technology. For example, a conductive via may be formed on the semiconductor layer 112 via the first surface P1 of the semiconductor layer 112, and the conductive structure 113 may be formed in the conductive via. The material of the conductive structure 113 may be a metal material such as copper, aluminum, iron, silver, etc., to improve the conductive performance of the conductive structure 113. It is understandable that the embodiment of the present application does not further limit the material of the conductive structure 113.

[0073] Figure 5 1 is a schematic cross-sectional view of the conductive structure 113 along a direction perpendicular to the surface (eg, the first surface P1 or the second surface P2) of the semiconductor layer 112. It can be understood that in order to clearly illustrate the conductive structure 113, Figure 5 Other structures of the semiconductor layer group 110 are not shown.

[0074] In some examples, the conductive structure 113 may be in the shape of a cylinder, a cuboid, or a prism, so that the cross-sectional shape of the conductive structure 113 along a direction perpendicular to the surface of the semiconductor layer 112 may be a rectangle. In other examples, the conductive structure 113 may also be in other irregular shapes.

[0075] Taking the shape of the conductive structure 113 as a cylinder as an example, in some examples, the bottom diameter of the cylinder can be 5 μm (unit: micrometer), and the height of the cylinder can be 50 μm. In other examples, the conductive structure 113 can also be of other sizes. It can be understood that the embodiment of the present application does not further limit the shape and size of the conductive structure 113.

[0076] In some examples, such as Figure 3 and Figure 4 As shown, the semiconductor layer group 110 may further include a second dielectric layer 115 , and the second dielectric layer 115 covers the conductive structure 113 .

[0077] For example, the second dielectric layer 115 can be located in the semiconductor layer 112 and cover the conductive structure 113. It can be understood that the second dielectric layer 115 can play a role of electrical isolation. For example, the material of the second dielectric layer 115 can be an oxide (English name: oxide), such as silicon dioxide (chemical formula: SiO2); or, the material of the second dielectric layer 115 can also be a nitride (English name: nitrides), such as silicon nitride (chemical formula: SiN); or, the material of the second dielectric layer 115 can also be a combination of one or more other high dielectric constant insulating materials. The material of the second dielectric layer 115 can be the same as or different from the material of the first dielectric layer 111.

[0078] For example, after forming a conductive through hole on the semiconductor layer 112 , a second dielectric layer 115 may be formed on the inner wall of the conductive through hole, and then a conductive structure 113 may be formed on a side of the second dielectric layer 115 away from the semiconductor layer 112 , so that the second dielectric layer 115 can cover the conductive structure 113 .

[0079] Figure 6 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application. Figure 7 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application.

[0080] See again Figure 2 After providing the semiconductor layer group 110 (that is, after step S101), the method for preparing the semiconductor structure 100 further includes:

[0081] Step S102, removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along a first direction to expose an end face of the conductive structure away from the electronic component. The first direction intersects with the surface of the semiconductor layer.

[0082] In some examples, the first direction X may be perpendicular to the surface of the semiconductor layer 112 (including the first surface P1 and the second surface P2 ).

[0083] It can be understood that, since the end of the conductive structure 113 away from the electronic element 114 passes through the first surface P1 of the semiconductor layer 112 and extends into the semiconductor layer 112, a portion of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, as shown in FIG. Figure 6 and Figure 7 As shown, the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. For example, the exposed end surface of the conductive structure 113 is flush with the second surface P2 of the semiconductor layer 112.

[0084] For example, the process of removing part of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112 along the first direction X to expose the end surface of the conductive structure 113 away from the electronic component 114 is called back side via revealing process (full name: Backside Via Reveal, abbreviated in English: BVR).

[0085] It can be understood that the BVR process is used to expose the end face of the conductive structure 113 away from the electronic component 114, so that other external components can be electrically connected to the electronic component 114 through the conductive structure 113, or two different semiconductor structures 100 can be electrically connected through the conductive structure 113, thereby improving the electrical reliability of the semiconductor structure 100 in subsequent processing technology.

[0086] In some examples, a CMP (full name in English: Chemical Mechanical Polishing, Chinese name: Chemical Mechanical Polishing) process can be used to thin the semiconductor layer 112 from an initial thickness (e.g., 75 μm) to a set thickness to expose the end surface of the conductive structure 113 away from the electronic component 114. It can be understood that the use of the CMP process to remove part of the semiconductor layer 112 can not only expose the end surface of the conductive structure 113 away from the electronic component 114, but also polish and planarize the second surface P2 of the semiconductor layer 112 and the end surface of the conductive structure 113 away from the electronic component 114, thereby improving the structural regularity of the semiconductor structure 100.

[0087] It can be understood that when part of the semiconductor layer 112 is not removed, the second surface P2 is a surface disposed opposite to the first surface P1. After part of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, the second surface P2 is a surface of the remaining semiconductor layer 112 disposed opposite to the first surface P1.

[0088] For example, while removing a portion of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112, the second dielectric layer 115 covering the end surface of the conductive structure 113 away from the electronic component 114 can be removed. Figure 6 and Figure 7 As shown, the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. It can be understood that in the embodiment of the present application, "simultaneously" refers to the same step or the same process, and is not limited to the same time.

[0089] In some examples, such as Figure 3 and Figure 4 As shown, before removing a portion of the semiconductor layer 112, a carrier wafer 118 may be provided, and the carrier wafer 118 is located on a side of the first dielectric layer 111 away from the semiconductor layer 112. The carrier wafer 118 may be bonded to the first dielectric layer 111 by a bonding adhesive or other material. It can be understood that the carrier wafer 118 can play a role of bearing support, thereby reducing the risk of the semiconductor layer group 110 being broken when removing a portion of the semiconductor layer 112.

[0090] In some other examples, the semiconductor layer group 110 may further include a functional film layer (not shown in the figure), and the functional film layer may be located on a side of the first dielectric layer 111 away from the semiconductor layer 112. It can be understood that the functional film layer can play a role of bearing and supporting the first dielectric layer 111 and the semiconductor layer 112, and in this case, there is no need to provide a carrier 118, which simplifies the preparation process of the semiconductor structure 100.

[0091] In some examples, after providing the semiconductor layer group 110, the semiconductor layer group 110 may be turned over so that the second surface P2 of the semiconductor layer 112 faces upward (toward the sky side, see Figure 4 ), which improves the convenience of removing part of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112.

[0092] In some examples, such as Figure 6 and Figure 7 As shown, there may be a plurality of conductive structures 113. The number of conductive structures 113 may be the same as or different from the number of electronic components 114. The plurality of conductive structures 113 may be arranged in an array.

[0093] In some examples, such as Figure 4 As shown, the plurality of conductive structures 113 may include a first conductive structure 113a and a second conductive structure 113b. Before a portion of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X to expose the end surface of the conductive structure 113 away from the electronic component 114, the distance L1 between the end surface of the first conductive structure 113a away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 is not equal to the distance L2 between the end surface of the second conductive structure 113b away from the electronic component 114 and the second surface P2 of the semiconductor layer 112.

[0094] It is understandable that there may be a plurality of first conductive structures 113a, a plurality of second conductive structures 113b, or the same or different number of first conductive structures 113a and second conductive structures 113b.

[0095] like Figure 4 As shown, before a portion of the semiconductor layer 112 is removed to expose the end surface of the conductive structure 113 away from the electronic component 114, the distance L1 between the end surface of the first conductive structure 113a away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 is not equal to the distance L2 between the end surface of the second conductive structure 113b away from the electronic component 114 and the second surface P2 of the semiconductor layer 112, that is, the length of the portion of the first conductive structure 113a located in the semiconductor layer 112 along the first direction X is not equal to the length of the portion of the second conductive structure 113b located in the semiconductor layer 112 along the first direction X.

[0096] In some examples, such as Figure 4 As shown, the distance L1 between the end surface of the first conductive structure 113a away from the side of the electronic component 114 and the second surface P2 of the semiconductor layer 112 may be greater than the distance L2 between the end surface of the second conductive structure 113b away from the side of the electronic component 114 and the second surface P2 of the semiconductor layer 112; in other examples, the distance L1 between the end surface of the first conductive structure 113a away from the side of the electronic component 114 and the second surface P2 of the semiconductor layer 112 may also be less than the distance L2 between the end surface of the second conductive structure 113b away from the side of the electronic component 114 and the second surface P2 of the semiconductor layer 112.

[0097] It can be understood that by removing a portion of the semiconductor layer 112 from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, an end surface of a conductive structure 113 (for example, a second conductive structure 113b) away from the electronic component 114 can be exposed, and end surfaces of multiple conductive structures 113 (for example, a first conductive structure 113a and a second conductive structure 113b) away from the electronic component 114 can also be exposed.

[0098] For example, in step S102, a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer along the first direction to expose an end surface of the conductive structure away from the electronic component, including:

[0099] Along the first direction, part of the semiconductor layer and part of the conductive structure are removed from one side of the second surface of the semiconductor layer to expose the end faces of the first conductive structure and the second conductive structure away from the electronic component; wherein the exposed end face of the first conductive structure is flush with the exposed end face of the second conductive structure.

[0100] It can be understood that, since the distance L1 between the end surface of the first conductive structure 113a away from the electronic component 114 and the second surface P2 of the semiconductor layer 112 is not equal to the distance L2 between the end surface of the second conductive structure 113b away from the electronic component 114 and the second surface P2 of the semiconductor layer 112, a portion of the semiconductor layer 112 and a portion of the conductive structure 113 (for example, the second conductive structure 113b) along the first direction X can be removed from one side of the second surface P2 of the semiconductor layer 112, such as Figure 7 As shown, the end surface of the first conductive structure 113a away from the electronic component 114 and the end surface of the second conductive structure 113b away from the electronic component 114 are both exposed.

[0101] It can be understood that the end face of the first conductive structure 113a away from the electronic component 114 and the end face of the second conductive structure 113b away from the electronic component 114 can be exposed, so that other external components can be electrically connected to the first conductive structure 113a and the second conductive structure 113b, and different semiconductor structures 100 can be electrically connected through the first conductive structure 113a and the second conductive structure 113b to meet different needs.

[0102] In addition, the exposed end surface of the first conductive structure 113 a is flush with the exposed end surface of the second conductive structure 113 b , which can improve the structural regularity of the semiconductor structure 100 and improve the processing convenience of the semiconductor structure 100 in subsequent processes.

[0103] In some examples, such as Figure 6 and Figure 7 As shown, the end surfaces of the plurality of conductive structures 113 away from the electronic component 114 are flush with each other, and the end surfaces of the plurality of conductive structures 113 away from the electronic component 114 are all flush with the second surface P2 of the semiconductor layer 112 .

[0104] Figure 8 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application. Fig. 9Electron microscope images of conductive structures provided for some embodiments of the present application. Fig.10 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application. Fig.11 The schematic diagram of the structure of the semiconductor layer group provided by some embodiments of the present application. It can be understood that: Fig. 9 FIG. 4 is an electron microscope image of the semiconductor layer 112 observed from the second surface P2 side of the semiconductor layer 112 .

[0105] See again Figure 2 After the end surface of the conductive structure 113 is exposed (that is, after step S102), the method for preparing the semiconductor structure 100 further includes:

[0106] Step S103 , etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction.

[0107] like Figure 8 As shown, after the end surface of the conductive structure 113 is exposed, a portion of the semiconductor layer 112 may be etched from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, as shown in FIG. Figure 8 and Fig. 9 As shown, the end of the conductive structure 113 away from the electronic component 114 may protrude from the semiconductor layer 112 .

[0108] For example, a dry etching process may be used to etch a portion of the semiconductor layer 112 along the first direction X from one side of the second surface P2 of the semiconductor layer 112 ; a wet etching process may also be used to etch a portion of the semiconductor layer 112 along the first direction X from one side of the second surface P2 of the semiconductor layer 112 .

[0109] Understandably, if Figure 8 As shown, since the second dielectric layer 115 covers the conductive structure 113 , when the semiconductor layer 112 is etched so that the end of the conductive structure 113 away from the electronic component 114 protrudes from the semiconductor layer 112 , the portion of the second dielectric layer 115 away from the electronic component 114 can also protrude from the semiconductor layer 112 .

[0110] Step S104 , forming a third dielectric layer, wherein the third dielectric layer covers the second surface of the semiconductor layer and wraps the end of the conductive structure protruding from the semiconductor layer.

[0111] like Fig.10 As shown, after the end of the conductive structure 113 protrudes from the semiconductor layer 112 , a third dielectric layer 116 may be formed to cover the second surface P2 of the semiconductor layer 112 and the end of the conductive structure 113 protruding from the semiconductor layer 112 .

[0112] It can be understood that the third dielectric layer 116 can play a role of electrical isolation. For example, the material of the third dielectric layer 116 can be an oxide (English name: oxide), such as silicon dioxide (chemical formula: SiO2); or, the material of the third dielectric layer 116 can also be a nitride (English name: nitrides), such as silicon nitride (chemical formula: SiN); or, the material of the third dielectric layer 116 can also be a combination of one or more other high dielectric constant insulating materials. The materials of the first dielectric layer 111, the second dielectric layer 115, and the third dielectric layer 116 can be the same or different.

[0113] Step S105 , removing a portion of the third dielectric layer along the first direction to expose the end surface of the conductive structure away from the electronic component.

[0114] like Fig.11 As shown, after the third dielectric layer 116 is formed, a portion of the third dielectric layer 116 may be removed along the first direction X, so that the end surface of the conductive structure 113 away from the electronic component 114 can be exposed.

[0115] In some examples, a portion of the third dielectric layer 116 may be removed by a CMP process, so that the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. For example, when removing a portion of the third dielectric layer 116, a portion of the conductive structure 113 along the first direction X may be removed, so as to polish and planarize the surface of the third dielectric layer 116 away from the semiconductor layer 112 and the end surface of the conductive structure 113 away from the electronic component 114, thereby improving the structural regularity of the semiconductor structure 100.

[0116] It can be understood that the third dielectric layer 116 can play a role of electrical isolation, thereby improving the reliability of the semiconductor structure 100 when it is electrically connected to other components (such as external components or other semiconductor structures 100 ).

[0117] Fig.12 A schematic diagram of the structure of a functional chip provided in some embodiments of the present application.

[0118] In other examples, such as Fig.12 As shown, when the functional chip 200 includes at least two semiconductor structures 100, the at least two semiconductor structures 100 may include a first semiconductor structure 100a and a second semiconductor structure 100b. The exposed end surface of the conductive structure 113 in the first semiconductor structure 100a may be bonded to the exposed end surface of the conductive structure 113 in the second semiconductor structure 100b.

[0119] It can be understood that the first semiconductor structure 100a and the second semiconductor structure 100b may be the same or different. The function that the first semiconductor structure 100a can achieve may be the same or different from the function that the second semiconductor structure 100b can achieve.

[0120] In some examples, such as Fig.12 As shown, the electronic element 114 in the semiconductor structure 100 (e.g., the first semiconductor structure 100a or the second semiconductor structure 100b) can be electrically connected to the conductive structure 113 through the conductive trace 141 and the metal interconnect structure 142. For example, the conductive trace 141, the metal interconnect structure 142, and the conductive structure 113 are made of the same material; in other examples, the conductive trace 141, the metal interconnect structure 142, and the conductive structure 113 can also be made of different materials.

[0121] In some examples, the semiconductor structure 100 (e.g., the second semiconductor structure 100b) may further include a buried oxide layer (full name in English: Burried Oxide, English abbreviation BOX) 117. The buried oxide layer 117 may be located between the first dielectric layer 111 and the semiconductor layer 112 to perform electrical isolation. For example, the material of the buried oxide layer 117 may include silicon dioxide.

[0122] It can be understood that the exposed end face of the conductive structure 113 in the first semiconductor structure 100a (that is, the end face of the conductive structure 113 in the first semiconductor structure 100a away from the electronic component 114) is bonded to the exposed end face of the conductive structure 113 in the second semiconductor structure 100b (that is, the end face of the conductive structure 113 in the second semiconductor structure 100b away from the electronic component 114), so that when the first semiconductor structure 100a and the second semiconductor structure 100b are stacked, the electronic component 114 in the first semiconductor structure 100a can be electrically connected to the electronic component 114 in the second semiconductor structure 100b, thereby realizing interlayer interconnection of the bonded wafers, so that the functional chip 200 can become a 3D IC.

[0123] Fig.13 for Fig. 9 A partial enlarged view of the middle M1 region.

[0124] The inventor of the present application has found that the above implementation method has at least the following technical problems:

[0125] In the related art, when the conductive structure 113 is formed by the TSV process, it can be divided into Via-First (Chinese name: first through hole), Via-Middle (Chinese name: middle through hole) and Via-Last (last through hole) according to different process sequences.

[0126] Via-First refers to the formation of the conductive structure 113 before the front-end process (full name in English: Front End Of The Line, English abbreviation: FEOL); Via-Middle refers to the formation of the conductive structure 113 after the front-end process and before the back-end process (full name in English: Back End Of The Line, English abbreviation: BEOL); Via-Last refers to the formation of the conductive structure 113 after the back-end process.

[0127] Among the above three methods, Via-First and Via-Middle are more common. However, no matter whether the Via-First process or the Via-Middle process is adopted, a part of the semiconductor layer 112 is removed from one side of the second surface P2 of the semiconductor layer 112 along the first direction X, so that the end surface of the conductive structure 113 away from the electronic component 114 is exposed, and then a part of the semiconductor layer 112 is etched (see Figure 2 Steps S102 and S103 in FIG.

[0128] In this way, when etching a portion of the semiconductor layer 112, the end surface of the conductive structure 113 away from the electronic component 114 will be exposed, so that the etching ion beam will directly bombard the exposed end surface of the conductive structure 113. Under the bombardment of the ion beam, the conductive structure 113 will splash out metal particles, which will fall on the second surface P2 of the semiconductor layer 112.

[0129] For example, when the conductive structure 113 is made of copper and the semiconductor layer 112 is made of silicon, the etching ion beam will directly bombard the copper surface. Under the bombardment of the ion beam, copper particles 113c will be splashed out of the conductive structure 113. Fig.13 As shown, the copper particles 113c fall onto the second surface P2 of the semiconductor layer 112, causing a serious copper contamination problem (full name: Cu Contamination Issue) to the semiconductor layer 112. The subsequent cleaning process is difficult to remove the copper contamination of the semiconductor layer 112, and the copper particles 113c are easy to diffuse in the semiconductor layer 112, affecting the electrical reliability of the semiconductor structure 100.

[0130] Fig.14 Schematic diagram of the curve showing the effective diffusion coefficient of copper changing with temperature. Fig.15 Schematic diagram of the diffusion depth curve of different metals in the same medium.

[0131] Fig.14 In the figure, the vertical axis is the effective diffusion coefficient of copper (full name in English: Effective Copper Diffusion Coefficient), which can be the effective diffusion coefficient of copper in silicon, with a unit of square meters per second (cm2 / s); the horizontal axis is temperature, the unit is 1000 / T(K -1 ); Different curves represent different experimental data.

[0132] from Fig.14 It can be seen that the effective diffusion coefficient of copper atoms in silicon is different at different temperatures. However, at each temperature, the migration coefficient (effective diffusion coefficient) of copper atoms in silicon is high.

[0133] Table 1

[0134]

[0135]

[0136] Table 1 shows the self-diffusion coefficient D, frequency factor D0 and activation energy Q of different metals in silicon at the same temperature (300K, unit: Kelvin).

[0137] As can be seen from Table 1, compared with other metal elements, copper has a higher self-diffusion coefficient D in silicon. Taking the temperature condition of 300K as an example, the self-diffusion coefficient of copper in silicon is as high as 1.4x10 -41 cm 2 / s, which is more than ten orders of magnitude higher than other common metals such as Co, Ni, Pt, etc.

[0138] Fig.15 Depth distribution of Ru, Pb and Cu in silicon after annealing at 400°C (unit: degrees Celsius) in a nitrogen environment for 1 hour. Fig.15 In the graph, the ordinate is the metal concentration (English: Metallic concentration), the unit is atoms / cubic centimeter (atoma / cm3); the abscissa is the depth (English: Depth), the unit is nanometers (nm); different curves represent different metals.

[0139] from Fig.15 It can be seen that under the same pollution concentration (metal concentration), the diffusion depth of copper is much higher than that of other metals (Ru and Pb).

[0140] It can be seen from the above data that after the copper particles fall onto the second surface P2 of the semiconductor layer 112 , they will quickly diffuse in the semiconductor layer 112 , affecting the electrical reliability of the semiconductor structure 100 .

[0141] Fig.16 A flow chart of the steps of a method for preparing a semiconductor structure provided in some other embodiments of the present application. Fig.17 Schematic diagrams of the structures of semiconductor layer groups according to some other embodiments of the present application. Fig.18Schematic diagrams of the structures of semiconductor layer groups according to some other embodiments of the present application. Fig.19 Schematic diagrams of the structures of semiconductor layer groups according to some other embodiments of the present application. Fig. 20 for Fig.19 A partial enlarged view of the middle M2 area.

[0142] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure.

[0143] like Fig.16 As shown, the method for preparing the semiconductor structure includes:

[0144] Step S201, providing a semiconductor layer group, the semiconductor layer group includes a first dielectric layer, a semiconductor layer, a conductive structure and an electronic component. The semiconductor layer includes a first surface and a second surface arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer. One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component, and the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer.

[0145] Step S202, along a first direction, a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer to expose an end face of the conductive structure away from the electronic component. The first direction intersects with the surface of the semiconductor layer.

[0146] It can be understood that step S201 is the same as step S101, and step S202 is the same as step S102. The above embodiments of the present application have provided examples for step S101 and step S102, which will not be repeated here.

[0147] Step S203 , forming a protection structure on a side of the conductive structure away from the first dielectric layer, wherein the orthographic projection of the protection structure on the semiconductor layer covers the orthographic projection of the exposed end surface of the conductive structure on the semiconductor layer.

[0148] It can be understood that the protection structure 121 is located on the side of the conductive structure 113 away from the first dielectric layer 111, and the orthographic projection of the protection structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end face of the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114) on the semiconductor layer 112, so that the protection structure 121 can shield and cover the end face of the conductive structure 113 away from the electronic component 114.

[0149] In some examples, the orthographic projection of the protective structure 121 on the semiconductor layer 112 may completely cover the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112 ; in other examples, the orthographic projection of the protective structure 121 on the semiconductor layer 112 may also partially cover the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112 .

[0150] In some examples, the orthographic projection of the protection structure 121 on the semiconductor layer 112 is aligned with the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112 (Overlay, OVL), and the distance between the center of the orthographic projection of the protection structure 121 on the semiconductor layer 112 and the center of the orthographic projection of the conductive structure 113 on the semiconductor layer 112 is less than 100 nm. Such a configuration can reduce the deviation between the orthographic projection of the protection structure 121 on the semiconductor layer 112 and the orthographic projection of the exposed end surface of the conductive structure 113 on the semiconductor layer 112, thereby improving the reliability of the method for preparing the semiconductor structure 100.

[0151] For example, the shape of the protection structure 121 may be a cylinder, a frustum, a cone, a prism, a prism, a cuboid, a cube or other irregular shapes, etc. The embodiment of the present application does not further limit the shape of the protection structure 121 .

[0152] For example, when the shape of the protective structure 121 is a cylinder, the shape of the orthographic projection of the cylinder on the semiconductor layer 112 is the shape of the orthographic projection of the bottom surface of the cylinder on the semiconductor layer 112. When the shape of the protective structure 121 is a truncated cone, the shape of the orthographic projection of the truncated cone on the semiconductor layer 112 is the shape of the orthographic projection of the lower bottom surface of the truncated cone on the semiconductor layer 112. The upper bottom surface of the truncated cone is parallel to the lower bottom surface, and the area of ​​the upper bottom surface is smaller than the area of ​​the lower bottom surface. When the shape of the protective structure 121 is a cone, the shape of the orthographic projection of the cone on the semiconductor layer 112 is the shape of the orthographic projection of the bottom surface of the cone on the semiconductor layer 112.

[0153] It can be understood that the shape of the orthographic projection of the protection structure 121 on the semiconductor layer 112 may be the same as or different from the shape of the orthographic projection of the end surface of the conductive structure 113 on the side away from the electronic component 114 on the semiconductor layer 112. In some examples, the shape of the orthographic projection of the protection structure 121 on the semiconductor layer 112 and the shape of the orthographic projection of the end surface of the conductive structure 113 on the side away from the electronic component 114 on the semiconductor layer 112 are both circular.

[0154] In some examples, the number of protection structures 121 is the same as the number of conductive structures 113, and the orthographic projection of one protection structure 121 on the semiconductor layer 112 covers the orthographic projection of an exposed end surface of one conductive structure 113 on the semiconductor layer 112. In other examples, the number of protection structures 121 may also be less than the number of conductive structures 113, and the orthographic projection of one protection structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end surfaces of at least two conductive structures 113 on the semiconductor layer 112.

[0155] In some examples, such as Fig.17 As shown, other film layers (such as an isolation layer 131 ) may be disposed between the protection structure 121 and the exposed end surface of the conductive structure 113 ; in other examples, the protection structure 121 and the exposed end surface of the conductive structure 113 may also be disposed adjacent to each other.

[0156] See again Fig.16 After step S203, the method for preparing the semiconductor structure further includes:

[0157] Step S204 , using the protection structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction.

[0158] It can be understood that since the protective structure 121 has an orthographic projection on the semiconductor layer 112 and covers the orthographic projection of the end face of the conductive structure 113 away from the electronic component 114 on the semiconductor layer 112 , the protective structure 121 can protect the exposed end face of the conductive structure 113 .

[0159] For example, a dry etching process may be used to etch a portion of the semiconductor layer 112 ; a wet etching process may also be used to etch a portion of the semiconductor layer 112 .

[0160] By using the protection structure 121 as a mask, when etching the semiconductor layer 112, the end face of the conductive structure 113 away from the electronic component 114 will not be exposed, thereby preventing the conductive structure 113 from being bombarded by the etching ion beam and causing metal particles to fall on the second surface P2 of the semiconductor layer 112, reducing the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improving the electrical reliability of the semiconductor structure 100.

[0161] Step S205, removing the protection structure.

[0162] like Fig.18 As shown, after a portion of the semiconductor layer 112 is etched from one side of the second surface P2 of the semiconductor layer 112 along the first direction X using the protective structure 121 as a mask, the end of the conductive structure 113 away from the electronic component 114 can protrude from the semiconductor layer 112. At this time, the protective structure 121 can be removed, as shown in FIG. Fig.19 As shown, the protection structure 121 is prevented from affecting the subsequent processing technology.

[0163] For example, the protection structure 121 may be removed by cleaning.

[0164] In an embodiment of the present application, a protective structure 121 is formed on a side of the conductive structure 113 away from the first dielectric layer 111, and the orthographic projection of the protective structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end face of the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114) on the semiconductor layer 112, so that the protective structure 121 can shield and cover the end face of the conductive structure 113 away from the electronic component 114.

[0165] In this way, the protective structure 121 can be used as a mask. When etching a portion of the semiconductor layer 112 from the side of the second surface P2 of the semiconductor layer 112 along the first direction X, the etching ion beam will not bombard the end face of the conductive structure 113 away from the electronic component 114, thereby reducing the risk of metal particles falling on the second surface P2 of the semiconductor layer 112 due to splashing of the conductive structure 113 under the action of the etching ion beam when etching a portion of the semiconductor layer 112. This can reduce the residual conductive metal particles, reduce the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improve the electrical reliability of the semiconductor structure 100.

[0166] Furthermore, after etching a portion of the semiconductor layer 112 , the protection structure 121 is removed, so that the protection structure 121 can be prevented from affecting subsequent processing techniques.

[0167] In some examples, while etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask (that is, at the same time as step S204), the method further includes:

[0168] The first part of the second dielectric layer is etched. The first part of the second dielectric layer covers the outer peripheral side of the conductive structure away from the end of one side of the electronic component and is away from the conductive structure along a second direction. The second direction is parallel to the surface of the semiconductor layer.

[0169] It can be understood that the first direction X intersects with the surface of the semiconductor layer 112 and the second direction Y is parallel to the surface of the semiconductor layer 112 , so that the first direction X intersects with the second direction Y. In some examples, the first direction X is perpendicular to the second direction Y.

[0170] For example, Fig.19 and Fig. 20As shown, while etching the semiconductor layer 112 , the first portion of the second dielectric layer 115 can be etched, that is, the portion of the second dielectric layer 115 covering the outer peripheral side of the end of the conductive structure 113 away from the electronic component 114 and away from the conductive structure 113 along the second direction Y is etched.

[0171] Understandably, if Fig. 20 As shown, before the semiconductor layer 112 is etched, the second surface P2 of the semiconductor layer 112 is located at the first position a. After the semiconductor layer 112 is etched, the second surface P2 of the semiconductor layer 112 is located at the second position b. The distance between the first position a and the second position b is the third distance L3, that is, the semiconductor layer 112 is etched along the first direction X by the third distance L3. The length of the portion of the second dielectric layer 115 etched along the first direction X is the fourth distance L4, as shown in FIG. Fig. 20 As shown, the third distance L3 is equal to the fourth distance L4.

[0172] Etching the first portion of the second dielectric layer 115 while etching the semiconductor layer 112 can reduce the risk of the semiconductor layer 112 adhering to the second dielectric layer 115 and causing the semiconductor layer 112 to remain on the surface of the second dielectric layer 115 away from the conductive structure 113, thereby improving the reliability of the method for preparing the semiconductor structure.

[0173] Furthermore, in the second dielectric layer 115 covering the outer peripheral side of the end of the conductive structure 113 away from the electronic component 114 , a portion close to the conductive structure 113 along the second direction Y is not etched away. For example, this portion of the second dielectric layer 115 can be referred to as the second portion of the second dielectric layer 115 .

[0174] The second portion of the second dielectric layer 115 can protect the peripheral side of the end of the conductive structure 113 away from the electronic component 114. That is, the protective structure 121 can protect the end face of the conductive structure 113 away from the electronic component 114, and the second portion of the second dielectric layer 115 can protect the peripheral side of the end of the conductive structure 113 away from the electronic component 114, thereby preventing the etching ion beam from bombarding the end (including the end face and the peripheral side) of the conductive structure 113 away from the electronic component 114 when etching the semiconductor layer 112, reducing the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improving the electrical reliability of the semiconductor structure 100.

[0175] In some examples, such as Fig. 20As shown, the thickness D of the second portion of the second dielectric layer 115 may be half of the thickness of the unetched portion of the second dielectric layer 115. In other examples, the thickness D of the second portion of the second dielectric layer 115 may also be greater than or less than half of the thickness of the unetched portion of the second dielectric layer 115. It is understandable that the embodiment of the present application does not further limit the value of the thickness D of the second portion of the second dielectric layer 115.

[0176] In some examples, the thickness D of the second portion of the second dielectric layer 115 adjacent to different locations of the conductive structure 113 may be different.

[0177] Fig.21 A diagram showing the positional relationship between the edge of the orthographic projection of the protection structure on the semiconductor layer and the orthographic projection of the second dielectric layer on the semiconductor layer provided in some embodiments of the present application.

[0178] In some examples, an edge Q1 of the orthographic projection of the protection structure 121 on the semiconductor layer 112 is located between an orthographic projection Q2 of a surface of the second dielectric layer 115 on the side away from the conductive structure 113 on the semiconductor layer 112 and an orthographic projection Q3 of a surface of the second dielectric layer 115 on the side close to the conductive structure 113 on the semiconductor layer 112 .

[0179] For example, the orthographic projection of the protection structure 121 on the semiconductor layer 112 is a circle, the orthographic projection of the end surface of the conductive structure 113 away from the electronic component 114 on the semiconductor layer 112 is a circle, and the orthographic projection of the second dielectric layer 115 on the semiconductor layer 112 is a ring. Fig.21 As shown, the second dielectric layer 115 covers the conductive structure 113 , so that the orthographic projection of the conductive structure 113 on the semiconductor layer 112 can be located within the orthographic projection of the second dielectric layer 115 on the semiconductor layer 112 .

[0180] The edge Q1 of the orthographic projection of the protection structure 121 on the semiconductor layer 112 is located between the orthographic projection Q2 of the surface of the second dielectric layer 115 on the side away from the conductive structure 113 on the semiconductor layer 112 and the orthographic projection Q3 of the surface of the second dielectric layer 115 on the side close to the conductive structure 113 on the semiconductor layer 112, so that the protection structure 121 can cover the end surface of the conductive structure 113 on the side away from the electronic component 114, and the second part of the second dielectric layer 115 (see Fig.21 middle M3 area).

[0181] It can be understood that the protection structure 121 can protect the end surface of the conductive structure 113 that is away from the electronic component 114 and the second portion along the second dielectric layer 115, and the first portion of the second dielectric layer 115 that is not covered by the protection structure 121 can be etched away (see Fig.21 middle M4 area).

[0182] That is, by adopting the above-mentioned setting method, the protection structure 121 can protect the end surface of the conductive structure 113 away from the electronic component 114 and the second part of the second dielectric layer 115, and the first part of the second dielectric layer 115 can be etched and removed, thereby reducing the risk of the semiconductor layer 112 adhering to the second dielectric layer 115 and causing the semiconductor layer 112 to remain on the surface of the second dielectric layer 115 away from the conductive structure 113, thereby improving the reliability of the method for preparing the semiconductor structure.

[0183] Fig. 22 A flow chart of the steps of a method for preparing a semiconductor structure provided in some other embodiments of the present application. Fig.23 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application. Fig.24 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application.

[0184] In some examples, such as Fig. 22 As shown, forming a protection structure on a side of the conductive structure away from the first dielectric layer (that is, step S203) includes:

[0185] Step S2031, forming a photoresist layer on a side of the semiconductor layer away from the first dielectric layer.

[0186] like Fig.23 As shown, a photoresist layer (full name: Photoresist, English abbreviation: PR) 120 can be formed on the side of the semiconductor layer 112 away from the first dielectric layer 111. In some examples, such as Fig.23 As shown, other film layer structures may be disposed between the photoresist layer 120 and the second surface P2 of the semiconductor layer 112 ; in other examples, the photoresist layer 120 may also be disposed adjacent to the second surface P2 of the semiconductor layer 112 .

[0187] In some examples, a printing process may be used to form the photoresist layer 120 on a side of the isolation layer 131 away from the semiconductor layer 112 .

[0188] Step S2032, patterning the photoresist layer by exposure and development to form a protection structure.

[0189] For example, a mask may be disposed between the light source and the photoresist layer 120, and light passes through the pattern on the mask to irradiate the photoresist layer 120, so that the photoresist layer 120 can be patterned to form a protective structure 121 (see Fig.17 ).

[0190] In some examples, a positive developing photoresist layer may be used; in other examples, a negative developing photoresist layer may also be used.

[0191] It can be understood that the photoresist layer 120 is patterned by exposure and development to form a protective structure 121 without the need for a complicated preparation method. While improving the electrical performance of the semiconductor structure 100, the preparation process of the semiconductor structure 100 is simplified and the preparation cost of the semiconductor structure 100 is reduced.

[0192] Before forming a photoresist layer on a side of the semiconductor layer away from the first dielectric layer, the method comprises:

[0193] An isolation layer is formed on one side of the second surface of the semiconductor layer, and the isolation layer covers the semiconductor layer and the exposed end surface of the conductive structure.

[0194] like Fig.24 As shown, before forming the photoresist layer 120, an isolation layer 131 is formed on one side of the second surface P2 of the semiconductor layer 112. For example, the isolation layer 131 can be disposed adjacent to the second surface P2 of the semiconductor layer 112, so that the isolation layer 131 can cover the exposed end face of the semiconductor layer 112 and the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114). The photoresist layer 120 can be located on the side of the isolation layer 131 away from the semiconductor layer 112.

[0195] It can be understood that the isolation layer 131 can play an isolation role. For example, the material of the isolation layer 131 can be an oxide (English name: oxide), such as silicon dioxide (chemical formula: SiO2); or, the material of the isolation layer 131 can also be a nitride (English name: nitrides), such as silicon nitride (chemical formula: SiN); or, the material of the isolation layer 131 can also be a combination of one or more other high dielectric constant insulating materials. The materials of the first dielectric layer 111, the second dielectric layer 115, the third dielectric layer 116, and the isolation layer 131 can be the same or different. The embodiments of the present application do not further limit the material of the isolation layer 131.

[0196] Taking the conductive structure 113 as a cylinder, the bottom diameter of the cylinder is 5 μm, and the height of the cylinder is 50 μm as an example, the thickness of the isolation layer 131 can be (Unit: Angstrom). In some examples, the larger the size of the conductive structure 113, the greater the thickness of the isolation layer 131. The smaller the size of the conductive structure 113, the smaller the thickness of the isolation layer 131. The embodiments of the present application do not further limit the thickness of the isolation layer 131.

[0197] It can be understood that the isolation layer 131 is formed before forming the photoresist layer 120, so that the isolation layer 131 can isolate the photoresist layer 120 from the end face of the conductive structure 113 away from the electronic component 114, thereby avoiding contact between the photoresist layer 120 and the end face of the conductive structure 113 away from the electronic component 114, thereby avoiding contamination of the end face of the conductive structure 113 away from the electronic component 114 by the photoresist layer 120, and improving the electrical reliability of the semiconductor structure 100.

[0198] In some examples, before etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask (that is, before step S204), the method further includes:

[0199] Using the protection structure as a mask, the portion of the isolation layer covering the semiconductor layer is etched.

[0200] See again Fig.17 Since the isolation layer 131 covers the second surface P2 of the semiconductor layer 112 and the exposed end surface of the conductive structure 113, before etching the semiconductor layer 112, it is necessary to use the protection structure 121 as a mask to etch the portion of the isolation layer 131 covering the semiconductor layer 112 so that the semiconductor layer 112 can be exposed, thereby avoiding the isolation layer 131 from affecting subsequent processes.

[0201] In one example, etching the portion of the isolation layer 131 covering the semiconductor layer 112 and etching the semiconductor layer 112 may be implemented in the same step.

[0202] See also Fig.18 After etching the portion of the isolation layer 131 covering the semiconductor layer 112, the remaining portion of the isolation layer 131 covers the end surface of the conductive structure 113 away from the electronic component 114. In some examples, the orthographic projection of the protection structure 121 on the semiconductor layer 112 coincides with the orthographic projection of the remaining portion of the isolation layer 131 on the semiconductor layer 112.

[0203] In some examples, such as Fig.19 and Fig. 20 As shown, after etching the portion of the isolation layer 131 covering the semiconductor layer 112 and a portion of the semiconductor layer 112 , the protection structure 121 may be removed.

[0204] Fig.25 Schematic diagram of the structure of semiconductor layer groups provided in some other embodiments of the present application. Fig.26 A schematic diagram of the structure of a semiconductor structure provided for some embodiments of the present application.

[0205] In some examples, after removing the protection structure (that is, after step S205), the method further includes:

[0206] A third dielectric layer is formed, and the third dielectric layer covers the second surface of the semiconductor layer and wraps the end of the conductive structure protruding from the semiconductor layer.

[0207] It can be understood that the above embodiments of the present application have provided examples of the materials of the third dielectric layer 116 , which will not be described in detail herein.

[0208] like Fig.25 As shown, the third dielectric layer 116 is located on a side of the semiconductor layer 112 away from the first dielectric layer 111, so that the third dielectric layer 116 can cover the semiconductor layer 112 and wrap the end of the conductive structure 113 protruding from the semiconductor layer 112. In some examples, the third dielectric layer 116 can be disposed adjacent to the second surface P2 of the semiconductor layer 112.

[0209] A portion of the third dielectric layer and the isolation layer are removed along the first direction to expose the end surface of the conductive structure.

[0210] It can be understood that after forming the third dielectric layer 116, a portion of the third dielectric layer 116 and the isolation layer 131 covering the end surface of the conductive structure 113 away from the electronic component 114 can be removed along the first direction X. Fig.26 As shown, the end surface of the conductive structure 113 away from the electronic component 114 can be exposed. For example, the end surface of the conductive structure 113 away from the electronic component 114 is flush with the surface of the third dielectric layer 116 away from the semiconductor layer 112.

[0211] In some examples, a CMP process may be used to remove a portion of the third dielectric layer 116 and the isolation layer 131 covering the end surface of the conductive structure 113 away from the electronic component 114. For example, when removing a portion of the third dielectric layer 116 and the isolation layer 131 covering the end surface of the conductive structure 113 away from the electronic component 114, a portion of the conductive structure 113 along the first direction X may be removed, thereby achieving polishing and planarization of the surface of the third dielectric layer 116 away from the semiconductor layer 112 and the end surface of the conductive structure 113 away from the electronic component 114, thereby improving the structural regularity of the semiconductor structure 100.

[0212] It can be understood that the third dielectric layer 116 is removed along the first direction X, so that the end surface of the conductive structure 113 away from the electronic element 114 can be exposed, so that other components (such as external components or other semiconductor structures 100) can be electrically connected to the semiconductor structure 100 through the conductive structure 113. In addition, the third dielectric layer 116 can play a role of electrical isolation, thereby improving the reliability of the semiconductor structure 100 when electrically connected to other components.

[0213] On the other hand, an embodiment of the present application provides a semiconductor structure 100. Fig.26 As shown, the semiconductor structure 100 may include a semiconductor layer group 110 and a third dielectric layer 116 .

[0214] For example, as shown in FIG26, the semiconductor layer group 110 may include a first dielectric layer 111, a semiconductor layer 112, a second dielectric layer 115, a conductive structure 113, and an electronic component 114. The semiconductor layer 112 includes a first surface P1 and a second surface P2 that are oppositely disposed, the first dielectric layer 111 is disposed adjacent to the first surface P1 of the semiconductor layer 112, and the electronic component 114 is located in the first dielectric layer 111. One end of the conductive structure 113 is located in the first dielectric layer 111 and is electrically connected to the electronic component 114. The second dielectric layer 115 covers the conductive structure 113.

[0215] The third dielectric layer 116 is disposed adjacent to the second surface P2 of the semiconductor layer 112. The end of the conductive structure 113 away from the electronic element 114 passes through the semiconductor layer 112 and the third dielectric layer 116, and the end surface of the conductive structure 113 away from the electronic element 114 is exposed to the third dielectric layer 116.

[0216] It can be understood that the above embodiments of the present application have provided examples of the materials and positional relationship of the semiconductor layer group 110 and the third dielectric layer 116 , which will not be described in detail herein.

[0217] For example, Fig.26 As shown, the second dielectric layer 115 includes a first sub-portion 115a and a second sub-portion 115b, wherein the first sub-portion 115a is located between the third dielectric layer 116 and the conductive structure 113, and the second sub-portion 115b is located between the semiconductor layer 112 and the conductive structure 113. The thickness of the first sub-portion 115a is less than that of the second sub-portion 115b.

[0218] It can be understood that since the first portion along the second dielectric layer 115 is etched while etching the semiconductor layer 112, the thickness of the remaining portion of the second dielectric layer 115 (the second portion of the second dielectric layer 115, that is, the first sub-portion 115a) after etching can be smaller than the thickness of the second dielectric layer 115 that has not been etched.

[0219] Such a configuration can reduce the risk of the semiconductor layer 112 adhering to the surface of the first sub-portion 115 a away from the conductive structure 113 , thereby improving the electrical reliability of the semiconductor structure 100 .

[0220] In summary, the embodiments of the present application have at least the following beneficial effects:

[0221] In an embodiment of the present application, a protective structure 121 is formed on a side of the conductive structure 113 away from the first dielectric layer 111, and the orthographic projection of the protective structure 121 on the semiconductor layer 112 covers the orthographic projection of the exposed end face of the conductive structure 113 (that is, the end face of the conductive structure 113 away from the electronic component 114) on the semiconductor layer 112, so that the protective structure 121 can shield and cover the end face of the conductive structure 113 away from the electronic component 114.

[0222] In this way, the protective structure 121 can be used as a mask. When etching a portion of the semiconductor layer 112 from the side of the second surface P2 of the semiconductor layer 112 along the first direction X, the etching ion beam will not bombard the end face of the conductive structure 113 away from the electronic component 114, thereby reducing the risk of metal particles falling on the second surface P2 of the semiconductor layer 112 due to splashing of the conductive structure 113 under the action of the etching ion beam when etching a portion of the semiconductor layer 112. This can reduce the residual conductive metal particles, reduce the metal contamination of the semiconductor layer 112 caused by the conductive structure 113, and improve the electrical reliability of the semiconductor structure 100.

[0223] Furthermore, after etching a portion of the semiconductor layer 112 , the protection structure 121 is removed, so that the protection structure 121 can be prevented from affecting subsequent processing techniques.

[0224] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor layer group, the semiconductor layer group comprising a first dielectric layer, a semiconductor layer, a conductive structure and an electronic element; The semiconductor layer comprises a first surface and a second surface which are arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer; One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component, and the other end of the conductive structure passes through the first surface of the semiconductor layer and extends into the semiconductor layer; Along the first direction, a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer to expose an end surface of the conductive structure away from the electronic component; The first direction intersects with the surface of the semiconductor layer; forming a protection structure on a side of the conductive structure away from the first dielectric layer, wherein the orthographic projection of the protection structure on the semiconductor layer covers the orthographic projection of the exposed end surface of the conductive structure on the semiconductor layer; Using the protection structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along a first direction; The protective structure is removed.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The semiconductor layer group further includes a second dielectric layer, and the second dielectric layer covers the conductive structure; Using the protection structure as a mask, etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction, further comprising: The first portion of the second dielectric layer is etched; the first portion of the second dielectric layer covers the outer peripheral side of the conductive structure away from the end of one side of the electronic component and is away from the conductive structure along a second direction; the second direction is parallel to the surface of the semiconductor layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The edge of the orthographic projection of the protection structure on the semiconductor layer is located between the orthographic projection of the surface of the second dielectric layer away from the conductive structure on the semiconductor layer and the orthographic projection of the surface of the second dielectric layer close to the conductive structure on the semiconductor layer.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The protection structure is formed on a side of the conductive structure away from the first dielectric layer, comprising: forming a photoresist layer on a side of the semiconductor layer away from the first dielectric layer; The photoresist layer is patterned by exposure and development to form the protection structure.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: Before forming the photoresist layer on a side of the semiconductor layer away from the first dielectric layer, the method comprises: forming an isolation layer on one side of the second surface of the semiconductor layer, wherein the isolation layer covers the semiconductor layer and the exposed end surface of the conductive structure; Before etching a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask, the method further includes: Using the protection structure as a mask, etching the portion of the isolation layer covering the semiconductor layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: After removing the protective structure, the method further comprises: forming a third dielectric layer, wherein the third dielectric layer covers the second surface of the semiconductor layer and wraps the end of the conductive structure protruding from the semiconductor layer; A portion of the third dielectric layer and the isolation layer are removed along the first direction to expose an end surface of the conductive structure away from the electronic component.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 6, characterized in that: There are multiple conductive structures, and the multiple conductive structures include a first conductive structure and a second conductive structure; before a portion of the semiconductor layer is removed from one side of the second surface of the semiconductor layer along the first direction to expose an end surface of the conductive structure away from the electronic component, a distance between the end surface of the first conductive structure away from the electronic component and the second surface of the semiconductor layer is not equal to a distance between the end surface of the second conductive structure away from the electronic component and the second surface of the semiconductor layer; Removing a portion of the semiconductor layer from one side of the second surface of the semiconductor layer along the first direction to expose an end surface of the conductive structure away from the electronic component comprises: Along the first direction, a portion of the semiconductor layer and a portion of the conductive structure are removed from one side of the second surface of the semiconductor layer to expose the end faces of the first conductive structure and the second conductive structure away from the electronic component; wherein the exposed end face of the first conductive structure is flush with the exposed end face of the second conductive structure.

8. A semiconductor structure, characterized in that: include: A semiconductor layer group, the semiconductor layer group comprising a first dielectric layer, a semiconductor layer, a second dielectric layer, a conductive structure and an electronic element; The semiconductor layer comprises a first surface and a second surface which are arranged opposite to each other, the first dielectric layer is arranged adjacent to the first surface of the semiconductor layer, and the electronic component is located in the first dielectric layer; One end of the conductive structure is located in the first dielectric layer and is electrically connected to the electronic component; The second dielectric layer covers the conductive structure; a third dielectric layer, the third dielectric layer being disposed adjacent to the second surface of the semiconductor layer; an end of the conductive structure away from the electronic component passes through the semiconductor layer and the third dielectric layer, and an end surface of the conductive structure away from the electronic component is exposed to the third dielectric layer; The second dielectric layer includes a first sub-portion and a second sub-portion, the first sub-portion is located between the third dielectric layer and the conductive structure, and the second sub-portion is located between the semiconductor layer and the conductive structure; the thickness of the first sub-portion is smaller than the thickness of the second sub-portion.

9. A functional chip, characterized in that: comprising at least one semiconductor structure; the semiconductor structure being the semiconductor structure as claimed in claim 8; or, The semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure according to any one of claims 1 to 7.

10. The functional chip according to claim 9, characterized in that: When the functional chip includes at least two semiconductor structures, the at least two semiconductor structures include a first semiconductor structure and a second semiconductor structure; The exposed end surface of the conductive structure in the first semiconductor structure is bonded to the exposed end surface of the conductive structure in the second semiconductor structure.

11. An electronic device, characterized in that: include: bus; The function chip as claimed in claim 9 or 10, wherein the function chip is electrically connected to the bus.

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