Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes: a lower semiconductor chip including a first circuit layer; an upper semiconductor chip disposed on the lower semiconductor chip and including a second circuit layer; and an interconnection layer disposed between the lower semiconductor chip and the upper semiconductor chip, the interconnection layer including: a plurality of pads including at least a first pad offset from the lower semiconductor chip or the upper semiconductor chip; and a wiring portion extending horizontally and connecting a first pad of the plurality of pads to a second pad of the plurality of pads disposed between the lower semiconductor chip and the upper semiconductor chip, in which the wiring portion of the interconnect layer electrically connects the first circuit layer to the second circuit layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Korean Patent Application No. 10-2023-0082179 filed in the Korean Intellectual Property Office on June 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package including an interconnection layer connecting semiconductor chips offset from each other. Background Art

[0004] The demand for portable electronic devices has led to the development of high-performance, small-size and light-weight electronic components constituting these devices. Among these electronic components, the demand for memory-type semiconductor devices with high performance, high bandwidth and / or high processing power is increasing.

[0005] Reduction in component size and / or improvement in device performance may lead to various difficulties. In particular, for semiconductor packages for processing high frequency signals, reduction in size may need to be balanced with electrical characteristics such as reliability.

[0006] Generally, packaging technology has been developed to reduce device size and ensure device characteristics. For example, multiple memory chips can be stacked on a package substrate using a through silicon via (TSV) process, a flip chip process, a wire bonding process, etc. However, these processes may be associated with high complexity and high cost. Summary of the invention

[0007] Embodiments of the inventive concept provide a semiconductor package having high integration density and a method of manufacturing the same.

[0008] Embodiments of the inventive concept provide a semiconductor package having improved electrical characteristics and a method of manufacturing the same.

[0009] According to an embodiment conceived in the present invention, a semiconductor package may include: a lower semiconductor chip, which includes a first circuit layer; an upper semiconductor chip, which is arranged on the lower semiconductor chip and includes a second circuit layer; and an interconnection layer, which is arranged between the lower semiconductor chip and the upper semiconductor chip, the interconnection layer including: a plurality of pads, the plurality of pads including at least a first pad offset from the lower semiconductor chip or the upper semiconductor chip; a wiring portion, which extends horizontally and connects a first pad among the plurality of pads to a second pad among the plurality of pads arranged between the lower semiconductor chip and the upper semiconductor chip, wherein the wiring portion of the interconnection layer electrically connects the first circuit layer to the second circuit layer.

[0010] According to an embodiment of the inventive concept, a semiconductor package may include: a package substrate; a lower semiconductor chip disposed on the package substrate; an upper semiconductor chip disposed on the lower semiconductor chip and horizontally offset from a portion of the lower semiconductor chip; and an interconnection layer disposed between the lower semiconductor chip and the upper semiconductor chip. The interconnection layer covers the bottom surface of the upper semiconductor chip in a first region offset from the lower semiconductor chip. The upper semiconductor chip may include a first circuit layer disposed on the bottom surface of the upper semiconductor chip. The thickness of the interconnection pattern of the first circuit layer may be less than the thickness of the interconnection pattern of the interconnection layer.

[0011] According to an embodiment of the present invention, a semiconductor package may include: a package substrate; a first semiconductor chip disposed on the package substrate; a first mold layer disposed on the package substrate to surround the first semiconductor chip; a first interconnect layer covering a top surface of the first semiconductor chip and a top surface of the first mold layer; a second semiconductor chip on the first interconnect layer; a second mold layer disposed on the first interconnect layer to surround the second semiconductor chip; and a plurality of external terminals disposed on a bottom surface of the package substrate. The second semiconductor chip may be horizontally offset from the first semiconductor chip and may vertically overlap with a side surface of the first semiconductor chip. The first semiconductor chip and the first mold layer may be spaced apart from the second semiconductor chip and the second mold layer by the first interconnect layer.

[0012] According to an embodiment of the present invention, a semiconductor package may include: a package substrate; a first semiconductor chip disposed on the package substrate, the first semiconductor chip including: a first circuit layer disposed on a surface of the first semiconductor chip; and a plurality of first through-holes vertically penetrating the first semiconductor chip and coupled to the first circuit layer; a first mold layer disposed on the package substrate to surround the first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip and offset from the first semiconductor chip, the second semiconductor chip including: a second circuit layer disposed on a bottom surface of the second semiconductor chip; and a plurality of second through-holes vertically penetrating the second semiconductor chip and coupled to the second circuit layer; a first interconnect layer disposed between the second circuit layer and the first semiconductor chip, and between the second circuit layer and the first mold layer; and a second mold layer disposed on the first mold layer to surround the first interconnect layer and the second semiconductor chip. The first interconnect layer may expose the top surface of the first semiconductor chip in a region beside the second semiconductor chip. The second semiconductor chip may be connected to the first interconnect layer through a plurality of chip pads of the second circuit layer. When viewed in a plan view, at least one of the chip pads may be disposed on a side surface of the first semiconductor chip, and the interconnection pattern of the first interconnection layer may electrically connect the at least one of the chip pads to the first via.

[0013] According to an embodiment of the present invention, a method for manufacturing a semiconductor package may include: providing a package substrate; mounting a first semiconductor chip on the package substrate; forming a first mold layer surrounding the first semiconductor chip on the package substrate; setting a second semiconductor chip; forming an interconnection layer on at least one of a top surface of the first semiconductor chip and a bottom surface of the second semiconductor chip; mounting the second semiconductor chip on a portion of the first semiconductor chip and a portion of the first mold layer, the second semiconductor chip being electrically connected to the first semiconductor chip through the interconnection layer; and forming a second mold layer surrounding the second semiconductor chip on the first mold layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0015] Figure 2 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0016] Figure 3 It is shown Figure 1 An enlarged cross-sectional view of portion "A" of FIG.

[0017] Figure 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0018] Figure 5 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0019] Figure 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0020] Figure 7 It is shown Figure 6 An enlarged cross-sectional view of portion "B" of FIG.

[0021] Figure 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0022] Fig. 9 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0023] Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0024] Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. Specific embodiments

[0025] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings.

[0026] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 2 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 3 It is shown Figure 1 An enlarged cross-sectional view of portion "A" of FIG.

[0027] Reference Figure 1 , a package substrate 100 may be provided. The package substrate 100 may be a redistribution substrate. For example, the package substrate 100 may include one or more substrate interconnect layers. In the case of two or more substrate interconnect layers, the substrate interconnect layers may be stacked. Each of the substrate interconnect layers may include a substrate insulating layer 110 and a substrate interconnect pattern 120 disposed in the substrate insulating layer 110. The substrate interconnect pattern 120 of the first substrate interconnect layer may be electrically connected to the substrate interconnect pattern 120 of the second substrate interconnect layer adjacent to the first substrate interconnect layer.

[0028] The substrate insulating layer 110 may include at least one of an insulating polymer and a photoimageable polymer (e.g., a photoimageable dielectric (PID)). For example, the substrate insulating layer 110 may be formed of or include at least one of a photoimageable polyimide, a polybenzoxazole (PBO), a phenol-based polymer, and a benzocyclobutene-based polymer.

[0029] The substrate interconnection pattern 120 may be disposed in the substrate insulating layer 110. The substrate interconnection pattern 120 may extend horizontally in the substrate insulating layer 110. For example, the substrate interconnection pattern 120 may be used as a pad portion or a line portion of the substrate interconnection layer. In an embodiment, the substrate interconnection pattern 120 may be a structure for horizontal redistribution of a signal or power within the package substrate 100. The substrate interconnection pattern 120 may be disposed in the upper portion of the substrate insulating layer 110. The top surface of the substrate interconnection pattern 120 may be exposed on the top surface of the substrate insulating layer 110. For example, the top surface of the substrate interconnection pattern 120 may be exposed to the outside of the substrate insulating layer 110 at the top surface of the substrate insulating layer 110. The substrate interconnection pattern 120 in the uppermost substrate interconnection layer may be used as a substrate pad. For example, the substrate interconnection pattern 120 in the uppermost substrate interconnection layer may be connected to the first semiconductor chip 200. The substrate interconnection pattern 120 may include a conductive material. For example, the substrate interconnection pattern 120 may be formed of a metal material (e.g., copper (Cu)), or include a metal material (e.g., copper (Cu)).

[0030] The substrate interconnection pattern 120 may include a through-piece portion extending toward the bottom surface of the substrate insulation layer 110. The through-piece portion may be a structure for vertically connecting adjacent substrate interconnection patterns in the substrate interconnection pattern 120. Alternatively, the through-piece portion of the substrate interconnection pattern 120 may be a structure for connecting the lowermost one of the substrate interconnection patterns to the external pad 130. For example, the through-piece portion may extend from the bottom surface of the substrate interconnection pattern 120 to penetrate the substrate insulation layer 110, and may be coupled to the top surface of the substrate interconnection pattern 120 of the lower substrate interconnection layer. Alternatively, the through-piece portion may extend from the bottom surface of the substrate interconnection pattern 120 to penetrate the lowermost one of the substrate insulation layers, and may be coupled to the top surface of the external pad 130.

[0031] In an embodiment, in one of the substrate interconnection layers, a substrate interconnection pattern 120 may be disposed on a top surface of a substrate insulating layer 110, and a through-piece portion of the substrate interconnection pattern 120 may penetrate the substrate insulating layer 110 and may be coupled to the substrate interconnection pattern 120 of the underlying substrate interconnection layer.

[0032] The external pad 130 may be disposed on the bottom surface of the lowest one of the substrate interconnection layers. The external pad 130 may be electrically connected to the substrate interconnection pattern 120. The external terminal 150 may be disposed on and coupled to the external pad 130. The external pad 130 may electrically connect the substrate interconnection pattern 120 to the external terminal 150.

[0033] A substrate protection layer 140 may be provided. The substrate protection layer 140 may cover the bottom surface of the lowermost one of the substrate interconnection layers and expose the external pads 130. The external terminals 150 may be disposed on the exposed bottom surfaces of the external pads 130. The external terminals 150 may include, for example, solder balls or solder bumps.

[0034] The package substrate 100 may have the above-described structure. However, the inventive concept is not limited to these examples. The package substrate 100 may be a printed circuit board (PCB). For example, the package substrate 100 may include a core layer and a peripheral portion that may be used to connect interconnects above and below the core layer.

[0035] The first semiconductor chip 200 may be disposed on the package substrate 100. The first semiconductor chip 200 may be a logic chip. In an embodiment, the first semiconductor chip 200 may be a memory chip (e.g., a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), or a flash memory chip). The first semiconductor chip 200 may have a front surface 200a and a rear surface 200b. Hereinafter, in this specification, the front surface may be a surface of a semiconductor chip referred to as an active surface, and an integrated device or a pad is formed on the surface, and the rear surface may be another surface of the semiconductor chip opposite to the front surface. The bottom surface of the first semiconductor chip 200 may be the front surface 200a. That is, the first semiconductor chip 200 may be disposed on the package substrate 100 in a face-down manner. The first semiconductor chip 200 may include a first base layer 210, a first circuit layer 220, and at least one first through-through member 230.

[0036] The first base layer 210 may include a semiconductor material. For example, the first base layer 210 may be a single crystal silicon wafer. A semiconductor device may be provided in the first base layer 210. In detail, an integrated device or an integrated circuit may be formed in a lower portion of the first base layer 210. For example, an integrated device (e.g., a transistor), a passive device (e.g., a resistor, a capacitor, or an inductor), or an interconnection pattern may be formed on the bottom surface of the first base layer 210. That is, the bottom surface of the first base layer 210 may be a front surface, and the top surface of the first base layer 210 may be a rear surface.

[0037] The first circuit layer 220 may be disposed on the bottom surface of the first base layer 210. The first circuit layer 220 may be electrically connected to an integrated device or an integrated circuit that may be formed in the first base layer 210. For example, the first circuit layer 220 may include a first insulating pattern 222 and a first interconnection pattern 224 that may be disposed in the first insulating pattern 222, and the first interconnection pattern 224 may be coupled to the integrated device or the integrated circuit in the first base layer 210.

[0038] The first insulating pattern 222 on the bottom surface of the first base layer 210 may cover an integrated device or an integrated circuit. Figure 1 An example in which the first insulating pattern 222 is a single layer is shown, but the inventive concept is not limited to this example. In an embodiment, a plurality of first insulating patterns 222 may be stacked on top of each other. In this case, the first insulating pattern 222 may be an interconnect layer that may be vertically connected to each other. The first insulating pattern 222 may be formed of silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), or include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON).

[0039] The first interconnect pattern 224 may be disposed in the first insulating pattern 222. In the case where the first insulating pattern 222 is composed of a plurality of layers, the first interconnect pattern 224 may also be composed of a plurality of layers, and one of the first insulating patterns 222 and one of the first interconnect patterns 224 may constitute a single interconnect layer. The first interconnect pattern 224 may be coupled to an integrated device or an integrated circuit formed in the first base layer 210. That is, the first circuit layer 220 may be electrically connected to an integrated device or an integrated circuit that may be formed in the first base layer 210. A portion of the first interconnect pattern 224 may be exposed on the bottom surface of the first circuit layer 220. The exposed portion of the first interconnect pattern 224 may be used as a first chip pad 225 of the first semiconductor chip 200. In an embodiment, a plurality of first chip pads 225 may be provided. The first interconnect pattern 224 may include a wiring portion extending horizontally to serve as a horizontal interconnect path and a through-piece portion extending vertically to serve as a vertical interconnect path. The first interconnection pattern 224 may be formed of or include at least one of a metal material (e.g., copper (Cu) or aluminum (Al)). The bottom surface of the first semiconductor chip 200 on which the first interconnection pattern 224 is disposed may be an active surface of the first semiconductor chip 200.

[0040] The first penetration penetration 230 may vertically penetrate the first base layer 210. For example, the first penetration penetration 230 may be a columnar pattern vertically penetrating the first base layer 210. The first penetration penetration 230 may include an end extending toward the front surface 200a of the first semiconductor chip 200 and connected to the first circuit layer 220. The first penetration penetration 230 may be coupled to the first interconnect pattern 224 of the first circuit layer 220. The first penetration penetration 230 may also include an opposite end exposed on the top surface of the first base layer 210. For example, the opposite end of the first penetration penetration 230 may be located at the same horizontal height as the top surface of the first base layer 210 (i.e., the rear surface 200b of the first semiconductor chip 200). The top surface of the first penetration penetration 230 and the top surface of the first base layer 210 may be substantially coplanar with each other, thereby forming a substantially flat surface. Alternatively, the first penetration penetration 230 may protrude above the top surface of the first base layer 210. For example, the opposite ends of the first penetration penetration piece 230 may be located at a higher level than the top surface of the first base layer 210. In this case, a protective layer may be provided on the top surface of the first base layer 210 to cover the top surface of the first base layer 210 and surround the first penetration penetration piece 230. The top surface of the first penetration penetration piece 230 may be exposed on the top surface of the protective layer. In an embodiment, a plurality of first penetration penetration pieces 230 may be provided. The first penetration penetration piece 230 may be formed of or include at least one metal material (e.g., copper (Cu) and tungsten (W)).

[0041] Although not shown, the first penetration penetration 230 may further include a penetration barrier layer surrounding the outer surface of the first penetration penetration 230. Here, the penetration barrier layer may not cover the top surface of the first penetration penetration 230. That is, the top surface of the first penetration penetration 230 may not be covered by the penetration barrier layer and may be exposed to the outside of the penetration barrier layer. The penetration barrier layer may be used to electrically isolate the first penetration penetration 230 from the first base layer 210. The penetration barrier layer may be used to prevent the material of the first penetration penetration 230 from diffusing into the first base layer 210. The penetration barrier layer may be formed of at least one conductive metal nitride (e.g., titanium nitride (TiN) and tantalum nitride (TaN)), or include at least one conductive metal nitride (e.g., titanium nitride (TiN) and tantalum nitride (TaN)). Alternatively, the penetration barrier layer may be formed of an insulating layer, or include an insulating layer. In an embodiment, the penetration barrier layer may be omitted.

[0042] The first semiconductor chip 200 may be mounted on the package substrate 100 in a flip chip manner. For example, the first semiconductor chip 200 may be arranged so that the first chip pad 225 faces the package substrate 100. That is, the first semiconductor chip 200 may be arranged so that the front surface 200a of the first semiconductor chip 200 faces the package substrate 100. The first chip terminal 240 may be arranged between the first chip pad 225 and the package substrate 100. The first chip terminal 240 may be coupled to the first chip pad 225. The first semiconductor chip 200 may be connected to the package substrate 100 through the first chip pad 225, the first chip terminal 240 and the substrate interconnection pattern 120. The first chip terminal 240 may include a solder ball or a solder bump.

[0043] The first mold layer 410 may be disposed on the package substrate 100. The first mold layer 410 may cover the top surface of the package substrate 100. The first mold layer 410 may surround the first semiconductor chip 200. The first mold layer 410 may protect the first semiconductor chip 200. For example, the first mold layer 410 may cover the side surface of the first semiconductor chip 200. The first mold layer 410 may fill the space between the package substrate 100 and the first semiconductor chip 200. Between the package substrate 100 and the first semiconductor chip 200, the first mold layer 410 may surround the first chip terminal 240. The first mold layer 410 may expose the top surface 200b of the first semiconductor chip 200. The top surface of the first mold layer 410 may be coplanar with the top surface 200b of the first semiconductor chip 200, and the top surface of the first mold layer 410 and the top surface 200b of the first semiconductor chip 200 may be substantially flat. The first mold layer 410 may include an insulating material. For example, the first molding layer 410 may be formed of or include an epoxy molding compound (EMC).

[0044] In an embodiment, the bottom filling portion may be disposed between the first semiconductor chip 200 and the package substrate 100. The bottom filling portion may include a non-conductive film (NCF). For example, the bottom filling portion may be a polymer tape including an insulating material. Alternatively, the bottom filling portion may include a fluid adhesive. The bottom filling portion may fill the space between the first semiconductor chip 200 and the package substrate 100 and surround the first chip terminal 240. The bottom filling portion may be disposed between the first chip terminals 240 and may prevent an electrical short circuit from being formed between the first chip terminals 240. The bottom filling portion may protrude laterally relative to the side surface of the first semiconductor chip 200. The first mold layer 410 may surround the first semiconductor chip 200. In an embodiment, the first mold layer 410 on the package substrate 100 may surround both the bottom filling portion and the first semiconductor chip 200.

[0045] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. The second semiconductor chip 300 may be placed on the rear surface 200b of the first semiconductor chip 200. The first semiconductor chip 200 and the second semiconductor chip 300 may be arranged to form an offset stacking structure. For example, the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked to form a step structure that is tilted upward in the first direction D1. In detail, when viewed in a plan view, a portion of the second semiconductor chip 300 may overlap with the first semiconductor chip 200, and the other portion of the second semiconductor chip 300 may protrude relative to the side surface of the first semiconductor chip 200 in the first direction D1. That is, the second semiconductor chip 300 may be stacked on the first semiconductor chip 200 to be horizontally offset from the first semiconductor chip 200 in the first direction D1. The second semiconductor chip 300 may vertically overlap with the side surface of the first semiconductor chip 200 in the first direction D1. As an example, when viewed from the bottom of the semiconductor package, a portion of the bottom surface of the second semiconductor chip 300 may not be covered by the first semiconductor chip 200 and may be exposed to the outside of the first semiconductor chip 200 .

[0046] The second semiconductor chip 300 may be provided with a structure identical or similar to the above-mentioned first semiconductor chip 200. For example, the first semiconductor chip 200 and the second semiconductor chip may be of the same type. As an example, the width of the second semiconductor chip 300 may be substantially equal to the width of the first semiconductor chip 200. Alternatively, the second semiconductor chip 300 may be of a type different from the first semiconductor chip 200. The second semiconductor chip 300 may be a logic chip. In an embodiment, the second semiconductor chip 300 may be a memory chip (e.g., a DRAM, SRAM, MRAM, or flash memory chip). The second semiconductor chip 300 may have a front surface 300a and a rear surface. The bottom surface of the second semiconductor chip 300 may be the front surface 300a. The second semiconductor chip 300 may be provided on the first semiconductor chip 200 in a face-down manner. The second semiconductor chip 300 may include a second base layer 310, a second circuit layer 320, and at least one second penetration through-piece 330.

[0047] The second base layer 310 may include a semiconductor material. For example, the second base layer 310 may be a single crystal silicon substrate. A semiconductor device may be provided in the second base layer 310. In detail, an integrated device or an integrated circuit may be formed in a lower portion of the second base layer 310. For example, an integrated device (e.g., a transistor), a passive device (e.g., a resistor, a capacitor, or an inductor), or an interconnection pattern may be formed on the bottom surface of the second base layer 310. That is, the bottom surface of the second base layer 310 may be a front surface, and the top surface of the second base layer 310 may be a rear surface.

[0048] The second circuit layer 320 may be disposed on the bottom surface of the second base layer 310. The second circuit layer 320 may be electrically connected to an integrated device or integrated circuit formed in the second base layer 310. For example, the second circuit layer 320 may include a second insulating pattern 322 and a second interconnection pattern 324 therein, and here, the second interconnection pattern 324 may be coupled to the integrated device or integrated circuit formed in the second base layer 310.

[0049] On the bottom surface of the second base layer 310 , a second insulating pattern 322 may cover the integrated device or the integrated circuit. Figure 1 and Figure 3 An example in which the second insulating pattern 322 is a single layer is shown, but the inventive concept is not limited to this example. In an embodiment, a plurality of second insulating patterns 322 may be arranged to be stacked on top of each other. In this case, the second insulating pattern 322 may be an interconnect layer that may be vertically connected to each other. The second insulating pattern 322 may be formed of at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or may include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0050] The second interconnection pattern 324 may be disposed in the second insulating pattern 322. In the case where the second insulating pattern 322 is composed of multiple layers, the second interconnection pattern 324 may also be composed of multiple layers, and one of the second insulating patterns 322 and one of the second interconnection patterns 324 may constitute a single interconnection layer. The second interconnection pattern 324 may be coupled to an integrated device or integrated circuit in the second base layer 310. That is, the second circuit layer 320 may be electrically connected to an integrated device or integrated circuit that may be formed in the second base layer 310. A portion of the second interconnection pattern 324 may be exposed on the bottom surface of the second circuit layer 320. The exposed portion of the second interconnection pattern 324 may be used as a second chip pad 325 of the second semiconductor chip 300. In an embodiment, a plurality of second chip pads 325 may be provided. The second interconnection pattern 324 may include a wiring portion extending horizontally to serve as a horizontal interconnection path and a through-piece portion extending vertically to serve as a vertical interconnection path. The second interconnection pattern 324 may be formed of at least one metal material (e.g., copper (Cu) and aluminum (Al)), or include at least one metal material (e.g., copper (Cu) and aluminum (Al)). The bottom surface of the second semiconductor chip 300 on which the second interconnection pattern 324 is disposed may be an active surface of the second semiconductor chip 300 .

[0051] Since the first semiconductor chip 200 and the second semiconductor chip 300 are stacked to form an offset stack structure, the position of the second chip pad 325 may be different from the position of the first penetration penetration 230 when viewed in a plan view. For example, the second chip pad 325 may be offset from the first penetration penetration 230 in the vertical direction. More specifically, the second chip pad 325 may not be vertically aligned with the first penetration penetration 230. As an example, at least one offset first penetration penetration 230s of the first penetration penetration 230 may be spaced apart from the second semiconductor chip 300 in a direction opposite to the first direction D1. The offset second chip pad 325s of the second chip pad 325 may be spaced apart from the first semiconductor chip 200 in the first direction D1. The second chip pad 325 may be aligned with the first penetration penetration 230 in an area where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap each other. However, in an embodiment, in an overlap region between the first semiconductor chip 200 and the second semiconductor chip 300 , the second chip pad 325 may not be aligned with the first through via 230 .

[0052] The second penetration penetration piece 330 may vertically penetrate the second base layer 310. For example, the second penetration penetration piece 330 may be a columnar pattern vertically penetrating the second base layer 310. The second penetration penetration piece 330 may include an end extending toward the front surface 300a of the second semiconductor chip 300 and connected to the second circuit layer 320. The second penetration penetration piece 330 may be coupled to the second interconnect pattern 324 of the second circuit layer 320. The second penetration penetration piece 330 may also include an opposite end exposed on the top surface of the second base layer 310. For example, the opposite end of the second penetration penetration piece 330 may be located at the same horizontal height as the top surface of the second base layer 310 (that is, the rear surface of the second semiconductor chip 300). The top surface of the second penetration penetration piece 330 and the top surface of the second base layer 310 may be substantially coplanar with each other, thereby forming a substantially flat surface. Alternatively, the second penetration penetration 330 may protrude upward relative to the top surface of the second base layer 310, and the protective layer may be disposed on the top surface of the second base layer 310 to cover the top surface of the second base layer 310 and surround the second penetration penetration 330. In an embodiment, a plurality of second penetration penetrations 330 may be provided. The second penetration penetration 330 may be formed of or include at least one metal material (e.g., copper (Cu) and tungsten (W)). In an embodiment, the second penetration penetration 330 may further include a penetration barrier layer disposed around the outer surface of the second penetration penetration 330.

[0053] The redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the top surface 200b of the first semiconductor chip 200 and the bottom surface 300a of the second semiconductor chip 300. The redistribution layer 420 may extend from an area on the first semiconductor chip 200 to an area on the first mold layer 410. For example, the redistribution layer 420 may be disposed to cover the top surface 200b of the first semiconductor chip 200 and the top surface of the first mold layer 410. The redistribution layer 420 may be disposed for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. In an embodiment, the redistribution layer 420 may be composed of a single interconnection layer. The interconnection layer may include a redistribution insulation pattern 422 and a redistribution pattern 424 in the redistribution insulation pattern 422.

[0054] The redistribution insulating pattern 422 may include at least one of an insulating polymer and a photoimageable polymer (e.g., a photoimageable dielectric (PID)). For example, the redistribution insulating pattern 422 may be formed of at least one of a photoimageable polyimide, a polybenzoxazole (PBO), a phenol-based polymer, and a benzocyclobutene-based polymer, or include at least one of a photoimageable polyimide, a polybenzoxazole (PBO), a phenol-based polymer, and a benzocyclobutene-based polymer. Alternatively, the redistribution insulating pattern 422 may be formed of at least one of an insulating material (e.g., silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON)), or include at least one of an insulating material (e.g., silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON)).

[0055] The redistribution pattern 424 may be disposed in the redistribution insulating pattern 422. In the redistribution insulating pattern 422, the redistribution pattern 424 may extend horizontally. Figure 2 As shown, the redistribution pattern 424 may include a pad portion 424p and a wiring portion 424w. The redistribution pattern 424 may be a structure for horizontal redistribution of a signal or power within the redistribution layer 420. The pad portion 424p of the redistribution pattern 424 may be exposed on the top surface or the bottom surface of the redistribution insulating pattern 422, and the wiring portion 424w may connect the pad portions 424p to each other. The wiring portion 424w may extend in a horizontal direction within the redistribution layer 420 to connect the pad portions 424p to each other. The redistribution pattern 424 may include a conductive material. For example, the redistribution pattern 424 may be formed of at least one metal material (e.g., copper (Cu)), or include at least one metal material (e.g., copper (Cu)).

[0056] The pad portion 424p of the redistribution pattern 424 may be arranged at a position corresponding to the first penetration through-piece 230 and the second chip pad 325. As an example, the pad portion 424p may be arranged along the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may be two different directions parallel to the top surface of the package substrate 100 and may not be parallel to each other. The first direction D1 and the second direction D2 may be perpendicular to each other. As an example, the pad portion 424p may be arranged in a lattice shape. In an embodiment, the pad portion 424p may be arranged in a honeycomb shape or other shapes. The pad portion 424p may be used as a substrate pad, and the first semiconductor chip 200 or the second semiconductor chip 300 may be coupled to the substrate pad. For example, some of the pad portions 424p may be arranged on the first semiconductor chip 200. In detail, such pad portions 424p may be respectively arranged on the first penetration through-piece 230. The first through-via 230 may be coupled to the pad portion 424p at the interface between the redistribution layer 420 and the first semiconductor chip 200. Some of the pad portions 424p may be disposed under the second semiconductor chip 300. In detail, the pad portions 424p disposed under the second semiconductor chip 300 may be respectively disposed under the second chip pads 325. At the interface between the redistribution layer 420 and the second semiconductor chip 300, the second chip pad 325 may be coupled to the pad portion 424p.

[0057] Since the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked to form an offset stack structure, the pad portion 424p that does not vertically overlap with the first semiconductor chip 200 (i.e., in a region beside the first semiconductor chip 200) may be coupled to the offset second chip pad 325s of the second semiconductor chip 300. In addition, the pad portion 424p that does not vertically overlap with the second semiconductor chip 300 may be coupled to the offset first through-via 230s of the first semiconductor chip 200. In a region where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap with each other, the pad portion 424p may be aligned with the first through-via 230 and the second chip pad 325s, as shown in FIG. Figure 2As shown. In this case, one of the first penetration penetrations 230 and one of the second chip pads 325 may be commonly coupled to one of the pad portions 424p. In an embodiment, in an area where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap each other, the pad portion 424p may be aligned with one of the first penetration penetration 230 and the second chip pad 325. In this case, either the first penetration penetration 230 or the second chip pad 325 may be coupled to one of the pad portions 424p. The first penetration penetration 230 and the second chip pad 325 may be connected to each other through the pad portion 424p of the redistribution layer 420 or through the pad portion 424p and the wiring portion 424w. As an example, each of the wiring portions 424w may connect the pad portion coupled to the first penetration penetration 230 to the pad portion coupled to the second chip pad 325.

[0058] The thickness of the redistribution layer 420 may be greater than the thickness of a single interconnection layer in the second circuit layer 320. In detail, the first thickness TH1 of the redistribution pattern 424 of the redistribution layer 420 may be greater than the second thickness TH2 of the second interconnection pattern 324. Here, the thickness of the interconnection pattern may mean the thickness of a wiring portion, wherein the wiring portion may be a horizontally extending portion of the interconnection pattern.

[0059] According to an embodiment of the inventive concept, since the first semiconductor chip 200 and the second semiconductor chip 300 are stacked to form an offset stack structure, at least one of the second chip pads 325 of the second semiconductor chip 300 may not be aligned with the first through-via 230 of the first semiconductor chip 200. Specifically, according to the position of the second semiconductor chip 300, when viewed in a plan view, some of the second chip pads 325 may be placed in a region that does not overlap with the first semiconductor chip 200. However, since the redistribution layer 420 is disposed between the first semiconductor chip 200 and the second semiconductor chip 300, the first through-via 230 and the second chip pad 325 that may not be aligned with each other may be electrically connected. That is, the electrical connection characteristics between the first semiconductor chip 200 and the second semiconductor chip 300 may be improved, and a semiconductor package with improved electrical characteristics may be implemented.

[0060] In addition, the second semiconductor chip 300 can be electrically connected to the package substrate 100 through the redistribution layer 420 and the first through-via 230 of the first semiconductor chip 200. That is, when at least one offset second chip pad 325s of the second chip pads 325 of the second semiconductor chip 300 is arranged in a region that is not overlapped with the first semiconductor chip 200, such offset second chip pad 325s can be electrically connected to the package substrate 100 without a vertical connection structure (such as a conductive column or a bridge chip). Therefore, technical constraints (for example, technical constraints on the thickness and width of the conductive column) that may be required when forming a conductive column in the first mold layer 410 during the manufacturing process of the semiconductor package can be relaxed or eliminated. In addition, since the second semiconductor chip 300 can be connected to the package substrate 100 through the first through-via 230 in the first base layer 210 of the first semiconductor chip 200, the integration density of the interconnection structure that connects the second semiconductor chip 300 to the package substrate 100 can be increased. Therefore, the semiconductor package can be provided with a high integration density. For example, the pitch PI between the first through vias 230 and the pitch between the second through vias 330 may be in the range of about 4 micrometers (μm) to 30 μm. The third thickness TH3 of the first semiconductor chip 200 and the thickness of the second semiconductor chip 300 may be in the range of about 100 μm to 1000 μm.

[0061] The second mold layer 430 may be disposed on the redistribution layer 420. The second mold layer 430 may cover the redistribution layer 420. The first mold layer 410 and the second mold layer 430 may be spaced apart from each other by the redistribution layer 420. The second mold layer 430 on the redistribution layer 420 may surround the second semiconductor chip 300. The second mold layer 430 on the redistribution layer 420 may be provided to encapsulate the second semiconductor chip 300. For example, the second mold layer 430 may cover the side surface and the top surface of the second semiconductor chip 300. In an embodiment, the second mold layer 430 may expose the top surface of the second semiconductor chip 300. The bottom surface of the second mold layer 430 may be coplanar with the bottom surface 300a of the second semiconductor chip 300. In an embodiment, the redistribution layer 420 may cover the bottom surface of the second mold layer 430 and the bottom surface 300a of the second semiconductor chip 300.

[0062] In the following, the previous reference Figures 1 to 5 The elements described above may be identified by the same reference numerals without repeating their description. Figures 1 to 3 The technical features in the embodiments are different from the technical features.

[0063] Figure 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 5is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0064] Reference Figure 4 and Figure 5 , a redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the top surface 200b of the first semiconductor chip 200 and the bottom surface 300a of the second semiconductor chip 300. The redistribution layer 420 may include a plurality of interconnection layers that may be sequentially stacked. Each of the interconnection layers may include a redistribution insulation pattern 422 and a redistribution pattern 424 disposed therein. The redistribution patterns 424 of adjacent interconnection layers disposed in the interconnection layer may be electrically connected to each other.

[0065] Figure 4 An example in which the redistribution insulation pattern 422 is a single layer is shown, but in an embodiment, the redistribution layer 420 may include a plurality of redistribution insulation patterns 422 that may be vertically stacked. A redistribution pattern 424 may be provided in each of the redistribution insulation patterns 422 .

[0066] The redistribution pattern 424 may include a first pad portion 424p1 exposed on the bottom surface of the redistribution layer 420 and a second pad portion 424p2 exposed on the top surface of the redistribution layer 420. The redistribution pattern 424 may include a wiring portion 424w disposed in the redistribution layer 420. The wiring portion 424w may connect the first pad portion 424p1 to the second pad portion 424p2. The wiring portion 424w may connect one or more of the first pad portions 424p1 offset from the second pad portion 424p2 in a sequential manner. For example, the wiring portion 424w may connect the leftmost first pad portion of the first pad portions 424p1 on the first semiconductor chip 200 to the leftmost second pad portion of the second pad portions 424p2 on the second semiconductor chip 300.

[0067] Despite Figure 4 and Figure 5 The wiring portion 424w is depicted using a dotted line, but the dotted line schematically illustrates an electrical connection path of the wiring portion 424w, and the inventive concept is not limited to the illustrated shape and position of the wiring portion 424w.

[0068] The first pad portion 424p1 may be placed on the first semiconductor chip 200. The first pad portion 424p1 may be coupled to the first through via 230 at an interface between the redistribution layer 420 and the first semiconductor chip 200.

[0069] The second pad portion 424p2 may be disposed under the second semiconductor chip 300. The second pad portion 424p2 may be coupled to the second chip pad 325 at an interface between the redistribution layer 420 and the second semiconductor chip 300.

[0070] In a similar Figure 4 and Figure 5 In the case of the embodiment of the present invention, the redistribution layer 420 may include a plurality of interconnection layers including a wiring portion 424w. The wiring portion 424w may extend in a horizontal direction within the redistribution layer 420 to connect the first pad portion 424p1 and the second pad portion 424p2, and the degree of freedom of constructing the interconnection structure between the first semiconductor chip 200 and the second semiconductor chip 300 may be increased.

[0071] Figure 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. Figure 7 It is shown Figure 6 An enlarged cross-sectional view of portion "B" of FIG.

[0072] Reference Figure 6 and Figure 7 , the first semiconductor chip 200 may be disposed on the package substrate 100. The bottom surface of the first semiconductor chip 200 may be a rear surface 200b. The first semiconductor chip 200 may be disposed on the package substrate 100 in a face-up manner. The first semiconductor chip 200 may include a first base layer 210, a first circuit layer 220, and at least one first penetration via 230.

[0073] The first circuit layer 220 may be disposed on the top surface of the first base layer 210. The first circuit layer 220 may be electrically connected to an integrated device or an integrated circuit that may be formed in the first base layer 210. For example, the first circuit layer 220 may include a first insulating pattern 222 and a first interconnection pattern 224 disposed in the first insulating pattern 222. A portion of the first interconnection pattern 224 may be exposed on the top surface of the first circuit layer 220. The exposed portion of the first interconnection pattern 224 may be used as a first chip pad 225 of the first semiconductor chip 200. In an embodiment, a plurality of first chip pads 225 may be provided.

[0074] The first through via 230 may vertically penetrate the first base layer 210. The first through via 230 may include an end portion extending toward the front surface 200a of the first semiconductor chip 200 and connected to the first circuit layer 220. The first through via 230 may also include an opposite end portion exposed on the bottom surface of the first base layer 210.

[0075] The first semiconductor chip 200 may further include a rear pad 252 and a rear protective layer 254 .

[0076] The rear pads 252 may be disposed on the rear surface 200b of the first semiconductor chip 200. Each of the rear pads 252 on the rear surface 200b of the first semiconductor chip 200 may be connected to a corresponding one of the first penetration vias 230. The rear pads 252 may include a conductive material. For example, the rear pads 252 may be formed of or include at least one metal material (e.g., copper (Cu) and tungsten (W)).

[0077] The rear protective layer 254 may be disposed on the bottom surface of the first base layer 210. The rear protective layer 254 may cover the bottom surface of the first base layer 210. The rear protective layer 254 may surround the rear pad 252. Here, the bottom surface of the rear protective layer 254 and the bottom surface of the rear pad 252 may be substantially coplanar with each other, thereby forming a substantially flat surface. The rear protective layer 254 may include an insulating material. For example, the rear protective layer 254 may be formed of at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON), or include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). Alternatively, the rear protective layer 254 may include an adhesive material.

[0078] The first semiconductor chip 200 may be mounted on the package substrate 100 in a flip chip manner. For example, the first semiconductor chip 200 may be arranged so that the rear pad 252 faces the package substrate 100. That is, the first semiconductor chip 200 may be arranged so that the rear surface 200b of the first semiconductor chip 200 faces the package substrate 100. The first chip terminal 240 may be arranged between the rear pad 252 and the package substrate 100. The first chip terminal 240 may be coupled to the rear pad 252. The first chip terminal 240 may be electrically connected to the rear pad 252. The first semiconductor chip 200 may be connected to the package substrate 100 through the rear pad 252, the first chip terminal 240, and the substrate interconnection pattern 120.

[0079] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. Since the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked to form an offset stack structure, the position of the second chip pad 325 may be different from that of the first chip pad 225. In detail, the second chip pad 325 may not be vertically aligned with the first chip pad 225. For example, at least one offset first chip pad 225s among the first chip pads 225 may be spaced apart from the second semiconductor chip 300 in the opposite direction of the first direction D1. The offset second chip pad 325s among the second chip pads 325 may be spaced apart from the first semiconductor chip 200 in the first direction D1. In the region where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap each other, the second chip pad 325 may be aligned with the first chip pad 225. Alternatively, in the region where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap each other, the second chip pad 325 may not be vertically aligned with the first chip pad 225.

[0080] The redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may be in contact with the front surface 200a of the first semiconductor chip 200 and the bottom surface 300a of the second semiconductor chip 300.

[0081] The redistribution pattern 424 may be disposed in the redistribution insulating pattern 422. The redistribution pattern 424 may extend horizontally in the redistribution insulating pattern 422. The pad portion of the redistribution pattern 424 may be arranged at a position corresponding to the first chip pad 225 and the second chip pad 325. Therefore, the redistribution layer 420 may electrically connect the first chip pad 225 and the second chip pad 325 to each other.

[0082] The thickness of the redistribution layer 420 may be greater than the thickness of each interconnection layer in the first circuit layer 220 and the thickness of each interconnection layer in the second circuit layer 320. In detail, the first thickness TH1 of the redistribution pattern 424 of the redistribution layer 420 may be greater than the fourth thickness TH4 of the first interconnection pattern 224 and the second thickness TH2 of the second interconnection pattern 324.

[0083] According to an embodiment of the inventive concept, the front surface 200a of the first semiconductor chip 200 and the front surface 300a of the second semiconductor chip 300 may be directly connected to each other through the redistribution layer 420. Therefore, the length of the electrical connection path between the first semiconductor chip 200 and the second semiconductor chip 300 may be shortened, and thus, the semiconductor package may have improved electrical characteristics.

[0084] Figure 8is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept. Fig. 9 is a plan view illustrating a semiconductor package according to an embodiment of the inventive concept. Fig.10 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0085] Reference Figure 8 and Fig. 9 , the redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may be in contact with the top surface 200b of the first semiconductor chip 200 and the bottom surface 300a of the second semiconductor chip 300. Here, the redistribution layer 420 may cover the bottom surface 300a of the second semiconductor chip 300 and a portion of the top surface 200b of the first semiconductor chip 200. The redistribution layer 420 may cover the entire bottom surface 300a of the second semiconductor chip 300 and a portion of the top surface 200b of the first semiconductor chip 200. In detail, the redistribution layer 420 may expose a portion of the top surface 200b of the first semiconductor chip 200 that does not vertically overlap with the second semiconductor chip 300 (i.e., in a region beside the second semiconductor chip 300). The second mold layer 430 may surround the second semiconductor chip 300 and the redistribution layer 420. In an offset region that does not vertically overlap with the second semiconductor chip 300, the second mold layer 430 may contact an exposed portion of the top surface 200b of the first semiconductor chip 200. The first semiconductor chip 200 may expose a portion of the bottom surface of the redistribution layer 420 that does not overlap with the first semiconductor chip 200. The first mold layer 410 may contact an exposed portion of the bottom surface of the redistribution layer 420 in an offset region that does not vertically overlap with the first semiconductor chip 200. The second mold layer 430 may contact the first mold layer 410 in an offset region that does not vertically overlap with the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. In an embodiment, the redistribution layer 420 may be composed of a single interconnection layer. The interconnection layer may include a redistribution insulation pattern 422 and a redistribution pattern 424 in the redistribution insulation pattern 422.

[0086] Since the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked to form an offset stack structure, the pad portion 424p that may not vertically overlap with the first semiconductor chip 200 may be coupled to the second chip pad 325s of the second semiconductor chip 300. The first through vias 230 of the first semiconductor chip 200 that do not vertically overlap with the second semiconductor chip 300 may not contact the redistribution layer 420. In a region where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap with each other, one of the pad portions 424p may be commonly coupled to one of the first through vias 230 and one of the second chip pads 325s, as shown in FIG. Fig. 9 As shown. However, in an embodiment, one of the pad portions 424p may be coupled to either the first through-through 230 or the second chip pad 325. The first through-through 230 and the second chip pad 325 may be connected to each other through the pad portion 424p of the redistribution layer 420 or through the pad portion 424p and the wiring portion 424w. More specifically, the aligned first through-throughs and the second chip pads in the first through-through 230 and the second chip pad 325 may be connected to each other through the pad portion 424p of the redistribution layer 420. The offset first through-throughs and the second chip pads in the first through-through 230 and the second chip pad 325 may be connected to each other through the pad portion 424p and the wiring portion 424w.

[0087] Reference Fig. 9 , one or more wiring portions 424w may be connected to pad portions 424p adjacent in the first direction D1. One or more of the wiring portions 424w may be connected to pad portions 424p that are distant in the first direction D1 (eg, separated by one or more intermediate pad portions 424p).

[0088] Figure 8 and Fig. 9 An example is shown in which the first semiconductor chip 200 is disposed in a face-down manner, but the inventive concept is not limited to this example.

[0089] Reference Fig.10 , the first semiconductor chip 200 may be Figure 6 The first semiconductor chip 200 may be disposed on the package substrate 100 in the same or similar manner as described above. The bottom surface of the first semiconductor chip 200 may be a rear surface 200b. In an embodiment, the first semiconductor chip 200 may be disposed on the package substrate 100 in a face-up manner. The first semiconductor chip 200 may include a first base layer 210, a first circuit layer 220, and at least one first through-via 230.

[0090] The first semiconductor chip 200 may further include a rear pad 252 and a rear protective layer 254 .

[0091] Since the first semiconductor chip 200 and the second semiconductor chip 300 may be stacked to form an offset stack structure, the pad portions of the redistribution pattern 424 that do not vertically overlap with the first semiconductor chip 200 may be coupled to the offset second chip pads 325s of the second semiconductor chip 300. The offset first chip pads 225s of the first semiconductor chip 200 that do not vertically overlap with the second semiconductor chip 300 may not contact the redistribution layer 420. In a region where the first semiconductor chip 200 and the second semiconductor chip 300 vertically overlap with each other, one of the pad portions of the redistribution pattern 424 may be commonly coupled to one of the first chip pads 225 and one of the second chip pads 325. In an embodiment, one of the pad portions of the redistribution pattern 424 may be coupled to either the first chip pad 225 or the second chip pad 325.

[0092] Fig.11 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0093] Reference Fig.11 The redistribution layer may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer may include a first redistribution layer 420-1 that may be disposed on the top surface 200b of the first semiconductor chip 200 and a second redistribution layer 420-2 that may be disposed on the bottom surface 300a of the second semiconductor chip 300.

[0094] The first redistribution layer 420 - 1 may be provided to have a Figure 1 The first redistribution layer 420-1 may have a structure that is the same or similar to the redistribution layer 420 described above. For example, the first redistribution layer 420-1 may contact the top surface 200b of the first semiconductor chip 200. The first redistribution layer 420-1 may extend from an area on the first semiconductor chip 200 to an area on the first mold layer 410. The first redistribution layer 420-1 may cover the top surface 200b of the first semiconductor chip 200 and the top surface of the first mold layer 410. In an embodiment, the first redistribution layer 420-1 may be composed of a single interconnect layer. The interconnect layer may include a first redistribution insulation pattern 422-1 and a first redistribution pattern 424-1 in the first redistribution insulation pattern 422-1. The first redistribution pattern 424-1 may be coupled to the first through-vias 230 and 230s of the first semiconductor chip 200.

[0095] The second redistribution layer 420 - 2 may be provided to have a Figure 8The second redistribution layer 420-2 may have the same or similar structure as described above. For example, the second redistribution layer 420-2 may contact the bottom surface 300a of the second semiconductor chip 300. Here, the second redistribution layer 420-2 may cover the bottom surface 300a of the second semiconductor chip 300. The second redistribution layer 420-2 may cover the entire bottom surface 300a of the second semiconductor chip 300. The second mold layer 430 may surround the second semiconductor chip 300 and the second redistribution layer 420-2. In an embodiment, the second redistribution layer 420-2 may be composed of a single interconnect layer. The interconnect layer may include a second redistribution insulation pattern 422-2 and a second redistribution pattern 424-2 in the second redistribution insulation pattern 422-2. The second redistribution pattern 424-2 may be coupled to the second chip pad 325 of the second semiconductor chip 300.

[0096] The second redistribution layer 420-2 may be disposed on the first redistribution layer 420-1. The top surface of the first redistribution layer 420-1 and the bottom surface of the second redistribution layer 420-2 may contact each other. The second redistribution layer 420-2 may cover a portion of the top surface of the first redistribution layer 420-1. In detail, the second redistribution layer 420-2 may expose a portion of the top surface of the first redistribution layer 420-1 that does not vertically overlap with the second semiconductor chip 300. The second mold layer 430 may contact the exposed portion of the top surface of the first redistribution layer 420-1 in an offset region that does not vertically overlap with the second semiconductor chip 300. The first redistribution pattern 424-1 of the first redistribution layer 420-1 and the second redistribution pattern 424-2 of the second redistribution layer 420-2 may be connected to each other. The first semiconductor chip 200 and the second semiconductor chip 300 may be electrically connected to each other through the first redistribution layer 420-1 and the second redistribution layer 420-2.

[0097] Fig.12 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0098] Reference Fig.12 , a plurality of first semiconductor chips 200 may be provided. The first semiconductor chips 200 may be spaced apart from each other on the package substrate 100. For example, the first semiconductor chips 200 may be horizontally spaced apart from each other on the package substrate 100.

[0099] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. The second semiconductor chip 300 may be placed on the top surface of the first semiconductor chip 200. For example, the second semiconductor chip 300 may overlap with a portion of the plurality of first semiconductor chips 200. The second semiconductor chip 300 and one of the first semiconductor chips 200 may be arranged to form an offset stack structure. For example, when viewed in a plan view, a portion of the second semiconductor chip 300 may overlap with a first chip of the first semiconductor chip 200, and another portion of the second semiconductor chip 300 may overlap with a second chip of the first semiconductor chip 200.

[0100] The redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the top surface of the first semiconductor chip 200 and the bottom surface of the second semiconductor chip 300. The redistribution layer 420 may cover the top surface of the first semiconductor chip 200 and the top surface of the first mold layer 410. The redistribution layer 420 may be provided to form an electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include a redistribution insulating pattern 422 and a redistribution pattern 424 disposed in the redistribution insulating pattern 422. The redistribution pattern 424 may electrically connect the second chip pad 325 of the second semiconductor chip 300 to the first through-via 230 of the first semiconductor chip 200.

[0101] Fig.13 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0102] Reference Fig.13 , a plurality of second semiconductor chips 300 may be provided. The second semiconductor chips 300 may be spaced apart from each other on the first semiconductor chip 200. The second semiconductor chips 300 may be spaced apart from each other horizontally on the first semiconductor chip 200.

[0103] The second semiconductor chip 300 may be disposed on the first semiconductor chip 200. The second semiconductor chip 300 may be placed on the top surface of the first semiconductor chip 200. For example, the first semiconductor chip 200 may overlap with a portion of the plurality of second semiconductor chips 300. Each of the second semiconductor chip 300 and the first semiconductor chip 200 may be arranged to form an offset stack structure. For example, when viewed in a plan view, each of the second semiconductor chips 300 may include two portions, one of which overlaps with the first semiconductor chip 200, and the other of which protrudes laterally relative to the first semiconductor chip 200.

[0104] The redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the top surface of the first semiconductor chip 200 and the bottom surface of the second semiconductor chip 300. The redistribution layer 420 may cover the top surface of the first semiconductor chip 200 and the top surface of the first mold layer 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include a redistribution insulating pattern 422 and a redistribution pattern 424 disposed in the redistribution insulating pattern 422. The redistribution pattern 424 may electrically connect the second chip pad 325 of the second semiconductor chip 300 to the first through-via 230 of the first semiconductor chip 200.

[0105] Fig.14 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the inventive concept.

[0106] Reference Fig.14 , the second semiconductor chip 300 may have a different structure from the first semiconductor chip 200. For example, the width of the second semiconductor chip 300 may be greater than the width of the first semiconductor chip 200. Therefore, the second semiconductor chip 300 may include a protruding portion extending from the first semiconductor chip 200 in the first direction D1 and not vertically overlapping the first semiconductor chip 200. As an example, when viewed in a plan view, one or more of the second chip pads 325 of the second semiconductor chip 300 may be offset from the second chip pads 325s and may be disposed in a region next to the first semiconductor chip 200.

[0107] The redistribution layer 420 may be disposed between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may contact the top surface of the first semiconductor chip 200 and the bottom surface of the second semiconductor chip 300. The redistribution layer 420 may cover the top surface of the first semiconductor chip 200 and the top surface of the first mold layer 410. The redistribution layer 420 may be provided for electrical connection between the first semiconductor chip 200 and the second semiconductor chip 300. The redistribution layer 420 may include a redistribution insulating pattern 422 and a redistribution pattern 424 disposed in the redistribution insulating pattern 422. The redistribution pattern 424 may electrically connect the second chip pad 325 of the second semiconductor chip 300 to the first through-via 230 of the first semiconductor chip 200.

[0108] According to an embodiment of the present invention, since the redistribution layer 420 can be disposed between the first semiconductor chip 200 and the second semiconductor chip 300, an electrical connection structure can be easily formed between the first semiconductor chip 200 and the second semiconductor chip 300 even when the first semiconductor chip 200 and the second semiconductor chip 300 have different sizes from each other.

[0109] Fig.15 , Fig.16 , Fig.17 and Fig.18 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0110] Reference Fig.15 , a carrier substrate 900 may be provided. The carrier substrate 900 may be an insulating substrate (which may be formed of, or include, glass or a polymer) or a conductive substrate (which may be formed of, or include a metal material). An adhesive member may be provided on the top surface of the carrier substrate 900. In an embodiment, the adhesive member may include an adhesive tape.

[0111] The package substrate 100 may be formed on the carrier substrate 900. Hereinafter, a process of forming the package substrate 100 will be described in detail.

[0112] A lower insulating layer 910 may be disposed on the carrier substrate 900. The lower insulating layer 910 may be formed of or include at least one of an insulating polymer and a photoimageable polymer.

[0113] The external pad 130 may be formed in the lower insulating layer 910. For example, the lower insulating layer 910 may be patterned to form an opening in which the external pad 130 may be disposed, a seed layer may be conformally formed in the opening, and an electroplating process using the seed layer may be performed to form the external pad 130 filling the opening.

[0114] The substrate insulating layer 110 may be formed on the lower insulating layer 910. The substrate insulating layer 110 may be formed through a coating process (eg, a spin coating process or a slit coating process).

[0115] A substrate interconnection pattern 120 may be formed. For example, the substrate insulating layer 110 may be patterned to form an opening exposing the external pad 130, a barrier layer and a conductive layer may be formed on the substrate insulating layer 110 to fill the opening, and then a planarization process may be performed on the barrier layer and the conductive layer to form the substrate interconnection pattern 120. The substrate insulating layer 110 and the substrate interconnection pattern 120 formed by the above process may constitute a substrate interconnection layer. The process of forming a substrate interconnection layer may be repeated to form a package substrate 100 in which a plurality of substrate interconnection layers are stacked. The substrate interconnection pattern 120 in the uppermost one of the substrate interconnection layers may correspond to a substrate pad of the package substrate 100.

[0116] A first semiconductor chip 200 may be provided. The first semiconductor chip 200 may have a Figure 1 The first semiconductor chip 200 has the same or similar structure as described above.

[0117] The first semiconductor chip 200 may be mounted on the package substrate 100. For example, a solder ball may be provided on the first chip pad 225 of the first semiconductor chip 200. The first semiconductor chip 200 may be placed on the package substrate 100 in such a manner that the first chip pad 225 is aligned with the substrate interconnection pattern 120 of the package substrate 100. The first semiconductor chip 200 may be lowered downward to form contact between the solder ball and the substrate interconnection pattern 120, and thereafter, a reflow process may be performed on the solder ball to form a first chip terminal 240 connecting the first semiconductor chip 200 to the package substrate 100.

[0118] Reference Fig.16 , a first mold layer 410 may be formed on the package substrate 100. For example, a first molding material may be coated on the top surface of the package substrate 100 to encapsulate the first semiconductor chip 200, and thereafter, the first molding material may be hardened to form the first mold layer 410. The first mold layer 410 may cover the top surface of the package substrate 100, the side surfaces of the first semiconductor chip 200, and the rear surface of the first semiconductor chip 200. The first semiconductor chip 200 may not be exposed to the outside of the first mold layer 410.

[0119] A portion of the first mold layer 410 and a portion of the first semiconductor chip 200 may be removed. In detail, a thinning process may be performed on the first semiconductor chip 200. For example, a grinding or chemical mechanical polishing (CMP) process may be performed on the top surface of the first mold layer 410. Therefore, the rear surface of the first semiconductor chip 200 and the top surface of the first mold layer 410 may have a flat shape. As a result of the thinning process, the upper portion of the first mold layer 410 may be removed. That is, the rear surface of the first semiconductor chip 200 may be exposed to the outside by the thinning process. The rear surface of the first semiconductor chip 200 and the top surface of the first mold layer 410 may be substantially coplanar with each other, thereby forming a flat surface.

[0120] Reference Fig.17 , a redistribution layer 420 may be formed on the first mold layer 410 and the first semiconductor chip 200. For example, a redistribution insulating pattern 422 may be formed by coating or depositing an insulating material on the top surface of the first mold layer 410 and the rear surface of the first semiconductor chip 200. Thereafter, the redistribution insulating pattern 422 may be patterned to form an opening, a seed layer may be conformally formed in the opening, and an electroplating process using the seed layer may be performed to form a redistribution pattern 424 filling the opening. Some of the openings may be formed to expose the first through-via 230 of the first semiconductor chip 200. Such an opening may define an area for a pad portion of the redistribution pattern 424 to be connected to the first semiconductor chip 200. Other openings may be formed in an area beside the first semiconductor chip 200. The opening formed in the area beside the first semiconductor chip 200 may define an area for a pad portion of the redistribution pattern 424 that may be electrically connected to the second chip pad 325 of the second semiconductor chip 300. In an embodiment, during the formation of the openings in the redistribution insulating pattern 422 , trenches may be formed in the redistribution insulating pattern 422 . The trenches may connect the openings to each other. The trenches may define an area for a wiring portion of the redistribution pattern 424 .

[0121] Reference Fig.18 , the second semiconductor chip 300 may be disposed on the redistribution layer 420. For example, the second chip pad 325 of the second semiconductor chip 300 may be aligned with the redistribution pattern 424 of the redistribution layer 420. The second semiconductor chip 300 may be lowered downward to form contact between the second chip pad 325 and the redistribution pattern 424. The second chip pad 325 may be bonded to the redistribution pattern 424 at an interface between the second semiconductor chip 300 and the redistribution layer 420.

[0122] Reference Figure 1, a second mold layer 430 may be formed on the redistribution layer 420. For example, a second molding material may be coated on the top surface of the redistribution layer 420 to encapsulate the second semiconductor chip 300, and thereafter, the second molding material may be hardened to form the second mold layer 430. The second mold layer 430 may cover the top surface of the redistribution layer 420, the side surfaces of the second semiconductor chip 300, and the rear surface of the second semiconductor chip 300.

[0123] The carrier substrate 900 may be removed. Thus, the bottom surface of the package substrate 100 (eg, the external pads 130 of the package substrate 100 ) may be exposed to the outside.

[0124] The lower insulating layer 910 may be removed, and a substrate protection layer 140 may be formed under the package substrate 100. The substrate protection layer 140 under the substrate insulating layer 110 may cover the substrate interconnection pattern 120 and the external pad 130. Alternatively, an insulating layer may be additionally formed on the lower insulating layer 910 by, for example, a coating or deposition method. The lower insulating layer 910 together with the additional insulating layer may form the substrate protection layer 140.

[0125] Fig.19 , Fig. 20 and Fig.21 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0126] Reference Fig.19 , a second semiconductor chip 300 may be provided. The second semiconductor chip 300 may have the same Figure 8 The second semiconductor chip 300 has the same or similar structure as described above.

[0127] Reference Fig. 20, a redistribution layer 420 may be formed on the second semiconductor chip 300. For example, a redistribution insulating pattern 422 may be formed by coating or depositing an insulating material on the top surface of the second circuit layer 320 of the second semiconductor chip 300. Thereafter, the redistribution insulating pattern 422 may be patterned to form an opening, a seed layer may be conformally formed in the opening, and an electroplating process using the seed layer may be performed to form a redistribution pattern 424 filling the opening. Some of the openings may be formed to expose the second chip pad 325 of the second semiconductor chip 300. The opening formed to expose the second chip pad 325 of the second semiconductor chip 300 may define an area for a pad portion of the redistribution pattern 424 connected to the second semiconductor chip 300. Other openings may be formed in an area beside the second semiconductor chip 300. The opening formed in the area beside the second semiconductor chip 300 may define an area for a pad portion of the redistribution pattern 424 that may be electrically connected to the first chip pad 225 of the first semiconductor chip 200. In an embodiment, during the formation of the openings in the redistribution insulating pattern 422 , trenches may be formed in the redistribution insulating pattern 422 . The trenches may connect the openings to each other. The trenches may define an area for a wiring portion of the redistribution pattern 424 .

[0128] Reference Fig.21 , you can Fig.16 The second semiconductor chip 300 is disposed on the structure of the redistribution layer 420 (e.g., disposed on the first semiconductor chip 200 and the first mold layer 410). The redistribution pattern 424 of the redistribution layer 420 may be aligned with the first through-via 230 of the first semiconductor chip 200. Thereafter, the second semiconductor chip 300 may be lowered downward to form contact between the redistribution pattern 424 and the first through-via 230. The redistribution pattern 424 may be bonded to the first through-via 230 at an interface between the redistribution layer 420 and the first semiconductor chip 200.

[0129] Reference Figure 8 , a second mold layer 430 may be formed on the first mold layer 410. For example, a second molding material may be coated on the top surface of the first mold layer 410 and the rear surface 200 b of the first semiconductor chip 200 to encapsulate the second semiconductor chip 300, and thereafter, the second molding material may be hardened to form the second mold layer 430. The second mold layer 430 may cover the side surfaces of the redistribution layer 420, the side surfaces of the second semiconductor chip 300, and the rear surface of the second semiconductor chip 300.

[0130] The carrier substrate 900 may be removed. Thus, the bottom surface of the package substrate 100 (eg, the external pads 130 of the package substrate 100 ) may be exposed to the outside.

[0131] The lower insulating layer 910 may be removed, and a substrate protection layer 140 may be formed under the package substrate 100 .

[0132] Fig. 22 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0133] Reference Fig. 22 , you can Fig.16 The structure is set Fig. 20 Here, we can refer to Fig.16 The redistribution layer 420 manufactured by the described method may be referred to as a first redistribution layer 420-1 and may be referred to as a first redistribution layer 420-1. Fig. 20 The redistribution layer 420 manufactured by the described method may be referred to as a second redistribution layer 420 - 2 .

[0134] The second semiconductor chip 300 may be disposed on the first redistribution layer 420-1. For example, the second redistribution pattern 424-2 of the second redistribution layer 420-2 may be aligned with the first redistribution pattern 424-1 of the first redistribution layer 420-1. The second semiconductor chip 300 may be lowered downward to form contact between the first redistribution pattern 424-1 and the second redistribution pattern 424-2. The first redistribution pattern 424-1 and the second redistribution pattern 424-2 may be bonded to each other at an interface between the first redistribution layer 420-1 and the second redistribution layer 420-2. The first redistribution insulation pattern 422-1 and the second redistribution insulation pattern 422-2 may contact each other at an interface between the first redistribution layer 420-1 and the second redistribution layer 420-2.

[0135] Reference Fig.11 , a second mold layer 430 may be formed on the first redistribution layer 420-1. For example, a second molding material may be coated on the top surface of the first redistribution layer 420-1 to encapsulate the second semiconductor chip 300, and thereafter, the second molding material may be hardened to form the second mold layer 430. The second mold layer 430 may cover the side surfaces of the second redistribution layer 420-2, the side surfaces of the second semiconductor chip 300, and the rear surface of the second semiconductor chip 300. The second mold layer 430 may surround the side surfaces of the second redistribution layer 420-2, the side surfaces of the second semiconductor chip 300, and the rear surface of the second semiconductor chip 300.

[0136] The carrier substrate 900 may be removed. Thus, the bottom surface of the package substrate 100 (eg, the external pads 130 of the package substrate 100 ) may be exposed to the outside.

[0137] The lower insulating layer 910 may be removed, and a substrate protection layer 140 may be formed under the package substrate 100 .

[0138] In a semiconductor package according to an embodiment of the present invention, a redistribution layer may be provided between stacked semiconductor chips to electrically connect through-vias or chip pads to each other, wherein the through-vias or chip pads may not be aligned with each other. Thus, electrical connection characteristics between semiconductor chips may be improved, and a semiconductor package having improved electrical characteristics may be realized.

[0139] In addition, even when the chip pad of the upper semiconductor chip is arranged in the area next to the lower semiconductor chip, the upper chip pad can be connected to the package substrate without a vertical connection structure (such as a conductive column or a bridge chip). Therefore, the technical constraints (for example, technical constraints on the thickness and width of the conductive column) that may be required when forming the conductive column in the molding layer in the process of manufacturing the semiconductor package can be relaxed or eliminated. In addition, the integration density of the interconnection structure that connects the semiconductor chip to the package substrate can be increased. Therefore, a highly integrated semiconductor package can be realized.

[0140] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Package substrate; a lower semiconductor chip disposed on the package substrate; an upper semiconductor chip disposed on the lower semiconductor chip and horizontally offset from a portion of the lower semiconductor chip; as well as an interconnection layer disposed between the lower semiconductor chip and the upper semiconductor chip, wherein the interconnect layer covers the bottom surface of the upper semiconductor chip in a first region offset from the lower semiconductor chip, The upper semiconductor chip includes a first circuit layer disposed on a bottom surface of the upper semiconductor chip; and The thickness of the interconnection pattern of the first circuit layer is smaller than the thickness of the interconnection pattern of the interconnection layer.

2. The semiconductor package according to claim 1, further comprising: a first molding layer disposed on the package substrate to surround the lower semiconductor chip; as well as a second molding layer disposed on the first molding layer to surround the upper semiconductor chip, Wherein, the interconnection layer is disposed between the first molding layer and the bottom surface of the upper semiconductor chip.

3. The semiconductor package according to claim 2, wherein: The interconnection layer is disposed between the first mold layer and the second mold layer.

4. The semiconductor package according to claim 3, wherein: The lower semiconductor chip and the first mold layer are spaced apart from the upper semiconductor chip and the second mold layer by the interconnection layer.

5. The semiconductor package according to claim 2, wherein: The first mold layer and the second mold layer contact each other in a second region beside the upper semiconductor chip.

6. The semiconductor package according to claim 1, wherein: The lower semiconductor chip includes a second circuit layer disposed on a top surface of the lower semiconductor chip, The interconnect layer is directly connected to the first circuit layer and the second circuit layer, and The thickness of the interconnection pattern of the second circuit layer is smaller than the thickness of the interconnection pattern of the interconnection layer.

7. The semiconductor package according to claim 1, wherein: The lower semiconductor chip comprises: A second circuit layer disposed on a bottom surface of the lower semiconductor chip; and a plurality of first through-pieces, the plurality of first through-pieces being arranged to vertically penetrate the lower semiconductor chip, connected to the second circuit layer, and exposed on a top surface of the lower semiconductor chip, and The interconnect layer is directly connected to the first circuit layer and the first via.

8. The semiconductor package according to claim 1, wherein: The interconnect layer comprises: a first redistribution layer in contact with a top surface of the lower semiconductor chip; and a second redistribution layer in contact with a bottom surface of the upper semiconductor chip, wherein the first redistribution layer overlaps both the top surface of the lower semiconductor chip and the bottom surface of the upper semiconductor chip, and The second redistribution layer overlaps a bottom surface of the upper semiconductor chip and is offset from at least a portion of a top surface of the lower semiconductor chip.

9. The semiconductor package according to claim 1, wherein: The lower semiconductor chip includes a plurality of first through-pieces, the plurality of first through-pieces being arranged to vertically penetrate the lower semiconductor chip and connected to a second circuit layer of the lower semiconductor chip, The upper semiconductor chip includes a plurality of second through-holes and a plurality of chip pads, the plurality of second through-holes being arranged to vertically penetrate the upper semiconductor chip and be connected to the first circuit layer, the plurality of chip pads being arranged in the first circuit layer, and At least one of the chip pads is offset from the lower semiconductor chip when viewed in a plan view.

10. The semiconductor package according to claim 9, wherein: The interconnection pattern of the interconnection layer electrically connects the at least one of the chip pads to the first via.

11. A semiconductor package, comprising: Package substrate; A first semiconductor chip is disposed on the package substrate; a first molding layer disposed on the package substrate to surround the first semiconductor chip; a first interconnect layer covering a top surface of the first semiconductor chip and a top surface of the first mold layer; a second semiconductor chip on the first interconnect layer; a second molding layer disposed on the first interconnect layer to surround the second semiconductor chip; as well as a plurality of external terminals disposed on a bottom surface of the package substrate, wherein the second semiconductor chip is horizontally offset from the first semiconductor chip and vertically overlaps with a side surface of the first semiconductor chip, and The first semiconductor chip and the first mold layer are spaced apart from the second semiconductor chip and the second mold layer by the first interconnection layer.

12. The semiconductor package according to claim 11, wherein The first semiconductor chip comprises: A first circuit layer is provided on a surface of the first semiconductor chip; and a plurality of first through-holes, the plurality of first through-holes being arranged to vertically penetrate the first semiconductor chip and be coupled to the first circuit layer, Wherein, the second semiconductor chip comprises: A second circuit layer is disposed on a surface of the second semiconductor chip; and A plurality of second vias are disposed to vertically penetrate the second semiconductor chip and be coupled to the second circuit layer.

13. The semiconductor package according to claim 12, wherein: The first circuit layer is disposed on a top surface of the first semiconductor chip facing the second semiconductor chip, The second circuit layer is provided on a bottom surface of the second semiconductor chip facing the first semiconductor chip, and The first interconnect layer is coupled to the first circuit layer and the second circuit layer.

14. The semiconductor package according to claim 12, wherein: The first circuit layer is disposed on a bottom surface of the first semiconductor chip facing the package substrate, The second circuit layer is provided on a bottom surface of the second semiconductor chip facing the first semiconductor chip, and The first interconnection layer is coupled to the first vias and the second circuit layer exposed on a top surface of the first semiconductor chip.

15. The semiconductor package according to claim 12, wherein: A thickness of the interconnection pattern of the first circuit layer and a thickness of the interconnection pattern of the second circuit layer are smaller than a thickness of the interconnection pattern of the first interconnection layer.

16. The semiconductor package according to claim 12, further comprising a plurality of chip pads of the second circuit layer connected to the plurality of second vias, in, When viewed in a plan view, at least one of the chip pads of the second circuit layer is offset from a side surface of the first semiconductor chip, and The interconnection pattern of the first interconnection layer electrically connects the at least one of the chip pads connected to the second via to the first via.

17. The semiconductor package according to claim 11, further comprising a second interconnect layer disposed on a bottom surface of the second semiconductor chip, in, The second mold layer on the first interconnect layer surrounds the second semiconductor chip and the second interconnect layer.

18. The semiconductor package according to claim 17, wherein: The second interconnection layer is disposed between the first mold layer and the second semiconductor chip and between the first semiconductor chip and the second semiconductor chip, and a top surface of the first interconnection layer is exposed in a region beside the second semiconductor chip.

19. A semiconductor package, comprising: Package substrate; A first semiconductor chip is disposed on the package substrate, the first semiconductor chip comprises a first circuit layer and a plurality of first through-holes, the first circuit layer is disposed on a surface of the first semiconductor chip, and the plurality of first through-holes vertically penetrate the first semiconductor chip and are coupled to the first circuit layer; a first molding layer disposed on the package substrate to surround the first semiconductor chip; a second semiconductor chip disposed on the first semiconductor chip and offset from the first semiconductor chip, the second semiconductor chip comprising a second circuit layer and a plurality of second vias, the second circuit layer being disposed on a bottom surface of the second semiconductor chip, the plurality of second vias vertically penetrating the second semiconductor chip and coupled to the second circuit layer; a first interconnection layer disposed between the second circuit layer and the first semiconductor chip and between the second circuit layer and the first molding layer; as well as a second molding layer disposed on the first molding layer to surround the first interconnection layer and the second semiconductor chip, wherein the first interconnect layer exposes a top surface of the first semiconductor chip in a region beside the second semiconductor chip, The second semiconductor chip is connected to the first interconnect layer through a plurality of chip pads of the second circuit layer, When viewed in a plan view, at least one of the chip pads is disposed on a side surface of the first semiconductor chip, and The interconnection pattern of the first interconnection layer electrically connects the at least one of the chip pads to the first via.

20. The semiconductor package according to claim 19, wherein The thickness of the interconnection pattern of the second circuit layer is smaller than the thickness of the interconnection pattern of the first interconnection layer.

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