Packaging structure for improving sip packaging reliability of semiconductor chip

Abstract

The invention discloses a packaging structure for improving the sip packaging reliability of a semiconductor chip, and aims to solve the problems that in the existing SIP packaging technology, all bonding pads are arranged at the bottom, when two or more bonding pads are used for heat dissipation, the bonding pad gap is reduced, the welding failure risk is improved, meanwhile, due to the fact that the number of the bonding pads is increased, the use amount of soldering tin is increased, and the cost is reduced. And the cost is high. The packaging structure comprises a packaging body, a PCB substrate and a semiconductor chip main body, the PCB substrate comprises a PCB layer, and the upper surface of the PCB layer is provided with a plurality of top layer bonding pad pins. According to the packaging structure, a structure similar to a stamp hole is additionally arranged at the side edge position of the PCB substrate, the redundant structure of the stamp hole is cut off through a packaging cutting procedure, and finally, a bonding pad with the same thickness as the PCB substrate is additionally arranged at the side edge of the PCB substrate, so that side bonding pad pins are arranged on the four edges of a packaging body, the bonding pad is enlarged, the subsequent surface mounting and board mounting are firmer, and the packaging quality is improved. The product reliability is improved, the large current characteristic is increased, and the cost is low.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a packaging structure for improving the reliability of semiconductor chip SIP packaging. Background Art

[0002] System In a Package (SIP) is the best solution to integrate electronic circuits into a package. All integrated circuits contain power analog circuits and digital processing circuits. The power analog circuits require larger pads to provide sufficient current. In order to increase the pads and reduce the risk of poor contact, more power supply pads can only be added, resulting in more pins and making it more difficult to mount the chips on the board.

[0003] The existing SIP packaging technology, including BGA and LGA packaging, has pad pins, whether square pins, round pins, single divergent arrangement, or array regular arrangement, all of which are at the bottom. When some pins require a larger current or a larger heat dissipation area, two or more pads are required. This will result in a reduction in the pad gap due to the increase in pads, resulting in an increased risk of welding failure, and there is a large interference between analog signals and digital signals, requiring additional empty pins to cover the gap. At the same time, the increase in pads will increase the amount of solder used, resulting in higher costs. Summary of the invention

[0004] (1) Technical issues to be solved

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a packaging structure that improves the reliability of the SIP packaging of semiconductor chips. The packaging structure is intended to solve the technical problems that all the pads in the existing SIP packaging technology are at the bottom. When two or more pads are used for heat dissipation, the pad gap is reduced, resulting in an increased risk of welding failure. At the same time, the increase in the number of pads causes an increase in the amount of solder used, resulting in higher costs.

[0006] (2) Technical solution

[0007] In order to solve the above technical problems, the present invention provides a packaging structure for improving the reliability of semiconductor chip SIP packaging, the packaging structure includes a packaging body, a PCB substrate and a semiconductor chip body, the PCB substrate includes a PCB layer, the upper surface of the PCB layer is provided with a plurality of top-layer pad pins, the lower surface of the PCB layer is provided with a plurality of bottom-layer pad pins, the top-layer pad pins and the bottom-layer pad pins are electrically connected through side pad pins, and the bottom-layer pad pins and the side pad pins are exposed on the lower surface and side of the packaging body; and also includes a semiconductor chip body, the semiconductor chip body is installed inside the packaging body and is electrically connected to the plurality of top-layer pad pins.

[0008] Preferably, the package body is made of insulating epoxy resin material, and an outer surface of the package body is provided with grooves corresponding to the side pad pins.

[0009] Furthermore, the length of the side pad pin is smaller than the thickness of the package body, and the side pad pin is flush with the outer surface of the package body.

[0010] Furthermore, the thickness of the PCB layer is 1.7-2.2 mm, and the thickness of the top layer pad pin and the bottom layer pad pin is 0.15-0.25 mm.

[0011] Furthermore, the packaging method of the packaging structure includes the following steps:

[0012] Step 1: prepare a PCB substrate with a top-layer circuit and a bottom-layer circuit, and then use a mask material to divide the top-layer circuit and the bottom-layer circuit into multiple mounting areas;

[0013] Step 2: Process the top-layer circuit and the bottom-layer circuit by etching, then remove the mask material to form the top-layer pad pin, the bottom-layer pad pin and the cutting path, and make the cutting path located between two adjacent mounting areas;

[0014] Step 3: Perform via processing at the junction of the top pad pin and the cutting path to form a through hole, and then fill the through hole with conductive material to form a side pad pin, which connects the top pad pin and the bottom pad pin of the PCB substrate;

[0015] Step 4: Place the semiconductor chip body on the upper surface of the PCB layer by welding material, and then connect it to the top layer pad pins by using metal wires;

[0016] Step 5: Control the cutting equipment to cut the PCB substrate along the planned cutting path to obtain an independent structure with the semiconductor chip body welded thereon;

[0017] Step 6: Use the injection molding method to use the plastic packaging material to cover and seal the top layer pad pins, the semiconductor chip body and the metal wires. After the plastic packaging is completed, bake and solidify to form a reliable semiconductor chip packaging structure.

[0018] Furthermore, the top layer pad pins and the bottom layer pad pins are both located inside the mounting area.

[0019] Furthermore, the mask material includes a pin mask covering the top pad pins and the bottom pad pins, the plurality of pin masks are formed with horizontal mask strips and vertical mask strips, and the mounting area is surrounded by the horizontal mask strips and the vertical mask strips.

[0020] Furthermore, in step three, when filling the conductive material in the through hole, the dust on the inner wall is cleaned, and then the PCB substrate is placed on the flat plate, and then filled with the conductive material containing metal powder and solvent. After the conductive material is cured, the upper and lower sides of the PCB substrate are milled flat.

[0021] Furthermore, the through hole passes through the top pad pin, the PCB layer and the bottom pad pin, the through hole is a long strip structure and is perpendicular to the PCB substrate, and is close to the side pad pin when the PCB substrate is cut in step five.

[0022] Furthermore, the cutting device is one of laser cutting and plasma ray cutting.

[0023] (3) Beneficial effects

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The package body of the present invention has side solder pad pins on the four sides. If there is excessive tin at the bottom solder pad pins during welding, part of the tin will be attached to the exposed side solder pad pins. Due to the tin creeping phenomenon, the excess tin will be guided to the side solder pad pins, thereby avoiding the situation where the soldering gap is reduced and the welding failure is caused. There is no possibility of interference or short circuit between the solder pads, the amount of solder used is reduced, the welding quality is greatly improved, and the cost is low.

[0026] In the above scheme, the packaging structure adds a structure similar to a stamp hole on the side of the PCB substrate, and the excess structure of the stamp hole is removed through the packaging cutting process, and finally a pad with the same thickness as the board is added to the side of the PCB substrate, so that the four sides of the package body have side pad pins, the pad is enlarged, and the subsequent patch is more securely mounted on the board, thereby improving product reliability and increasing high current characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of a structure of a PCB substrate using a mask material for improving the reliability of semiconductor chip SIP packaging;

[0028] Figure 2 A schematic diagram of a structure in which a mask material is uncovered on a PCB substrate of a packaging structure for improving the reliability of a semiconductor chip SIP package;

[0029] Figure 3 A schematic diagram of a top view of a PCB substrate with a through hole for improving the reliability of semiconductor chip SIP packaging;

[0030] Figure 4 A schematic cross-sectional structure diagram of a PCB substrate with through holes provided in order to improve the reliability of semiconductor chip SIP packaging;

[0031] Figure 5 A schematic diagram of a structure in which a conductive material is filled into a through hole of a packaging structure in order to improve the reliability of a semiconductor chip SIP packaging;

[0032] Figure 6 A schematic diagram of the structure of the PCB substrate after cutting for improving the reliability of the semiconductor chip SIP packaging;

[0033] Figure 7 A schematic diagram of the structure of a welded semiconductor chip body in a packaging structure for improving the reliability of semiconductor chip SIP packaging;

[0034] Figure 8 A schematic diagram of the structure of a packaged semiconductor chip body for improving the reliability of semiconductor chip SIP packaging;

[0035] Fig. 9 A schematic diagram of the front view of a packaging structure for improving the reliability of a semiconductor chip SIP package;

[0036] Fig.10 A schematic diagram of the three-dimensional structure of a packaging structure for improving the reliability of SIP packaging of semiconductor chips.

[0037] The markings in the accompanying drawings are: 1. package body; 2. PCB substrate; 3. PCB layer; 4. top pad pin; 5. bottom pad pin; 6. side pad pin; 7. semiconductor chip body; 11. mounting area; 12. cutting path; 13. through hole; 14. metal wire; 15. mask material; 16. plastic packaging material; 1501. horizontal mask strip; 1502. vertical mask strip; 1503. pin mask. DETAILED DESCRIPTION

[0038] This specific implementation is a packaging structure that improves the reliability of semiconductor chip SIP packaging. Its structural schematic diagram is shown in Figure 1-Figure 10 As shown, the packaging structure includes a packaging body 1, a PCB substrate 2 and a semiconductor chip body 7, the PCB substrate 2 includes a PCB layer 3, a plurality of top-layer pad pins 4 are arranged on the upper surface of the PCB layer 3, a plurality of bottom-layer pad pins 5 are arranged on the lower surface of the PCB layer 3, the top-layer pad pins 4 and the bottom-layer pad pins 5 are electrically connected through the side pad pins 6, the bottom-layer pad pins 5 and the side pad pins 6 are exposed on the lower surface and the side of the packaging body 1, and also includes a semiconductor chip body 7, the semiconductor chip body 7 is installed inside the packaging body 1 and is electrically connected to the plurality of top-layer pad pins 4, so that the four sides of the packaging body 1 have welding pin positions, which improves product stability, simplifies PCB design layout, can quickly separate digital and analog signals, and reduce the difficulty of post-process production.

[0039] like Fig.10As shown, in this embodiment, the package body 1 is made of insulating epoxy resin material, and a groove corresponding to the side pad pin 6 is formed on the outer surface of the package body 1.

[0040] Such arrangement of the package body 1 can prevent the electronic components from being corroded by external water vapor and oxidized by oxygen. The package body 1 can also be made of materials such as plastic packaging, sealing resin or ceramic packaging.

[0041] like Fig. 9 and Fig.10 As shown, in this embodiment, the length of the side pad pin 6 is smaller than the thickness of the package body 1 , and the side pad pin 6 is flush with the outer surface of the package body 1 .

[0042] When soldering in this way, if there is excessive tin at the bottom pad pin 5, part of the tin will stick to the exposed side pad pin 6. Due to the tin creeping phenomenon, the excess tin will be guided to the side pad pin 6.

[0043] In this embodiment, the thickness of the PCB layer 3 is 1.7-2.2 mm, the thickness of the top pad pin 4 and the bottom pad pin 5 is 0.15-0.25 mm, wherein the thickness of the PCB layer 3 is specifically 2 mm, and the thickness of the top pad pin 4 and the bottom pad pin 5 is 0.2 mm.

[0044] like Figure 1-10 As shown, in this embodiment, the packaging method of the packaging structure includes the following steps:

[0045] Step 1: prepare a PCB substrate 2 having a top-layer circuit and a bottom-layer circuit, and then use a mask material 15 to divide the top-layer circuit and the bottom-layer circuit into a plurality of mounting areas 11;

[0046] Step 2: Process the top and bottom circuits by etching, then remove the mask material 15 to form the top pad pins 4, the bottom pad pins 5 and the cutting path 12, and make the cutting path 12 located between two adjacent mounting areas 11;

[0047] Step 3: Perform via processing at the junction of the top pad pin 4 and the cutting path 12 to form a through hole 13. The added through hole 13 is similar to the structure of a stamp hole. Then, fill the through hole 13 with conductive material to form a side pad pin 6. The side pad pin 6 connects the top pad pin 4 and the bottom pad pin 5 of the PCB substrate 2.

[0048] Step 4: Place the semiconductor chip body 7 on the upper surface of the PCB layer 3 by welding material, and then connect it to the top pad pin 4 by using a metal wire 14. The metal wire 14 can be a gold wire or a copper wire, etc. The semiconductor chip body 7 here can be various types of chips;

[0049] Step 5: Control the cutting equipment to cut the PCB substrate 2 along the planned cutting path 12 to obtain an independent structure with the semiconductor chip body 7 welded thereon;

[0050] Step 6: Use the injection molding method to cover and seal the top pad pins 4, the semiconductor chip body 7 and the metal wires 14 with the plastic packaging material 16. After the plastic packaging is completed, bake and solidify to form a reliable semiconductor chip packaging structure.

[0051] This setting uses the cooperation of PCB stamp hole process + semiconductor packaging cutting process to add auxiliary pads on the four sides of the BGA or LGA package of the semiconductor SIP packaging technology, so that it has the same side pins as DFN or QFN package, thereby improving product reliability.

[0052] like Figure 1 and Figure 2 As shown, in this embodiment, the top layer pad pins 4 and the bottom layer pad pins 5 are both located inside the mounting area 11 .

[0053] like Figure 1 and Figure 2 As shown, in this embodiment, the mask material 15 includes a pin mask 1503 covering the top pad pin 4 and the bottom pad pin 5, and the multiple pin masks 1503 form a horizontal mask strip 1501 and a vertical mask strip 1502, and the mounting area 11 is surrounded by the horizontal mask strip 1501 and the vertical mask strip 1502.

[0054] This arrangement will etch the top and bottom lines of the PCB substrate 2, and the masked parts of the mask material 15 will be retained.

[0055] In this embodiment, in step three, when filling the conductive material in the through hole 13, the dust on the inner wall is cleaned, and then the PCB substrate 2 is placed on the flat plate, and then filled with conductive material containing metal powder and solvent. After the conductive material is solidified, the upper and lower sides of the PCB substrate 2 are milled flat.

[0056] This arrangement reduces impurities in the conductive material, and the conductive material can better electrically connect the top pad pin 4 and the bottom pad pin 5 , while the surface after milling is smoother.

[0057] like Figure 3 and Figure 4 As shown, in this embodiment, the through hole 13 passes through the top pad pin 4, the PCB layer 3 and the bottom pad pin 5. The through hole 13 is a long strip structure and is perpendicular to the PCB substrate 2. When the PCB substrate 2 is cut in step five, it is close to the side pad pin 6.

[0058] This arrangement allows the side pad pins 6 to be exposed during the cutting process, making packaging more convenient.

[0059] In this embodiment, the cutting device is one of laser cutting, blade cutting or plasma ray cutting.

[0060] This arrangement can obtain an independent structure with the semiconductor chip body 7 welded thereto, while the cut surface is smoother and the appearance quality is better.

[0061] According to the technical solution provided by the present invention, the four sides of the package body 1 are provided with side solder pad pins 6. During welding, if there is excessive tin at the bottom solder pad pins 5, part of the tin will be stained with the exposed side solder pad pins 6. Due to the tin creeping phenomenon, the excess tin will be guided to the side solder pad pins 6, thereby avoiding the situation where the soldering gap is reduced and the welding failure is caused. There is no possibility of interference or short circuit between the pads, the amount of solder is reduced, and the welding quality is greatly improved. The packaging structure adds a structure similar to a stamp hole at the side position of the PCB substrate 2, and the excess structure of the stamp hole is removed through the packaging cutting process, and finally the side of the PCB substrate 2 is completed with a solder pad with the same thickness as the board, so that the four sides of the package body 1 are provided with side solder pad pins 6, and the solder pad is enlarged.

[0062] All technical features in this embodiment can be freely combined according to actual needs.

[0063] The above embodiments are preferred implementation schemes of the present invention. In addition, the present invention may also be implemented in other ways. Any obvious replacement without departing from the concept of the present technical solution is within the protection scope of the present invention.

Claims

1. A packaging structure for improving the reliability of semiconductor chip SIP packaging, characterized in that: The packaging structure comprises a packaging body (1) and a PCB substrate (2), wherein the PCB substrate (2) comprises a PCB layer (3), wherein the upper surface of the PCB layer (3) is provided with a plurality of top-layer pad pins (4), and the lower surface of the PCB layer (3) is provided with a plurality of bottom-layer pad pins (5), wherein the top-layer pad pins (4) and the bottom-layer pad pins (5) are electrically connected via side pad pins (6), and the bottom-layer pad pins (5) and the side pad pins (6) are exposed on the lower surface and side surfaces of the packaging body (1); It also includes a semiconductor chip body (7), which is mounted inside the package (1) and is electrically connected to a plurality of top-layer pad pins (4).

2. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 1, characterized in that: The package body (1) is made of insulating epoxy resin material, and an outer surface of the package body (1) is provided with a groove corresponding to the side pad pin (6).

3. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 1, characterized in that: The length of the side pad pin (6) is less than the thickness of the package body (1), and the side pad pin (6) is flush with the outer surface of the package body (1).

4. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 1, characterized in that: The thickness of the PCB layer (3) is 1.7-2.2 mm, and the thickness of the top layer solder pad pins (4) and the bottom layer solder pad pins (5) are 0.15-0.25 mm.

5. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 1, characterized in that: The packaging method of the packaging structure comprises the following steps: Step 1: preparing a PCB substrate (2) having a top-layer circuit and a bottom-layer circuit, and then using a mask material (15) to divide the top-layer circuit and the bottom-layer circuit into a plurality of mounting areas (11); Step 2: Processing the top-layer circuit and the bottom-layer circuit by etching, then removing the mask material (15) to form the top-layer pad pin (4), the bottom-layer pad pin (5) and the cutting path (12), and making the cutting path (12) located between two adjacent mounting areas (11); Step 3: Perform via processing at the junction of the top-layer pad pin (4) and the cutting path (12) to form a through hole (13), and then fill the through hole (13) with conductive material to form a side pad pin (6), and the side pad pin (6) connects the top-layer pad pin (4) and the bottom-layer pad pin (5) of the PCB substrate (2); Step 4: placing the semiconductor chip body (7) on the upper surface of the PCB layer (3) by means of welding material, and then connecting it to the top layer pad pin (4) by means of metal wires (14); Step 5: Controlling the cutting equipment to cut the PCB substrate (2) along the planned cutting path (12) to obtain an independent structure welded with the semiconductor chip body (7); Step 6: Use an injection molding method to encapsulate the top layer pad pins (4), the semiconductor chip body (7) and the metal wires (14) with a plastic encapsulation material (16). After the plastic encapsulation is completed, the materials are baked and cured to form a reliable semiconductor chip packaging structure.

6. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 4, characterized in that: The top-layer solder pad pins (4) and the bottom-layer solder pad pins (5) are both located inside the mounting area (11).

7. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 1, characterized in that: The mask material (15) comprises a pin mask (1503) covering a top layer solder pad pin (4) and a bottom layer solder pad pin (5), a plurality of the pin masks (1503) form a horizontal mask strip (1501) and a vertical mask strip (1502), and the mounting area (11) is surrounded by the horizontal mask strip (1501) and the vertical mask strip (1502).

8. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 1, characterized in that: In the step 3, when filling the through hole (13) with the conductive material, the dust on the inner wall is cleaned, and then the PCB substrate (2) is placed on the flat plate, and then filled with the conductive material containing metal powder and solvent. After the conductive material is solidified, the upper and lower sides of the PCB substrate (2) are milled flat.

9. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 8, characterized in that: The through hole (13) passes through the top pad pin (4), the PCB layer (3) and the bottom pad pin (5); the through hole (13) is a long strip structure and is perpendicular to the PCB substrate (2); when the PCB substrate (2) is cut in step five, it is close to the side pad pin (6).

10. The packaging structure for improving the reliability of semiconductor chip SIP packaging according to claim 9, characterized in that: The cutting device is one of laser cutting and plasma ray cutting.

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