High-integration-level semiconductor packaging structure and manufacturing method thereof

Abstract

The invention relates to a high-integration-level semiconductor packaging structure and a manufacturing method thereof. The structure comprises a substrate; a high-performance power supply heat dissipation module and a deep groove capacitor module, wherein the high-performance power supply heat dissipation module comprises a micro-channel; a plastic package layer; a redistribution layer; the chip modules comprise a first chip module, a second chip module and a third chip module; underfill glue; the micro-channel inlet and the micro-channel outlet are connected with the micro-channel; and welding balls. According to the high-integration-level semiconductor packaging structure provided by the invention, the high-performance power supply heat dissipation module containing the micro-channel is integrated in the cavity of the substrate, and the chip module is subjected to rapid heat dissipation through the bump, the rewiring layer and the micro-channel, so that the heat dissipation capability is remarkably improved; the gate driving layer and the power transistor layer are vertically connected with each other through the silicon through hole and are connected with the substrate, so that the power supply efficiency is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a high-integration semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] Applications such as artificial intelligence and high-performance computing have increasing demands for bandwidth, storage, high-power heat dissipation, large power supplies, and capacitor decoupling. Currently, 2.5D packaging based on adapters is often used to integrate high-performance chips and HBM (High Bandwidth Memory). However, as the number of integrated HBMs increases and chip performance gradually improves, the integration of high-performance chips and HBMs will be limited by the area of ​​the adapter, D2D (Die to Die) high-speed interconnection, power supply, and heat dissipation capacity. Among them, high-performance chips often use DRAM stacked directly on top of high-power AS ICs, so the demand for bottom heat dissipation increases, and the conventional heat dissipation covers, heat sinks, and air cooling methods are difficult to meet the high heat dissipation capacity and heat dissipation efficiency requirements of high-performance chips. In addition, in order to meet the bandwidth and storage requirements of high-performance chips, D2D high-speed interconnection with more HBMs is required, and the requirements for large power supplies and power decoupling are met. Summary of the invention

[0003] In view of some or all of the problems in the prior art, the present invention provides a highly integrated semiconductor packaging structure, which includes:

[0004] A substrate, the substrate comprising a substrate bottom, a substrate middle and a substrate top, a plurality of cavities arranged in the substrate, the sides of the plurality of cavities being the substrate middle and the substrate top, and the lower surfaces of the plurality of cavities being the substrate middle;

[0005] A high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged in the plurality of cavities, wherein the high-performance power supply and heat dissipation module comprises a microchannel;

[0006] A plastic sealing layer, wherein the plastic sealing layer seals and covers the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module;

[0007] A redistribution layer, the redistribution layer is arranged on the upper surface of the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module, and the redistribution layer is electrically connected to the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module;

[0008] Chip modules, the chip modules comprising a first chip module, a second chip module and a third chip module, arranged on the upper surface of the redistribution layer, the chip modules being electrically connected to the redistribution layer via bumps;

[0009] Bottom filling glue, filling the bottom of the chip module;

[0010] A microchannel inlet and a microchannel outlet are arranged in the redistribution layer, and the microchannel inlet and the microchannel outlet are interconnected with the microchannel to achieve inflow and outflow of cooling liquid;

[0011] Solder balls are arranged on the lower surface of the bottom of the substrate.

[0012] Furthermore, the bottom of the substrate comprises a first interconnection circuit layer; and / or

[0013] The middle portion of the substrate comprises a second interconnection circuit layer; and / or

[0014] The top of the substrate includes a third interconnection line layer.

[0015] Furthermore, the high-performance power supply and heat dissipation module includes:

[0016] Power transistor layer;

[0017] a bonding layer, the bonding layer being arranged on an upper surface of the power transistor layer;

[0018] A gate driving layer, wherein the gate driving layer is arranged on an upper surface of the bonding layer, and the gate driving layer is bonded to the power transistor layer through the bonding layer;

[0019] a fourth interconnection circuit layer, wherein the fourth interconnection circuit layer is arranged on an upper surface of the gate driving layer;

[0020] Through Silicon Via, wherein the through silicon via runs through the high-performance power supply and heat dissipation module;

[0021] A microchannel is arranged in the power transistor layer, the gate drive layer and the bonding layer.

[0022] Furthermore, the first chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or

[0023] The second chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or

[0024] The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

[0025] The present invention also provides a method for manufacturing a highly integrated semiconductor packaging structure, the method comprising the following steps:

[0026] A temporary bonding layer is formed on the upper surface of the slide;

[0027] Arranging a substrate on the upper surface of the temporary bonding layer, the substrate comprising a substrate bottom, a substrate middle and a substrate top, and a plurality of cavities arranged in the substrate;

[0028] In the plurality of cavities, a high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged, wherein the high-performance power supply and heat dissipation module comprises a microchannel;

[0029] Making a plastic encapsulation layer, encapsulating and covering the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module, thinning the plastic encapsulation layer to expose the interconnection pads on the top of the substrate, the interconnection pads on the top of the high-performance power supply and heat dissipation module and the interconnection pads on the top of the deep trench capacitor module;

[0030] Making a redistribution layer on the upper surfaces of the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module;

[0031] On the upper surface of the redistribution layer, a chip module is arranged, wherein the chip module includes a first chip module, a second chip module and a third chip module, and the chip module is electrically connected to the redistribution layer through a bump;

[0032] Filling the bottom of the chip module with bottom filling glue;

[0033] Punching holes at positions of the redistribution layer corresponding to the inlet and outlet of the microfluidic channel to form the inlet and outlet of the microfluidic channel;

[0034] The carrier is removed, the substrate is cut, and solder balls are arranged on the lower surface of the bottom of the substrate to form a highly integrated semiconductor packaging structure.

[0035] Further, the carrier is glass or silicon wafer or metal plate; and / or

[0036] The temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride or organic bonding glue.

[0037] Furthermore, the plastic encapsulation is injection molding; and / or

[0038] The material of the plastic sealing layer is epoxy resin.

[0039] Furthermore, the redistribution layer includes a plurality of dielectric layers and a plurality of metal layers.

[0040] Furthermore, the first chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or

[0041] The second chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or

[0042] The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

[0043] Further, the carrier is removed using mechanical separation or thermal sliding or laser separation.

[0044] The technical solution provided by the present invention has the following beneficial effects:

[0045] 1. The highly integrated semiconductor packaging structure provided by the present invention integrates a high-performance power supply and heat dissipation module containing microchannels in the substrate cavity. The chip module quickly dissipates heat through bumps, redistribution layers and microchannels, which can significantly improve the heat dissipation capacity. In addition, the heat is dissipated from the bottom of the chip module, which does not interfere with the normal operation of the chip module.

[0046] 2. The highly integrated semiconductor packaging structure provided by the present invention integrates a high-performance power supply and heat dissipation module in the substrate cavity. The gate drive layer and the power transistor layer are vertically interconnected through silicon vias and interconnected with the substrate, which can significantly improve the power supply efficiency and reduce power loss.

[0047] 3. The highly integrated semiconductor packaging structure provided by the present invention integrates a deep trench capacitor (DTC) module or an inductor module in the substrate cavity, which can significantly improve the power decoupling performance and power integrity performance.

[0048] 4. The highly integrated semiconductor packaging structure provided by the present invention arranges an interconnection line layer on top of a high-performance power supply and heat dissipation module. The chip module can achieve fast D2D interconnection through bumps, a redistribution layer and an interconnection line layer to meet the bandwidth and storage requirements of high-performance chips.

[0049] 5. The highly integrated semiconductor packaging structure provided by the present invention adopts a large-size cavity substrate instead of an adapter plate, which can break through the size limitation of the adapter plate, accommodate more chip modules, and significantly improve bandwidth and storage capacity.

[0050] 6. The highly integrated semiconductor packaging structure provided by the present invention embeds a high-performance power supply and heat dissipation module in the substrate cavity, and the substrate warping is smaller than that of the original substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0052] Figure 1 A schematic diagram showing a highly integrated semiconductor package structure according to an embodiment of the present invention;

[0053] Figure 2 A schematic diagram showing a high-performance power supply and heat dissipation module according to an embodiment of the present invention is shown;

[0054] Figure 3 A schematic diagram showing a process of a method for manufacturing a highly integrated semiconductor packaging structure according to an embodiment of the present invention; and

[0055] Figure 4a-4i A cross-sectional schematic diagram of a process for forming a highly integrated semiconductor packaging structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0056] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments can be implemented without one or more specific details or with other replacement and / or additional methods, materials or components. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid blurring the inventive point of the present invention. Similarly, for the purpose of explanation, specific quantities, materials and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn in correct proportions.

[0057] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.

[0058] In this specification, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." only indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0059] In this specification, unless otherwise specified, "upper surface", "lower surface" and "side surface" are only used to describe and distinguish surfaces of the same component.

[0060] In this specification, unless otherwise specified, the quantifiers "a", "an" do not exclude the presence of a plurality of elements, and the quantifiers "plurality" and "multiple" refer to one or more than one elements.

[0061] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.

[0062] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0063] High-performance processing chips have high requirements for bandwidth, storage, high power consumption heat dissipation, large power supply and capacitor decoupling. Conventional 2.5D packaging based on Si adapters is limited by the area and heat dissipation of adapters. The present invention provides a highly integrated semiconductor packaging structure, in which a high-performance power supply heat dissipation module containing microchannels is integrated in a substrate cavity, and the chip module is rapidly cooled by bumps, a rewiring layer and microchannels, significantly improving the heat dissipation capacity; the gate drive layer and the power transistor layer are vertically interconnected by silicon through vias and interconnected with the substrate, significantly improving the power supply efficiency and reducing power loss; a deep trench capacitor module or an inductor module is integrated in the substrate cavity, which can significantly improve the power decoupling performance and power integrity performance; an interconnection line layer is arranged on the top of the high-performance power supply heat dissipation module, and the chip module can achieve fast D2D interconnection through bumps, a rewiring layer and an interconnection line layer, meeting the bandwidth and storage requirements of high-performance chips.

[0064] Figure 1 A schematic diagram of a highly integrated semiconductor packaging structure of an embodiment of the present invention is shown. The highly integrated semiconductor packaging structure includes a substrate, a high-performance power supply and heat dissipation module, a deep trench capacitor module, a plastic encapsulation layer, a redistribution layer, a chip module, a bottom filling glue, a microchannel inlet, a microchannel outlet and solder balls.

[0065] like Figure 1 As shown, the substrate includes a substrate bottom 103, a substrate middle 104 and a substrate top 105. The substrate is dug to form a plurality of cavities. The sides of the plurality of cavities are the substrate middle and the substrate top, and the bottom surface of the plurality of cavities is the substrate middle, that is, the substrate middle is partially dug but not dug through. In one embodiment of the present invention, the substrate bottom 103 includes a first interconnection circuit layer; the substrate middle 104 includes a second interconnection circuit layer; the substrate top 105 includes a third interconnection circuit layer, and the substrate top 105 also includes an interconnection pad, and the interconnection pad of the substrate top 105 is electrically connected to the redistribution layer; the first interconnection circuit layer, the second interconnection circuit layer and the third interconnection circuit layer are electrically connected.

[0066] like Figure 1 As shown, the high-performance power supply and heat dissipation module 106 is arranged in the cavity of the substrate. Figure 2FIG. 1 is a schematic diagram showing a high-performance power supply and heat dissipation module according to an embodiment of the present invention. Figure 2 As shown, the high-performance power supply and heat dissipation module 106 includes a through silicon via 1061, a microchannel 1062, a fourth interconnection line layer 1063, a gate drive layer 1064, a bonding layer 1065, and a power transistor layer 1066. The through silicon via 1061 runs through the high-performance power supply and heat dissipation module. The microchannel 1062 is arranged in the power transistor layer 1066, the gate drive layer 1064 and the bonding layer 1065. The fourth interconnection line layer 1063 is arranged on the upper surface of the gate drive layer 1064, and an interconnection pad is arranged on the top of the fourth interconnection line layer 1063. The bonding layer 1065 is arranged on the upper surface of the power transistor layer 1066. The power transistors are Power Transistors, the gate drivers are Gate Drivers, and the gate driver layer 1064 is arranged on the upper surface of the bonding layer 1065. The gate driver layer 1064 is bonded to the power transistor layer 1066 through the bonding layer 1065. The bonding layer 1065 is preferably silicon oxide or silicon nitride or silicon oxynitride, and the bonding is preferably a mixed bonding. The gate driver layer 1064 and the power transistor layer 1066 are vertically interconnected through silicon vias 1061 and interconnected with the substrate, which significantly improves the power supply efficiency and reduces power loss.

[0067] like Figure 1 As shown, a plurality of deep trench capacitor modules 107 are arranged in a plurality of cavities of the substrate. In one embodiment of the present invention, the deep trench capacitor module 107 may also be an inductor module. Integrating a deep trench capacitor module or an inductor module in a substrate cavity can significantly improve power decoupling performance and power integrity performance.

[0068] like Figure 1 As shown, the plastic encapsulation layer 108 encapsulates and covers the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module. In one embodiment of the present invention, the plastic encapsulation is injection molding; the material of the plastic encapsulation layer 108 is epoxy resin.

[0069] like Figure 1 As shown, the redistribution layer 109 is arranged on the upper surface of the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module. In one embodiment of the present invention, the redistribution layer 109 includes multiple dielectric layers and multiple metal layers. Figure 1 As shown, the redistribution layer 109 is not provided with metal wiring at the position of the microchannel inlet and outlet, and the redistribution layer at the position of the microchannel inlet and outlet is etched to make the microchannel inlet 115 and the microchannel outlet 116. The microchannel inlet 115 and the microchannel outlet 116 are interconnected with the microchannel to realize the inflow and outflow of the coolant. The coolant flows in the microchannel, thereby quickly dissipating the heat of the chip module. The redistribution layer is electrically connected to the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module.

[0070] like Figure 1 As shown, the chip module is arranged on the upper surface of the redistribution layer 109. The chip module includes a first chip module 110, a second chip module 111 and a third chip module 112, and the chip module is electrically connected to the redistribution layer 109 through a bump 113. The bottom filling glue 114 fills the bottom of the chip module. In one embodiment of the present invention, the first chip module 110 includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; the second chip module 111 includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; the third chip module 112 includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types. In one embodiment of the present invention, the chip can be a logic chip such as a CPU, DSP, GPU, FPGA, etc., or a storage chip such as a DRAM, Flash, HBM, etc., or other types of chips such as SOC or sensors (such as MEMS sensors, etc.). In one embodiment of the present invention, the first chip module 110 and the second chip module 111 are preferably HBM memory chips, and the third chip module 112 is preferably a stacked chip formed by hybrid bonding of logic chips such as CPU, DSP, GPU, FPGA and DRAM. The third chip module 112 can also be other high-power chips or chips with high bandwidth and storage requirements. In one embodiment of the present invention, the material of the bump 113 can be pure metals such as Au, Cu, Sn, In, or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu. In one embodiment of the present invention, the main material of the bottom filling glue 114 is preferably an epoxy resin matrix and fillers such as SiO2 and Al2O3.

[0071] In one embodiment of the present invention, the upper surface of the redistribution layer 109 further includes a bump structure, and the material of the bump structure can be pure metal such as Au, Cu, Sn, In, or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc. The size and pitch of the bump used for Die to Die interconnection at the bottom of the chip module are smaller than the size and pitch of the bump structure used for interconnection with the upper surface of the redistribution layer.

[0072] like Figure 1 As shown, solder balls 117 are arranged on the lower surface of substrate bottom 103 and are electrically connected to substrate bottom 103. In one embodiment of the present invention, the material of solder balls 117 can be a single layer of metal such as copper, nickel, tin, silver or other metals, or composite metals.

[0073] Figure 3A schematic flow chart of a method for manufacturing a highly integrated semiconductor packaging structure according to an embodiment of the present invention is shown. Figure 4a-4i A cross-sectional schematic diagram of a process for forming a highly integrated semiconductor packaging structure according to an embodiment of the present invention is shown.

[0074] Combine the following Figure 3 and Figure 4a-4i A method for manufacturing a highly integrated semiconductor packaging structure of the present invention is described.

[0075] First, a temporary bonding layer 102 is formed on the upper surface of the carrier 101, such as Figure 4a In one embodiment of the present invention, the carrier 101 may be glass or silicon wafer or metal plate. In one embodiment of the present invention, the temporary bonding layer 102 may be silicon oxide or silicon nitride or silicon oxynitride or organic bonding adhesive, and the organic bonding adhesive may be bonding adhesive of TMAT, BSI, 3M and DuPont.

[0076] Next, a substrate is arranged on the upper surface of the temporary bonding layer 102, wherein the substrate includes a substrate bottom 103, a substrate middle 104 and a substrate top 105. Figure 4b As shown. The substrate is dug to form a plurality of cavities, the sides of the plurality of cavities are the middle part of the substrate and the top of the substrate, and the bottom surface of the plurality of cavities is the middle part of the substrate, that is, the middle part of the substrate is partially dug and not dug through. In one embodiment of the present invention, the bottom 103 of the substrate includes a first interconnection circuit layer; the middle part 104 of the substrate includes a second interconnection circuit layer; the top 105 of the substrate includes a third interconnection circuit layer, and the top 105 of the substrate also includes an interconnection pad, and the interconnection pad of the top 105 of the substrate is electrically connected to the redistribution layer; the first interconnection circuit layer, the second interconnection circuit layer, and the third interconnection circuit layer are electrically connected.

[0077] Next, high-performance power supply and heat dissipation modules 106 and deep trench capacitor modules 107 are arranged in the plurality of cavities, such as Figure 4c As shown. The high-performance power supply and heat dissipation module 106 includes a microchannel. In one embodiment of the present invention, the deep trench capacitor module 107 may also be an inductor module.

[0078] Next, a plastic encapsulation layer 108 is made to encapsulate and cover the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module. The plastic encapsulation layer is thinned to expose the interconnection pads on the top of the substrate, the interconnection pads on the top of the high-performance power supply and heat dissipation module, and the interconnection pads on the top of the deep trench capacitor module. Figure 4d In one embodiment of the present invention, the plastic encapsulation is injection molding; the material of the plastic encapsulation layer 108 is epoxy resin.

[0079] Next, a redistribution layer 109 is fabricated on the upper surfaces of the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module. Figure 4e As shown. In one embodiment of the present invention, the redistribution layer 109 includes a plurality of dielectric layers and a plurality of metal layers. In one embodiment of the present invention, the upper surface of the redistribution layer 109 also includes a bump structure, and the material of the bump structure can be a pure metal such as Au, Cu, Sn, In, or an alloy such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu. The redistribution layer is electrically connected to the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module.

[0080] Next, a chip module is arranged on the upper surface of the redistribution layer, wherein the chip module includes a first chip module 110, a second chip module 111 and a third chip module 112. Figure 4f As shown. The chip module is electrically connected to the redistribution layer 109 through the bump 113. In one embodiment of the present invention, the first chip module 110 includes multiple identical chips, or multiple chips of the same type, or multiple chips of different types; the second chip module 111 includes multiple identical chips, or multiple chips of the same type, or multiple chips of different types; the third chip module 112 includes multiple identical chips, or multiple chips of the same type, or multiple chips of different types. In one embodiment of the present invention, the chip can be a logic chip such as CPU, DSP, GPU, FPGA, etc., or a memory chip such as DRAM, Flash, HBM, etc., or other types of chips or sensors such as SOC (such as MEMS sensors, etc.). In one embodiment of the present invention, the first chip module 110 and the second chip module 111 are preferably HBM memory chips, and the third chip module 112 is preferably a stacked chip formed by hybrid bonding of logic chips such as CPU, DSP, GPU, FPGA and DRAM. The third chip module 112 can also be other high-power chips or chips with high bandwidth and storage requirements. In one embodiment of the present invention, the material of the bump 113 can be pure metal such as Au, Cu, Sn, In, or alloys such as Pb-Sn, Au-Sn, Ag-Sn, Sn-Cu, Ag-Sn-Cu, etc.

[0081] Next, fill the bottom of the chip module with bottom filling glue 114, such as Figure 4g In one embodiment of the present invention, the main material of the bottom filling glue 114 is preferably an epoxy resin matrix and fillers such as SiO2 and Al2O3.

[0082] Next, holes are punched at the positions of the redistribution layer corresponding to the microchannel inlet and outlet to form a microchannel inlet 115 and a microchannel outlet 116. Figure 4hAs shown, the microchannel inlet 115 and the microchannel outlet 116 are interconnected with the microchannel to realize the inflow and outflow of the cooling liquid. The cooling liquid flows in the microchannel, thereby quickly dissipating the heat of the chip module.

[0083] Finally, the carrier is removed, the substrate is cut, and solder balls 117 are arranged on the lower surface of the bottom of the substrate to form a highly integrated semiconductor packaging structure, such as Figure 4i As shown. In one embodiment of the present invention, mechanical separation or thermal sliding or laser separation is used to remove the carrier. The solder ball 117 is electrically connected to the substrate bottom 103. In one embodiment of the present invention, the material of the solder ball 117 can be a single layer of metal such as copper, nickel, tin, silver or other metals, or a composite metal.

[0084] The highly integrated semiconductor packaging structure provided by the present invention integrates a high-performance power supply and heat dissipation module containing microchannels in a substrate cavity, and the chip module quickly dissipates heat through bumps, redistribution layers and microchannels, thereby significantly improving the heat dissipation capacity; the gate drive layer and the power transistor layer are vertically interconnected through silicon vias and interconnected with the substrate, thereby significantly improving the power supply efficiency and reducing power loss; a deep trench capacitor module or an inductor module is integrated in the substrate cavity, which can significantly improve the power decoupling performance and the power integrity performance; an interconnection line layer is arranged on top of the high-performance power supply and heat dissipation module, and the chip module can achieve fast D2D interconnection through bumps, redistribution layers and interconnection line layers, thereby meeting the bandwidth and storage requirements of high-performance chips.

[0085] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A highly integrated semiconductor packaging structure, characterized in that: include: A substrate, the substrate comprising a substrate bottom, a substrate middle and a substrate top, a plurality of cavities arranged in the substrate, the sides of the plurality of cavities being the substrate middle and the substrate top, and the lower surfaces of the plurality of cavities being the substrate middle; A high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged in the plurality of cavities, wherein the high-performance power supply and heat dissipation module comprises a microchannel; A plastic sealing layer, wherein the plastic sealing layer seals and covers the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module; A redistribution layer, the redistribution layer is arranged on the upper surface of the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module, and the redistribution layer is electrically connected to the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module; Chip modules, the chip modules comprising a first chip module, a second chip module and a third chip module, arranged on the upper surface of the redistribution layer, the chip modules being electrically connected to the redistribution layer via bumps; Bottom filling glue, filling the bottom of the chip module; A microchannel inlet and a microchannel outlet are arranged in the redistribution layer, and the microchannel inlet and the microchannel outlet are interconnected with the microchannel to achieve inflow and outflow of cooling liquid; Solder balls are arranged on the lower surface of the bottom of the substrate.

2. The highly integrated semiconductor package structure according to claim 1, characterized in that: The bottom of the substrate comprises a first interconnection circuit layer; and / or The middle portion of the substrate comprises a second interconnection circuit layer; and / or The top of the substrate includes a third interconnection line layer.

3. The highly integrated semiconductor packaging structure according to claim 1, characterized in that: The high-performance power supply and heat dissipation module includes: Power transistor layer; a bonding layer, the bonding layer being arranged on an upper surface of the power transistor layer; A gate driving layer, wherein the gate driving layer is arranged on an upper surface of the bonding layer, and the gate driving layer is bonded to the power transistor layer through the bonding layer; a fourth interconnection circuit layer, wherein the fourth interconnection circuit layer is arranged on an upper surface of the gate driving layer; Through Silicon Via, wherein the through silicon via runs through the high-performance power supply and heat dissipation module; A microchannel is arranged in the power transistor layer, the gate drive layer and the bonding layer.

4. The highly integrated semiconductor packaging structure according to claim 1, characterized in that: The first chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The second chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

5. A method for manufacturing a highly integrated semiconductor packaging structure, characterized in that: The steps include: A temporary bonding layer is formed on the upper surface of the slide; Arranging a substrate on the upper surface of the temporary bonding layer, the substrate comprising a substrate bottom, a substrate middle and a substrate top, and a plurality of cavities arranged in the substrate; In the plurality of cavities, a high-performance power supply and heat dissipation module and a deep trench capacitor module are arranged, wherein the high-performance power supply and heat dissipation module comprises a microchannel; Making a plastic encapsulation layer, encapsulating and covering the substrate, the high-performance power supply and heat dissipation module and the deep trench capacitor module, thinning the plastic encapsulation layer to expose the interconnection pads on the top of the substrate, the interconnection pads on the top of the high-performance power supply and heat dissipation module and the interconnection pads on the top of the deep trench capacitor module; Making a redistribution layer on the upper surfaces of the substrate, the high-performance power supply and heat dissipation module, and the deep trench capacitor module; On the upper surface of the redistribution layer, a chip module is arranged, wherein the chip module includes a first chip module, a second chip module and a third chip module, and the chip module is electrically connected to the redistribution layer through a bump; Filling the bottom of the chip module with bottom filling glue; Punching holes at positions of the redistribution layer corresponding to the inlet and outlet of the microfluidic channel to form the inlet and outlet of the microfluidic channel; The carrier is removed, the substrate is cut, and solder balls are arranged on the lower surface of the bottom of the substrate to form a highly integrated semiconductor packaging structure.

6. The method for manufacturing a highly integrated semiconductor package structure according to claim 5, characterized in that: The carrier is a glass or silicon wafer or a metal plate; and / or The temporary bonding layer is silicon oxide, silicon nitride, silicon oxynitride or organic bonding glue.

7. The method for manufacturing a highly integrated semiconductor package structure according to claim 5, characterized in that: The plastic encapsulation is injection molding; and / or The material of the plastic sealing layer is epoxy resin.

8. The method for manufacturing a highly integrated semiconductor package structure according to claim 5, characterized in that: The redistribution layer includes a plurality of dielectric layers and a plurality of metal layers.

9. The method for manufacturing a highly integrated semiconductor package structure according to claim 5, characterized in that: The first chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The second chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types; and / or The third chip module includes a plurality of identical chips, or a plurality of chips of the same type, or a plurality of chips of different types.

10. The method for manufacturing a highly integrated semiconductor package structure according to claim 5, characterized in that: The slide is removed using mechanical separation or thermal sliding or laser separation.

Images