Wafer-level fan-out packaging method and wafer-level fan-out packaging structure

Abstract

The embodiment of the present invention provides a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure, which relate to the field of chip packaging technology. The method prepares a carrier with a relief protrusion and directly forms a plastic package body on the carrier. After removing the carrier, a plastic package body with a relief groove is obtained. The relief groove is directly obtained by plastic packaging with a plastic packaging material, and then the chip is embedded in the relief groove, and a passivation layer covering the relief groove is formed on the surface of the plastic package body, and finally the wafer-level processes such as wiring layer and solder ball are completed. The advantages of easy plasticity and low cost of the plastic package material are fully utilized, and the mature plastic packaging shaping process is used. In combination with the relief protrusion of the carrier, the relief groove and other structures can be accurately shaped, and the process is simple and the process difficulty is low. In addition, by embedding the chip in the relief groove, the front side is rewired to fan out each signal contact outside the plastic package, thereby improving the reliability of the plastic package.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging technology, and in particular to a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, wafer-level fan-out packaging structures are widely used in the semiconductor industry. As chips become smaller and smaller, the number of signal contacts increases, and traditional packaging can no longer meet the demand for high contact counts. Wafer-level fan-out packaging technology (FOWLP) is a supplement to wafer-level chip size packaging technology. It leads out the chip signal contact port by reconstructing the wafer, and forms a solder ball or bump terminal array on the reconstructed plastic package. It can replace the traditional wire bond and solder ball array (WBBGA) packaging or flip chip solder ball array (FCBGA) packaging (<500 signal contact count) packaging structure within a certain range, and is particularly suitable for the booming portable consumer electronics field.

[0003] The FOWLP process has been used since 2008, mainly in the eWLB (Embedded Wafer Level BGA) technology of Infineon Wireless (later Intel's wireless department). The standard eWLB process flow is as follows: first, a film is attached to a carrier, and then the chip signal connection points are placed face down on the film. The chip is encapsulated in the molding compound using a wafer-level injection molding process, the molding compound is cured, the carrier is removed, and then the molding compound wafer with the chip is subjected to wafer-level processing. The exposed side of the chip signal connection point is passivated, metal rewiring is performed, the bottom metal layer of the bump is prepared, the ball is planted, and finally the package is completed by slicing.

[0004] For the above process flow, since the chip needs to be bonded to the carrier, the film layer needs to be peeled off when the carrier is peeled off, which undoubtedly increases the complexity and difficulty of the process, and the material cost is high. It is easy to leave residual glue, which affects the subsequent wafer-level process and reduces the reliability of the package. In addition, since the plastic encapsulation material directly encapsulates the chip, it is easy to cause warping or offset problems during the encapsulation process, which affects the internal stress of the chip and even causes hidden cracks in the chip, affecting product quality. Summary of the invention

[0005] The objects of the present invention include, for example, providing a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure, which have simple processes and low costs, while having high packaging reliability, and reducing warping or offset problems, thereby improving product quality.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] In a first aspect, the present invention provides a wafer-level fan-out packaging method, comprising:

[0008] preparing a carrier plate with a relief protrusion;

[0009] Forming a plastic packaging body covering the outside of the giving way protrusion on the carrier board;

[0010] Removing the carrier plate and forming a recess on the plastic package body;

[0011] embedding the chip into the recess;

[0012] forming a passivation layer covering the recess on the plastic package body;

[0013] forming a wiring layer on the passivation layer;

[0014] Performing ball planting on the wiring layer to form solder balls;

[0015] Wherein, the wiring layer is electrically connected to the chip.

[0016] In an optional embodiment, the step of preparing a carrier plate with a relief protrusion comprises:

[0017] providing a metal plate;

[0018] The metal plate is grooved to remove a preset area to form the clearance protrusion.

[0019] In an optional embodiment, the step of cutting grooves on the metal plate to remove a preset area includes:

[0020] A plurality of preset areas with different spacings are removed by slotting the metal plate to form a plurality of the clearance protrusions with different widths.

[0021] In an optional embodiment, after the step of performing ball planting on the wiring layer, the method further includes:

[0022] A thinning process is performed on a surface of the plastic package body on a side away from the wiring layer.

[0023] In an optional embodiment, the step of forming a passivation layer on the plastic package body includes:

[0024] A dielectric material is coated in the recess and on the surface of the plastic package to form a passivation layer covering the chip.

[0025] In an optional embodiment, after the step of forming a passivation layer on the plastic package body, the method further comprises:

[0026] Grooving the passivation layer to form a passivation layer opening;

[0027] Wherein, the passivation layer opening penetrates to the surface of the chip.

[0028] In an optional embodiment, before the step of embedding the chip into the recess, the method further comprises:

[0029] Adhesive glue is coated on the bottom wall of the recess or the surface of the chip.

[0030] In an optional embodiment, the step of embedding the chip into the recess comprises:

[0031] embedding at least two of the chips into the recess;

[0032] Wherein, two adjacent chips are arranged at intervals and are mounted on the bottom wall of the recess.

[0033] In an optional embodiment, the step of forming a wiring layer on the passivation layer includes:

[0034] forming a metal layer on the passivation layer and patterning the metal layer;

[0035] forming a dielectric layer on the metal layer;

[0036] Wherein, the metal layer is used to electrically connect the solder ball and the chip.

[0037] In a second aspect, the present invention provides a wafer-level fan-out packaging structure, comprising:

[0038] A plastic package body having a recess on one side;

[0039] A chip disposed in the recess;

[0040] A passivation layer disposed on one side of the plastic package body and covering the recess;

[0041] A wiring layer disposed on a side of the passivation layer away from the plastic package body;

[0042] Solder balls disposed on the wiring layer;

[0043] Wherein, the wiring layer is electrically connected to the chip.

[0044] In an optional embodiment, there are a plurality of the recesses, each of which is provided with the chip, and the plurality of recesses have different widths for accommodating the chips of different specifications.

[0045] In an optional embodiment, a plurality of the chips are arranged in the recess, and the plurality of the chips are laid out in the recess at intervals.

[0046] The beneficial effects of the embodiments of the present invention include, for example:

[0047] The embodiment of the present invention provides a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure. A carrier with a relief protrusion is prepared, and a plastic encapsulation body is directly formed on the carrier. After the carrier is removed, a plastic encapsulation body with a relief groove is obtained. The relief groove is directly obtained by plastic encapsulation using a plastic encapsulation material, and then a chip is embedded in the relief groove, and a passivation layer covering the relief groove is formed on the surface of the plastic encapsulation body. Finally, wafer-level processes such as wiring layers and solder balls are completed. The advantages of easy plasticity and low cost of the plastic encapsulation material are fully utilized, and the mature plastic encapsulation shaping process is used. In combination with the relief protrusion of the carrier, structures such as the relief groove can be accurately shaped, and the process is simple and the process difficulty is low. In addition, by embedding the chip in the relief groove, the front side is rewired to fan out each signal contact to the outside of the plastic encapsulation body, thereby improving the reliability of the plastic encapsulation. At the same time, since the process of directly plastic encapsulating outside the chip is not adopted, and the structure of the relief groove is adopted, there is a certain buffer between the plastic encapsulation body and the chip when warping or offset occurs, thereby avoiding problems such as chip cracking. At the same time, the plastic package has good heat dissipation performance, which can ensure the heat dissipation of the product. Compared with the prior art, the wafer-level fan-out packaging method and wafer-level fan-out packaging structure provided by the present invention have simple process and low cost, high packaging reliability, and alleviate the problem of warping or offset, thereby improving product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 A flowchart of the steps of the wafer-level fan-out packaging method provided by the first embodiment of the present invention;

[0050] Figures 2 to 8 A process flow chart of a wafer-level fan-out packaging method provided by the first embodiment of the present invention;

[0051] Fig. 9 A schematic diagram of a wafer-level fan-out packaging structure provided by a first embodiment of the present invention;

[0052] Figures 10 to 13 A process flow chart of a wafer-level fan-out packaging method provided for a second embodiment of the present invention;

[0053] Figures 14 to 17 A process flow chart of a wafer-level fan-out packaging method provided in a third embodiment of the present invention;

[0054] Fig.18A schematic diagram of a wafer-level fan-out packaging structure provided in accordance with a third embodiment of the present invention.

[0055] Icon: 100-wafer-level fan-out packaging structure; 110-plastic package; 111-gap groove; 130-chip; 150-passivation layer; 170-wiring layer; 171-dielectric layer; 173-metal layer; 190-solder ball; 200-carrier; 210-gap protrusion. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0059] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0060] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0061] As disclosed in the background technology, the standard eWLB process flow in the prior art is as follows: first, a film is attached to a carrier, and then the chip signal connection point is placed on the film face down, and the chip is encapsulated in the molding compound using a wafer-level injection molding process, the molding compound is cured, and the carrier is removed. The molding compound wafer with the chip is then subjected to wafer-level processing, and the exposed side of the chip signal connection point is passivated, metal rewiring is performed, the bottom metal layer of the bump is prepared, and the ball is implanted, and finally the package is completed by slicing.

[0062] Furthermore, in order to solve a series of problems brought about by the above-mentioned processes, other solutions have emerged to realize fan-out packaging structures, such as patent US20080308917 and patent US2015003000, in which a number of chips are encapsulated with plastic materials such as polymers, so that the chips are embedded therein, and then wafer-level processes are performed. The main problems of this method are as follows. First, the warping problem of polymer adhesive wafers. The use of silicon or glass carriers can help reduce the warping, but it brings complex processes for temporary bonding and debonding. It is necessary to develop new low-warpage molding compounds, resulting in high material costs. Secondly, for 10×10mm to 12×12mm fan-out packages, board-level reliability is very challenging, especially for tests related to temperature cycling. For eWLB products, bottom filling glue is required after board-level connection to improve reliability. Thirdly, the use of polymer adhesive wafers has a great impact on yield. Chip offset during injection molding and molding compound curing is a major process obstacle. Another key point is the selection of rewiring dielectric materials, because the reconstructed wafer needs to adapt to the rewiring process, and standard wafer-level dielectrics cannot be directly applied.

[0063] Alternatively, patent CN201410288940 discloses a fan-out packaging structure, which is to make a groove on the silicon substrate, invert the chip at the bottom of the groove, and electrically lead the chip signal connection point to the surface of the silicon substrate through the line; the groove is filled with plastic packaging material, and a rewiring metal is made on the surface of the plastic packaging material to electrically lead the line. This structure and process are very complex and costly.

[0064] Alternatively, patent CN201520597950 discloses a fan-out packaging structure, which is to make grooves in the silicon substrate, place the chip at the bottom of the groove, and make a rewiring metal on the surface of the plastic packaging material to electrically lead out the circuit. The cost of making grooves in this structure is high and the time for preparing the wafer substrate in the early stage is long.

[0065] In other words, the existing technologies cannot solve the problems of complex process, high cost and poor reliability. In order to solve the technical problems existing in the standard process and other existing processes, the present invention provides a novel wafer-level fan-out packaging method and wafer-level fan-out packaging structure, which has simple process, low cost, high packaging reliability, and alleviates the problem of warping or offset, thereby improving product quality. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0066] First embodiment

[0067] See also Figure 1 The present embodiment provides a wafer-level fan-out packaging method for preparing a wafer-level fan-out packaging structure 100, wherein the method has a simple process and low cost, and at the same time has high packaging reliability, and alleviates the problem of warping or offset, thereby improving product quality.

[0068] The wafer-level fan-out packaging method provided in this embodiment includes the following steps:

[0069] S1: preparing a carrier board 200 with a relief protrusion 210.

[0070] See also Figure 2 Specifically, the carrier 200 is a metal carrier 200. In the actual preparation process, a metal plate may be provided first, and then a preset area on the metal plate may be removed by a grooving process, so that the remaining part forms a relief protrusion 210. The metal plate may be grooved by laser grooving, CNC finishing or electroforming, and the groove depth is adapted to the thickness of the chip 130 to be subsequently embedded.

[0071] In this embodiment, a pattern of a preset area can be set in advance on the metal plate, and the metal plate can be directly laser grooved, CNC finished or electroformed according to the preset pattern to remove excess metal plate, and the remaining part protrudes upward to form a yield protrusion 210.

[0072] S2: forming a plastic package body 110 on the carrier board 200 to cover the outer surface of the relief protrusion 210 .

[0073] See also Figure 3 Specifically, the carrier plate 200 is used as a carrier, and the plastic encapsulation material is used for plastic encapsulation. After curing, the plastic encapsulation body 110 is formed. The plastic encapsulation body 110 is covered outside the relinquishing protrusion 210. During the plastic encapsulation process, the plastic encapsulation body 110 has a small warping degree due to the use of a metal plate structure, and the metal plate and the plastic encapsulation material are also easy to separate. In addition, the metal plate here can be reused, which can greatly reduce the cost of the entire product.

[0074] S3 : removing the carrier board 200 and forming a clearance groove 111 on the plastic package body 110 .

[0075] See also Figure 4 Specifically, the carrier 200 is peeled off. Due to the presence of the relief protrusion 210 on the carrier 200, a relief groove 111 is formed on the plastic package body 110 after peeling off. The depth of the relief groove 111 can be determined by the height of the relief protrusion 210, that is, the depth of the relief groove 111 can be controlled by controlling the depth of the groove on the metal plate.

[0076] S4: embedding the chip 130 into the recess 111 .

[0077] See also Figure 5 Specifically, the chip 130 can be placed in the clearance groove 111 and mounted on the bottom wall of the clearance groove 111. In this embodiment, the width of the clearance groove 111 is adapted to the width of the chip 130, so that the chip 130 can be loaded into the clearance groove 111, and a single chip 130 is loaded in a single clearance groove 111.

[0078] It should be noted that the surface of the chip 130 in this embodiment is provided with a signal connection point. When mounting the chip 130, the side of the chip 130 with the signal connection point can be turned away from the bottom wall of the make way groove 111, and the other side can be mounted in the make way groove 111, so as to facilitate subsequent wafer-level processing.

[0079] In this embodiment, before executing step S4, in order to ensure the mounting effect of the chip 130, an adhesive may be applied or a die-mounting film may be attached to the bottom wall of the recess 111 or the back surface of the chip 130. Preferably, in this embodiment, an adhesive is applied or a die-mounting film is attached to the side of the chip 130 where no signal connection point is provided, and then the chip 130 is bonded to the recess 111 by the adhesive or die-mounting film.

[0080] S5: forming a passivation layer 150 on the plastic package body 110 to cover the chip 130 and the gap between the recess 111 and the sidewall of the chip 130 .

[0081] See also Figure 6 Specifically, a dielectric material may be pressed onto the plastic package 110 so that the dielectric material can fill the gap between the chip 130 and the sidewall of the recess 111 and cover the chip 130 , and the passivation layer 150 is formed after curing.

[0082] It should be noted that, in this embodiment, the passivation layer 150 covers the surface of the plastic package 110 and the chip 130 at the same time, and fills the gap between the chip 130 and the side wall of the recess 111. The passivation layer 150 also plays a buffering role in the subsequent process, preventing the warping stress of the plastic package 110 from directly acting on the surface of the chip 130, thereby alleviating the impact of the warping of the plastic package 110 on the chip 130.

[0083] It should be noted that the dielectric material in this embodiment may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, polymer glue, etc.

[0084] In this embodiment, in order to realize the fan-out structure of the chip 130, after forming the passivation layer 150, it is necessary to expose the signal connection points on the chip 130. Specifically, exposure and development can be performed on the passivation layer 150, and grooves can be formed to form passivation layer openings, wherein the passivation layer openings penetrate to the surface of the chip 130 and correspond to the signal connection points on the chip 130.

[0085] S6 : forming a wiring layer 170 on the passivation layer 150 .

[0086] See also Figure 7 Specifically, the wiring layer 170 includes a dielectric layer 171 and a metal layer 173, wherein the metal layer 173 is embedded in the dielectric layer 171 to play the role of electrical connection. When the step S6 is actually performed, after the passivation layer 150 is grooved, the metal layer 173 can be electroplated on the passivation layer 150, and the line distribution is completed after patterning, and then covered with a layer of dielectric layer 171. The metal layer 173 extends to the passivation layer opening and is connected to the signal connection point on the chip 130.

[0087] In this embodiment, the redistribution wiring layer is epitaxially extended by electroplating to form a metal layer 173, wherein one end of the metal layer 173 is connected to the signal connection point of the chip 130, and the other end is epitaxially extended to the plastic packaging material area and placed on the passivation layer 150. Then, the dielectric layer 171 is covered on the metal layer 173, and a groove process is performed, and then a pad is formed by electroplating, and the pad is connected to the metal layer 173. It is convenient to complete the subsequent ball planting process.

[0088] It should be noted that the metal layer 173 here is a copper wire layer, which plays the role of line connection. For the specific pattern preparation of the metal layer 173, reference can be made to the existing wiring process. Of course, the metal layer 173 here is made by electroplating process. In other preferred embodiments of the present invention, the metal layer 173 can also be prepared by physical vapor deposition process (PVD), chemical vapor deposition process (CVD), sputtering or chemical plating.

[0089] S7: performing ball planting on the wiring layer 170 to form solder balls 190 .

[0090] Please continue to see Figure 7Specifically, after forming the metal layer 173, a pad is formed by electroplating on the metal layer 173, and a ball is planted on the surface of the pad to form a solder ball 190 electrically connected to the metal layer 173. In this embodiment, the material of the solder ball 190 can be SnAg, SnAgCu, etc. The solder ball 190 can realize the external connection function and realize electrical connection with the chip 130 through the metal layer 173.

[0091] See also Figure 8 It is worth noting that after the ball implantation is completed, a thinning process can be performed on the surface of the plastic package body 110 away from the wiring layer 170 according to different thickness requirements.

[0092] See also Fig. 9 After the thinning is completed, a cutting process can be performed to obtain a single wafer-level fan-out packaging structure 100.

[0093] Please continue to see Fig. 9 The present embodiment also provides a wafer-level fan-out packaging structure 100, which is prepared by the above method. The wafer-level fan-out packaging structure 100 includes a plastic package 110, a chip 130, a passivation layer 150, a wiring layer 170 and a solder ball 190, wherein the plastic package 110 is provided with a clearance groove 111 on one side, the chip 130 is arranged in the clearance groove 111, the passivation layer 150 is arranged on one side of the plastic package 110 and covers the clearance groove 111, the wiring layer 170 is arranged on the side of the passivation layer 150 away from the plastic package 110, and the solder ball 190 is arranged on the wiring layer 170, wherein the wiring layer 170 is electrically connected to the chip 130.

[0094] In this embodiment, the size of the recess 111 is adapted to the size of the chip 130, and a single chip 130 is disposed in a single recess 111. The passivation layer 150 simultaneously fills the gap between the chip 130 and the side wall of the recess 111 to ensure the packaging effect and also plays a buffering role.

[0095] In this embodiment, the wiring layer 170 includes a dielectric layer 171 and a metal layer 173, wherein the metal layer 173 is embedded in the dielectric layer 171 for realizing line connection. One side surface of the chip 130 is mounted in the recess 111, and a signal connection point is arranged on the other side surface. A passivation layer opening is arranged in the passivation layer 150, and the metal layer 173 extends to the passivation layer opening and is connected to the signal connection point. The solder ball 190 is arranged on the pad of the metal layer 173.

[0096] In summary, the present embodiment provides a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure 100, by preparing a carrier 200 with a clearance protrusion 210, and directly forming a plastic package 110 on the carrier 200, after removing the carrier 200, a plastic package 110 with a clearance groove 111 is obtained, and the clearance groove 111 is directly obtained by plastic packaging with a plastic packaging material, and then the chip 130 is embedded in the clearance groove 111, and a passivation layer 150 covering the clearance groove 111 is formed on the surface of the plastic package 110, and finally the wafer-level processes such as the wiring layer 170 and the solder ball 190 are completed. The advantages of easy plasticity and low cost of the plastic package are fully utilized, and the mature plastic packaging molding process is used, combined with the clearance protrusion 210 of the carrier 200, so that the clearance groove 111 and other structures can be accurately molded, and the process is simple and the process difficulty is low. In addition, the chip 130 is embedded in the recess 111, and the front side is rewired to fan out each signal contact to the outside of the plastic package 110, thereby improving the reliability of the plastic package. At the same time, since the process of directly plastic-sealing the chip 130 is not adopted, but the structure of the recess 111 is adopted, there is a certain buffer between the chip 130 and the plastic package 110 when warping or offset occurs, thereby avoiding problems such as hidden cracks in the chip 130. At the same time, the plastic package 110 has good heat dissipation performance, which can ensure the heat dissipation of the product.

[0097] Second embodiment

[0098] Please continue to see Figure 1 This embodiment provides a wafer-level fan-out packaging method, and its basic process steps are similar to those of the first embodiment of the implementation principle. For matters not mentioned in this embodiment, please refer to the first embodiment for details.

[0099] The wafer-level fan-out packaging method provided in this embodiment includes the following steps:

[0100] S1: preparing a carrier board 200 with a relief protrusion 210.

[0101] See also Fig.10 , wherein, in the process of preparing the carrier 200, a metal plate is first provided, and then a groove is made on the metal plate to remove a preset area to form a clearance protrusion 210. Specifically, a plurality of preset areas with different spacings can be grooved on the metal plate to form a plurality of clearance protrusions 210 with different widths. In this embodiment, two clearance protrusions 210 are used as an example for description, wherein the widths of the two clearance protrusions 210 are not the same.

[0102] S2: forming a plastic package body 110 on the carrier board 200 to cover the outer surface of the relief protrusion 210 .

[0103] See also Fig.11Specifically, the carrier board 200 is used as a carrier body, and is encapsulated by a plastic encapsulation material, and the plastic encapsulation body 110 is formed after curing.

[0104] S3 : removing the carrier board 200 and forming a clearance groove 111 on the plastic package body 110 .

[0105] See also Fig.12 Specifically, the carrier plate 200 is peeled off. Since the widths of the relief protrusions 210 on the carrier plate 200 are different, two relief grooves 111 with different widths can be formed.

[0106] S4: embedding the chip 130 into the recess 111 .

[0107] See also Fig.13 Specifically, chips 130 of different specifications can be embedded in two clearance grooves 111 of different widths, so that the two chips 130 are respectively adapted to the two clearance grooves 111.

[0108] S5: forming a passivation layer 150 on the plastic package body 110 to cover the chip 130 and the gap between the recess 111 and the sidewall of the chip 130 .

[0109] The dielectric material may be pressed onto the plastic package 110 so that the dielectric material can fill the gap between the chip 130 and the sidewall of the recess 111 and cover the chip 130 . After curing, the passivation layer 150 is formed.

[0110] S6 : forming a wiring layer 170 on the passivation layer 150 .

[0111] Specifically, the metal layer 173 can be formed by electroplating on the passivation layer 150 , patterned to complete the circuit distribution, and then covered with a dielectric layer 171 . The metal layer 173 extends to the passivation layer opening and is connected to the signal connection point on the chip 130 .

[0112] S7: performing ball planting on the wiring layer 170 to form solder balls 190 .

[0113] Specifically, after the dielectric layer 171 is formed, a groove process is performed, and then a pad is formed by an electroplating process, the pad is connected to the metal layer 173 , and then a ball is implanted on the surface of the pad to form a solder ball 190 electrically connected to the metal layer 173 .

[0114] The process flow of step S5 to step S7 is the same as that of the first embodiment and is not illustrated here.

[0115] Please continue to see Fig. 9The present embodiment also provides a wafer-level fan-out packaging structure 100, which includes a plastic package 110, a chip 130, a passivation layer 150, a wiring layer 170 and a solder ball 190, wherein the plastic package 110 is provided with a clearance groove 111 on one side, the chip 130 is arranged in the clearance groove 111, the passivation layer 150 is arranged on one side of the plastic package 110 and covers the clearance groove 111, the wiring layer 170 is arranged on a side of the passivation layer 150 away from the plastic package 110, and the solder ball 190 is arranged on the wiring layer 170, wherein the wiring layer 170 is electrically connected to the chip 130.

[0116] In this embodiment, there are at least two clearance grooves 111, and the widths of the clearance grooves 111 are different. A chip 130 is correspondingly arranged in each clearance groove 111, and the chip 130 is adapted to the width of the corresponding clearance groove 111. For example, in this embodiment, there are two clearance grooves 111, one large and one small, which can be respectively embedded with two chips 130 of one large and one small, so as to realize the embedding setting of chips 130 of different sizes and improve the applicability of the packaging structure.

[0117] In summary, the wafer-level fan-out packaging method and wafer-level fan-out packaging structure 100 provided in this embodiment, by adopting the makeshift grooves 111 of different widths, realize the setting of chips 130 of different sizes, and realize a high-density chip 130 packaging structure, which is more suitable for the future multi-chip 130 integrated fan-out packaging structure.

[0118] Third embodiment

[0119] Please continue to see Figure 1 This embodiment provides a wafer-level fan-out packaging method, and its basic process steps are similar to those of the first embodiment of the implementation principle. For matters not mentioned in this embodiment, please refer to the first embodiment for details.

[0120] The wafer-level fan-out packaging method provided in this embodiment includes the following steps:

[0121] S1: preparing a carrier board 200 with a relief protrusion 210.

[0122] See also Fig.14 In the process of preparing the carrier 200, a metal plate is first provided, and then a groove is cut on the metal plate to remove a preset area to form a clearance protrusion 210. Specifically, a groove can be cut on the metal plate to remove a preset area to form the clearance protrusion 210. The width of the clearance protrusion 210 is relatively large.

[0123] S2: forming a plastic package body 110 on the carrier board 200 to cover the outer surface of the relief protrusion 210 .

[0124] See also Fig.15Specifically, the carrier board 200 is used as a carrier, and the plastic packaging material is used for plastic packaging, and after curing, the plastic packaging body 110 is formed. The plastic packaging body 110 is completely covered outside the relief protrusion 210.

[0125] S3 : removing the carrier board 200 and forming a clearance groove 111 on the plastic package body 110 .

[0126] See also Fig.16 Specifically, the carrier plate 200 is peeled off. Since the width of the relinquishing protrusion 210 on the carrier plate 200 is relatively large, a relatively wide relinquishing groove 111 can be formed.

[0127] S4: embedding the chip 130 into the recess 111 .

[0128] See also Fig.17 Specifically, at least two chips 130 may be embedded in the recess 111, wherein two adjacent chips 130 are spaced apart and mounted on the bottom wall of the recess 111. In this embodiment, two chips 130 are embedded as an example, and here two chips 130 may be embedded in the recess 111, thereby achieving high-density packaging of the chips 130.

[0129] S5: forming a passivation layer 150 on the plastic package body 110 to cover the chip 130 and the gap between the recess 111 and the sidewall of the chip 130 .

[0130] Specifically, the dielectric material may be pressed onto the plastic package 110 so that the dielectric material can fill the gap between the chip 130 and the sidewall of the recess 111 and cover the chip 130 , and the passivation layer 150 is formed after curing.

[0131] S6 : forming a wiring layer 170 on the passivation layer 150 .

[0132] Specifically, the metal layer 173 can be formed by electroplating on the passivation layer 150 , patterned to complete the circuit distribution, and then covered with a dielectric layer 171 . The metal layer 173 extends to the passivation layer opening and is connected to the signal connection point on the chip 130 .

[0133] S7: performing ball planting on the wiring layer 170 to form solder balls 190 .

[0134] Specifically, after forming the dielectric layer 171 , a groove process is performed, and then a pad is formed by an electroplating process, the pad is connected to the metal layer 173 , and then a ball is implanted on the surface of the pad to form a solder ball 190 electrically connected to the metal layer 173 .

[0135] The process flow of step S5 to step S7 is the same as that of the first embodiment and is not illustrated here.

[0136] See also Fig.18 The present embodiment also provides a wafer-level fan-out packaging structure 100, which includes a plastic package 110, at least two chips 130, a passivation layer 150, a wiring layer 170 and a solder ball 190, wherein the plastic package 110 is provided with a clearance groove 111 on one side, at least two chips 130 are arranged in the clearance groove 111, the passivation layer 150 is arranged on one side of the plastic package 110 and covers the clearance groove 111, the wiring layer 170 is arranged on a side of the passivation layer 150 away from the plastic package 110, and the solder ball 190 is arranged on the wiring layer 170, wherein the wiring layer 170 is electrically connected to the chip 130.

[0137] In this embodiment, the width of the recess 111 is relatively large and is greater than twice the width of the chip 130, so that at least two chips 130 can be embedded in the recess 111. Of course, multiple chips 130 of the same or different sizes can also be embedded in the same recess 111, so as to realize the embedding setting of multiple chips 130 and improve the applicability of the packaging structure.

[0138] In summary, the wafer-level fan-out packaging method and wafer-level fan-out packaging structure 100 provided in this embodiment realize the arrangement of multiple chips 130 by adopting the makeshift grooves 111 of different widths, thereby realizing a high-density chip 130 packaging structure, which is more suitable for future multi-chip 130 integrated fan-out packaging structures.

[0139] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A wafer-level fan-out packaging method, characterized in that: include: preparing a carrier plate with a relief protrusion; Forming a plastic packaging body on the carrier board to cover the outside of the giving way protrusion; Removing the carrier plate and forming a recess on the plastic package body; embedding the chip into the recess; forming a passivation layer covering the recess on the plastic package body; forming a wiring layer on the passivation layer; Performing ball planting on the wiring layer to form solder balls; Wherein, the wiring layer is electrically connected to the chip.

2. The wafer-level fan-out packaging method according to claim 1, characterized in that: The step of preparing a carrier plate with a relief protrusion comprises: providing a metal plate; The metal plate is grooved to remove a preset area to form the clearance protrusion.

3. The wafer-level fan-out packaging method according to claim 2, characterized in that: The step of cutting grooves on the metal plate to remove the preset area comprises: A plurality of preset areas with different spacings are removed by slotting the metal plate to form a plurality of the clearance protrusions with different widths.

4. The wafer-level fan-out packaging method according to claim 1, characterized in that: After the step of performing ball planting on the wiring layer, the method further comprises: A thinning process is performed on a surface of the plastic package body on a side away from the wiring layer.

5. The wafer-level fan-out packaging method according to claim 1, characterized in that: The step of forming a passivation layer on the plastic package body comprises: A dielectric material is coated in the recess and on the surface of the plastic package to form a passivation layer covering the chip.

6. The wafer-level fan-out packaging method according to claim 5, characterized in that: After the step of forming a passivation layer on the plastic package body, the method further comprises: Grooving the passivation layer to form a passivation layer opening; Wherein, the passivation layer opening penetrates to the surface of the chip.

7. The wafer-level fan-out packaging method according to claim 1, characterized in that: Before the step of embedding the chip into the recess, the method further comprises: Adhesive glue is coated on the bottom wall of the recess or the surface of the chip.

8. The wafer-level fan-out packaging method according to claim 1, characterized in that: The step of embedding the chip into the recess comprises: embedding at least two of the chips into the recess; Wherein, two adjacent chips are arranged at intervals and are mounted on the bottom wall of the recess.

9. The wafer-level fan-out packaging method according to claim 1, characterized in that: The step of forming a wiring layer on the passivation layer comprises: forming a metal layer on the passivation layer and patterning the metal layer; forming a dielectric layer on the metal layer; Wherein, the metal layer is used to electrically connect the solder ball and the chip.

10. A wafer-level fan-out packaging structure, prepared by the wafer-level fan-out packaging method according to claim 1, characterized in that: The wafer-level fan-out packaging structure comprises: A plastic package body having a recess on one side; A chip disposed in the recess; A passivation layer is arranged on one side of the plastic package body and covers the recess; A wiring layer disposed on a side of the passivation layer away from the plastic package body; Solder balls disposed on the wiring layer; Wherein, the wiring layer is electrically connected to the chip.

11. The wafer-level fan-out packaging structure according to claim 10, characterized in that: There are a plurality of the recesses, each of which is provided with the chip, and the widths of the plurality of recesses are different, so as to accommodate the chips of different specifications.

12. The wafer-level fan-out packaging structure according to claim 10, characterized in that: A plurality of the chips are arranged in the recess, and the plurality of the chips are laid out in the recess at intervals.

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