Packaging structure and manufacturing method of semiconductor chip

Abstract

The invention provides a packaging structure and a manufacturing method of a semiconductor chip, the packaging structure comprises at least one chip group, each chip group comprises a plurality of stacked semiconductor chips, the plurality of semiconductor chips in each chip group and / or connected chip groups, the semiconductor chips are connected through electrical connection parts exposed to the outside of the side walls of the semiconductor chips. The side wall of the electric connection part of the semiconductor chip is exposed out of the side wall of the semiconductor chip, the arrangement mode of the electric connection part except the top surface and the bottom surface of the semiconductor chip is provided, the semiconductor chip can be electrically connected with other devices through the electric connection part exposed out of the side wall, and the packaging mode is more flexible and changeable.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and a method for manufacturing a semiconductor chip. Background Art

[0002] In a semiconductor package structure, a plurality of bare chips are stacked and arranged, and electrical connections need to be formed between the bare chips and between the bare chips and external circuits to transmit electrical signals.

[0003] As the number of bare chips in semiconductor packaging structures gradually increases, packaging using traditional packaging processes is becoming less flexible and changeable. Summary of the invention

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect of the present disclosure, there is provided a packaging structure, comprising at least one chipset, each of the chipset comprising a plurality of semiconductor chips stacked;

[0006] The plurality of semiconductor chips in each chip group and / or the connected chip groups are connected via electrical connection portions exposed to the outside of the sidewalls of the semiconductor chips.

[0007] In some embodiments, the semiconductor chip comprises:

[0008] Chip body;

[0009] A plurality of electrical connection parts are arranged in the chip body, and each of the electrical connection parts extends along the thickness direction of the chip body;

[0010] A side wall of at least one of the plurality of electrical connection portions is exposed outside the chip body.

[0011] In some embodiments, the chip body includes a first type chip body, and in a thickness direction of the first type chip body, a bottom surface of the electrical connection portion is located inside the first type chip body;

[0012] The top surface of the electrical connection portion is flush with the top surface of the first type chip body, or the top surface of the electrical connection portion protrudes from the top surface of the first type chip body.

[0013] In some embodiments, the chip body includes a second type chip body, and in a thickness direction of the second type chip body, a bottom surface of the electrical connection portion is exposed outside the chip body;

[0014] Wherein, the top surface of the electrical connection portion is flush with the top surface of the second type chip body, or the top surface of the electrical connection portion protrudes from the top surface of the second type chip body;

[0015] The bottom surface of the electrical connection portion is flush with the bottom surface of the second-type chip body, or the bottom surface of the electrical connection portion protrudes from the bottom surface of the second-type chip body.

[0016] In some embodiments, the electrical connection includes a conductive plug disposed in a through silicon via.

[0017] In some embodiments, in the thickness direction of the semiconductor chip, the electrical connection parts of the plurality of semiconductor chips in the chipset are facing each other;

[0018] The packaging structure further includes a signal line, one end of which is connected to an electrical connection portion of any semiconductor chip in the chipset;

[0019] The other end of the signal line is connected to a substrate of the packaging structure, and the substrate is used to carry the chipset.

[0020] In some embodiments, the packaging structure further includes an interconnection portion, and the two connected electrical connection portions are electrically connected via the interconnection portion.

[0021] In some embodiments, the number of the chipsets is two, the exposed electrical connection parts of the two chipsets are arranged opposite to each other, the exposed electrical connection parts of the two chipsets are electrically connected through the interconnection part, and the interconnection part is connected to the side wall of the electrical connection part.

[0022] In some embodiments, in the thickness direction of the chipset, the electrical connection parts of the plurality of semiconductor chips in the chipset are facing each other; or,

[0023] The electrical connection parts of two adjacent semiconductor chips in the same chip group are staggered.

[0024] In some embodiments, the interconnection portion includes a hybrid bonding structure or a solder bump.

[0025] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor chip is provided, comprising:

[0026] Providing an initial semiconductor chip, the initial semiconductor chip comprising an initial chip body and a plurality of initial electrical connection portions disposed in the initial chip body;

[0027] Part of the side wall of the initial chip body is removed to expose the side wall of at least one of the multiple initial electrical connection parts outside the initial chip body, the retained initial chip body forms a chip body, and the retained initial electrical connection parts form multiple electrical connection parts.

[0028] In some embodiments, removing a portion of the sidewall of the initial chip body so that the sidewall of at least one of the plurality of initial electrical connection portions is exposed outside the initial chip body comprises:

[0029] The area between the side wall of the initial chip body and the side wall of the initial electrical connection part, as well as a partial area of ​​the initial electrical connection part are removed to expose the remaining side wall of the initial electrical connection part, and the retained initial electrical connection part forms the electrical connection part.

[0030] In some embodiments, the plurality of electrical connection portions are arranged along a first direction, and the first direction is perpendicular to a thickness direction of the chip body;

[0031] Removing part of the side wall of the initial chip body so that the side wall of at least one of the plurality of initial electrical connection parts is exposed outside the initial chip body, comprising:

[0032] The initial chip body is cut along a thickness direction of the initial chip body, with a cutting track being parallel to the first direction.

[0033] In some embodiments, in the second direction, the width dimension of the initial chip body removed is 29 μm to 31 μm;

[0034] The second direction is perpendicular to the first direction and a thickness direction of the chip body.

[0035] In some embodiments, the method for manufacturing the semiconductor chip further includes:

[0036] In the thickness direction of the initial chip body, a portion of the initial chip body is removed so that the top surface and / or the bottom surface of the electrical connection portion is exposed outside the initial chip body.

[0037] In some embodiments, when multiple semiconductor chips are stacked and packaged, the electrical connection parts of two connected chip bodies are electrically connected through a hybrid bonding process or a micro-bump interconnection process.

[0038] In the packaging structure and semiconductor chip manufacturing method provided by the present invention, by exposing the side walls of the electrical connection parts of the semiconductor chip to the outside of the side walls of the semiconductor chip, a setting method of the electrical connection parts other than the top and bottom surfaces of the semiconductor chip is provided. The semiconductor chip can be electrically connected to other devices through the electrical connection parts exposed to the side walls, and the packaging method is more flexible and varied.

[0039] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 It is a packaging structure in the comparative embodiment.

[0042] Figure 2 It is another packaging structure in the comparative embodiment.

[0043] Figure 3 is a schematic diagram showing a packaging structure according to an exemplary embodiment.

[0044] Figure 4 yes Figure 3 A schematic diagram of the interconnection method of the packaging structure is shown.

[0045] Figure 5 yes Figure 3 A schematic diagram of another interconnection method of the packaging structure is shown.

[0046] Figure 6 is a schematic diagram showing a packaging structure according to another exemplary embodiment.

[0047] Figure 7 The figure is a schematic diagram showing an interconnection method of a packaging structure according to an exemplary embodiment.

[0048] Figure 8 FIG. 1 is a schematic diagram of another interconnection method of a packaging structure according to an exemplary embodiment.

[0049] Fig. 9 is a schematic diagram of a semiconductor chip according to an exemplary embodiment.

[0050] Fig.10 yes Fig. 9A cross-sectional view of the AA section.

[0051] Fig.11 yes Fig. 9 Another cross-sectional view of section AA.

[0052] Fig.12 The figure is a flow chart of a method for manufacturing a semiconductor chip according to an exemplary embodiment.

[0053] Reference numerals:

[0054] 100', packaging structure;

[0055] 10', chipset; 11', semiconductor chip;

[0056] 20', base plate;

[0057] 31', signal line; 32', welding bump; 33', interconnection line;

[0058] 100. Packaging structure;

[0059] 10. Chip set; 11. Semiconductor chip; 111. Chip body; 111a. First type chip body; 111b. Second type chip body; 112. Electrical connection portion; 112a. First electrical connection portion; 112b. Second electrical connection portion; 12. Adhesive film;

[0060] 20. Substrate;

[0061] 30. interconnection part; 31. signal line; 32. welding bump;

[0062] 40. Cutting track;

[0063] 50. Initial semiconductor chip; 51. Initial chip body; 52. Initial electrical connection part. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0065] In a semiconductor packaging structure, multiple bare chips are stacked together, and electrical connections need to be formed between the bare chips and between the bare chips and external circuits to transmit electrical signals. Currently, the stacked bare chips are electrically connected through silicon via technology, which is a relatively simple method, resulting in insufficient flexibility in the arrangement of bare chips during packaging.

[0066] Reference Figure 1 FIG. 1 shows a packaging structure 100' in a comparative embodiment, which is packaged using a wire bonding process. A plurality of semiconductor chips 11' (also referred to as bare chips) are arranged along their thickness direction (reference Figure 3 The semiconductor chips 11' are stacked together in the z direction as shown in the figure, wherein each semiconductor chip 11' needs to be electrically connected to a substrate 20' (such as a silicon interposer, a packaging substrate), so that a signal line 31' (also known as a bonding wire, a gold wire, etc.) needs to be set between the substrate 20' and each semiconductor chip 11', resulting in a cumbersome packaging process and a complex packaging structure, making it difficult to ensure packaging efficiency and packaging quality.

[0067] Reference Figure 2 FIG. 1 shows another packaging structure 100' in a comparative embodiment, which is packaged by using a solder bump technology to realize electrical connection between adjacent bare chips. Figure 3 The semiconductor chips 11' are stacked together in the z direction as shown in the figure to form a chipset 10', wherein each semiconductor chip 11' is provided with a through silicon via (TSV), and in the stacking direction of the semiconductor chips 11', the through silicon vias in the plurality of semiconductor chips 11' are arranged opposite to each other, and welding bumps 32' are arranged between the through silicon vias of adjacent semiconductor chips 11', and the welding bumps 32' make the upper and lower sides opposite to each other (in the z direction as shown in the figure). Figure 2 The two through silicon vias (with the orientation shown in FIG. 1 ) are electrically connected. Figure 2 When two chipsets 10' need to be interconnected, they need to be connected on the substrate 20' (refer to Figure 1 ) additional interconnection lines 33' are provided, which makes the packaging process complicated.

[0068] In order to solve the above problems, the present disclosure provides a packaging structure and a method for manufacturing a semiconductor chip, wherein the packaging structure includes at least one chipset, each chip includes a plurality of semiconductor chips arranged in a stacked manner, and the plurality of semiconductor chips in each chipset and / or the connected chipsets are connected via an electrical connection portion exposed to the outside of the side wall of the semiconductor chip. The present disclosure provides a setting method for the electrical connection portion other than the top and bottom surfaces of the semiconductor chip by exposing the side wall of the electrical connection portion of the semiconductor chip to the outside of the side wall of the semiconductor chip, and the semiconductor chip can be electrically connected to other devices via the electrical connection portion exposed to the side wall, and the packaging method is more flexible and changeable.

[0069] In the exemplary embodiments of the present disclosure, Figures 3 to 8 As shown, an embodiment of the present disclosure provides a packaging structure 100, which can be used in the packaging process of various semiconductor products. The semiconductor devices may be, for example, dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0070] like Figures 3 to 8 As shown, the packaging structure 100 includes at least one chipset 10, each chipset 10 includes a plurality of semiconductor chips 11 stacked, wherein adjacent semiconductor chips 11 can be connected by an adhesive film 12, such as a die attach film (DAF). In the embodiment of the present disclosure, the semiconductor chip 11 is the bare die in the comparative embodiment, which is the body of an integrated circuit made of semiconductor material but not packaged. When bare die with a common interface are stacked together, a chipset 10 is formed, and the plurality of semiconductor chips 11 in the chipset 10 can be electrically connected to each other to achieve electrical signal transmission. It should be noted that in some embodiments (refer to Figure 7 ), multiple semiconductor chips 11 in the same chipset 10 may not communicate with each other, but may form electrical connections with semiconductor chips 11 in other chipsets 10 and implement electrical signal transmission (described in detail later).

[0071] Reference Figures 3 to 8 Each semiconductor chip 11 in the chipset 10 includes an electrical connection portion 112. The electrical connection portion 112 may be distributed at multiple locations of the semiconductor chip 11, but it is mainly ensured that part of the sidewalls of a certain number of the electrical connection portions 112 are exposed to the outside of the semiconductor chip 11. The electrical connection portion 112 is columnar, and the extension direction of the electrical connection portion 112 is parallel to the thickness direction of the semiconductor chip 11 ( Figure 3 The z direction is parallel to Figure 3 Taking the orientation shown as an example, this embodiment exemplarily shows a cross section ( Figure 3 The electrical connection portion 112 is a rectangular shape (in the xy plane shown in FIG. 1 ), which does not limit the technical solution of the present invention. The cross-section of the electrical connection portion 112 may also be circular, irregular, etc., without too many limitations.

[0072] In an exemplary embodiment, referring to Figure 6, shows a packaging structure 100, the packaging structure 100 includes a chipset 10, the chipset 10 includes four stacked semiconductor chips 11 (it can also be other numbers, this embodiment is only an exemplary number description), and the multiple semiconductor chips 11 in the chipset 10 can be electrically connected through the TSV technology and metal interconnection technology described above. Figure 1 Compared with the package structure 100' in the comparative embodiment shown, since each semiconductor chip 11 in the chipset 10 in this embodiment has a side wall of the electrical connection portion 112 exposed outside the semiconductor chip 11, in the process of packaging the package structure 100 shown in this embodiment, any semiconductor chip 11 can be selected, and a signal line 31 can be set on the side wall of the electrical connection portion 112 of the semiconductor chip 11, and the signal line 31 is electrically connected to the substrate 20 to form an electrical connection between the chipset 10 and the substrate 20. In other words, the arrangement position of the signal line 31 of the package structure 100 provided in this example is more flexible, and the packaging process is simpler.

[0073] It should be noted that, since the electrical connection parts 112 between the semiconductor chips 11 can be connected by TSV technology, it is not necessary to set all the electrical connection parts 112 of each semiconductor chip 11 to be exposed on the side wall of the semiconductor chip 11. The electrical connection parts 112 exposed outside the semiconductor chip 11 can be set on only one or several of the semiconductor chips 11, and the signal lines 31 are set accordingly to achieve the electrical connection between the chipset 10 and the substrate 20. The present disclosure utilizes the TSV process to obtain the electrical connection parts 112 exposed on the side wall of the semiconductor chip 11 by cutting the position where the TSV is located, so that the semiconductor chip 11 can be electrically connected not only through the top surface or bottom surface of the TSV, but also through the electrical connection parts 112 on the side wall of the semiconductor chip 11. It can be applied in the stacking packaging process and also in the lateral docking process of two semiconductor chips 11, providing more flexible packaging methods.

[0074] In addition, in some cases, if adjacent semiconductor chips 11 cannot be electrically connected through welding bumps 32 or hybrid bonding structures, electrical connection can be achieved by setting a signal line 31 between the side walls of the electrical connection portion 112 exposed outside the side walls of the two connected semiconductor chips 11.

[0075] In another exemplary embodiment, referring to Figures 3 to 5 FIG. 1 shows a package structure 100, which includes two connected chip groups 10, wherein the electrical connection portions 112 of the two chip groups 10 exposed to the outside of the sidewall of the semiconductor chip 11 are arranged opposite to each other. Figure 2Compared with the package structure 100′ in the comparative embodiment shown in the figure, since each semiconductor chip 11 in the chipset 10 in the present embodiment has a side wall of the electrical connection portion 112 exposed to the outside of the semiconductor chip 11, in the process of packaging the package structure 100 shown in the present embodiment, it is not necessary to set additional signal wiring in the substrate 20 (described in detail later), and it is only necessary to set the side walls of the electrical connection portions 112 of the two chipsets 10 exposed to the outside of the semiconductor chip 11 opposite to each other, and set the interconnection portion 30 between the side walls of the two opposite electrical connection portions 112 (refer to Figure 6 , which will be described in detail later) can realize the electrical connection between the two chipsets 10. Not only is the packaging method simple, but the spacing between the chipsets 10 is small, which improves the packaging integration.

[0076] The above two embodiments involved in the embodiments of the present disclosure can be used separately or in combination. By exposing the side wall of the electrical connection part of the semiconductor chip to the outside of the side wall of the semiconductor chip, a setting method of exposing the electrical connection part to the side wall of the semiconductor chip is provided, which is different from the electrical connection part on the top and bottom surfaces of the semiconductor chip. The semiconductor chip can form an electrical connection with other devices through the electrical connection part exposed to the side wall. The packaging method is more flexible and varied, and more types of packaging methods can be provided.

[0077] In an exemplary embodiment, Figures 3 to 8 As shown, this embodiment provides a packaging structure 100, which includes at least one chipset 10, each chipset 10 includes a plurality of semiconductor chips 11 stacked, and the plurality of semiconductor chips 11 in each chipset 10 and / or the connected chipsets 10 are connected via an electrical connection portion 112 exposed to the outside of the side wall of the semiconductor chip 11.

[0078] The specific structure of the electrical connection portion 112 exposed to the side wall of the semiconductor chip 11 involved in this embodiment is described below.

[0079] Reference Figures 3 to 11 The semiconductor chip 11 includes a chip body 111 and a plurality of electrical connection parts 112. The electrical connection parts 112 are arranged in the chip body 111, and each electrical connection part 112 is arranged along the thickness direction of the chip body 111 ( Fig. 9 Typically, the electrical connection portions 112 are evenly distributed in the semiconductor chip 11 in an array form, and the side walls of some of the electrical connection portions 112 are not exposed to the outside of the semiconductor chip 11. It is sufficient as long as the side wall of at least one of the plurality of electrical connection portions 112 is exposed to the outside of the chip body 111, or the side walls of a row or a column of electrical connection portions 112 are exposed to the outside of the chip body 111.

[0080] In some embodiments, reference Fig.10 The chip body 111 includes a first type chip body 111a. In the thickness direction ( Fig. 9 In the z direction shown in , the bottom surface of the first electrical connection portion 112a is located inside the first type chip body 111a, and the top surface of the first electrical connection portion 112a is aligned with the top surface of the first type chip body 111a. Alternatively, the bottom surface of the first electrical connection portion 112a is located inside the first type chip body 111a, and the top surface of the first electrical connection portion 112a protrudes from the top surface of the first type chip body 111a. That is, the top surface of the first electrical connection portion 112a is exposed, and the thickness of the first electrical connection portion 112a is less than the thickness h1 of the first type chip body 111a.

[0081] The semiconductor chip 11 with the first type chip body 111 a provided in this embodiment is usually arranged at the top layer or bottom layer of the chipset 10 , and is electrically connected to other semiconductor chips 11 through the exposed side of the first electrical connection portion 112 a .

[0082] In some embodiments, reference Fig.11 The chip body 111 includes a second type chip body 111b. In the thickness direction of the second type chip body 111b ( Fig. 9 The second electrical connection portion 112b is connected to the chip body 111b of the second type (in the z direction shown in FIG), the bottom surface of the second electrical connection portion 112b is exposed outside the second type chip body 111b, and the top surface of the second electrical connection portion 112b is flush with the top surface of the second type chip body 111b. That is, both ends of the second electrical connection portion 112b are exposed, and the thickness of the second electrical connection portion 112b is equal to the thickness h2 of the second type chip body 111b. Alternatively, the bottom surface of the second electrical connection portion 112b is exposed outside the second type chip body, and the top surface of the second electrical connection portion 112b protrudes from the top surface of the second type chip body 111b, that is, the thickness of the second electrical connection portion 112b is greater than the thickness h2 of the second type chip body 111b.

[0083] The semiconductor chip 11 having the second type chip body 111b provided in this embodiment is usually arranged in the middle layer of the chipset 10 stacked with multiple layers of semiconductor chips 11, and along the thickness direction ( Fig. 9 The second electrical connection portion 112 b penetrating the second type chip body 111 b may be electrically connected to the upper semiconductor chip 11 and the lower semiconductor chip 11 at the same time.

[0084] In an exemplary embodiment, Figures 3 to 8As shown, this embodiment provides a package structure 100, the package structure 100 includes at least one chipset 10, each chipset 10 includes a plurality of semiconductor chips 11 stacked, and the plurality of semiconductor chips 11 in each chipset 10 and / or the connected chipsets 10 are connected via electrical connection portions 112 exposed to the outside of the semiconductor chips 11. The package structure 100 provided in this embodiment may include the structure of the package structure 100 provided in any of the above embodiments.

[0085] In this embodiment, Figures 3 to 6 As shown, the package structure 100 includes a chipset 10, a semiconductor chip 11 in a thickness direction ( Figure 3 In the z direction shown in FIG. 1 ), the electrical connection parts 112 of the plurality of semiconductor chips 11 in the chipset 10 are facing each other. That is, the projections of the electrical connection parts 112 of the plurality of semiconductor chips 11 on the top surface / bottom surface of the semiconductor chip 11 overlap. For example, bonding can be achieved between the facing electrical connection parts 112 by setting welding bumps 32, or bonding can be achieved between the facing electrical connection parts 112 by a hybrid bonding structure formed by a hybrid bonding process, so that electrical connection can be formed between the electrical connection parts 112 of the plurality of semiconductor chips 11, so that the plurality of semiconductor chips 11 can transmit signals through the electrical connection parts 112, thereby realizing the interconnection of the plurality of semiconductor chips 11 in the chipset 10.

[0086] refer to Figure 6 The package structure 100 includes a signal line 31, one end of which is connected to the side wall of the electrical connection portion 112 of any semiconductor chip 11 in the chipset 10. The signal line 31 can be formed by wire bonding technology. The signal line 31 is usually used for electrical connection over a longer distance, such as for electrical connection between a semiconductor chip 11 at a higher position in the chipset 10 and the substrate 20. The material of the signal line 31 is a metal material with good electrical conductivity, such as copper (Cu), gold (Au), and aluminum (Al). The semiconductor chip 11 can be connected to the substrate 20 through the signal line 31.

[0087] In one example, reference Figure 6 , showing that four semiconductor chips 11 are stacked in the chipset 10, the signal line 31 can be connected not only to the side wall of the electrical connection portion 112 of the bottom semiconductor chip 11, but also to the electrical connection portion 112 of the semiconductor chips 11 located in other layers, that is, the signal line 31 can be connected to the electrical connection portion 112 of any semiconductor chip 11, for example, some devices in the packaging structure 100 can be avoided, thereby improving the flexibility of packaging the packaging structure 100, and facilitating efficient and reliable packaging.

[0088] Continue to refer Figure 6, the other end of the signal line 31 can be connected to the substrate 20, so that the semiconductor chip 11 and the substrate 20 can transmit signals, and then transmit signals to the external circuit through the signal channel (not shown) on the substrate 20, such as the memory controller. Here, it should be noted that the substrate 20 can be a packaging substrate or a silicon interposer (Si Interposer), wherein the packaging substrate is a type of circuit board used to carry the chipset 10, which has the characteristics of high density, high precision, high performance, miniaturization and thinness, and can provide support, heat dissipation and protection for the chipset 10, and at the same time provide electrical connection between the chipset 10 and the external circuit. The silicon interposer is arranged between the packaging substrate and the semiconductor chip, and the interconnection and communication between the semiconductor chips 11 can be realized through the routing in the silicon interposer. The memory controller is a bus circuit controller used to manage and plan the transmission speed from the packaging structure 100 to the core processor (Central Processing Unit, referred to as CPU). The memory controller controls the necessary logic to read and write the packaging structure 100, and refreshes the content in the packaging structure 100 (dynamic random access memory) at regular intervals.

[0089] In some embodiments, Figures 3 to 8 As shown, the package structure 100 further includes an interconnection portion 30 , through which the connected electrical connection portions 112 are electrically connected, and some types of interconnections 30 can also enable adjacent electrical connection portions 112 to form a reliable physical connection.

[0090] In one example, reference Figure 4 and Figure 7 , interconnection part 30 (reference Figure 6 ) can be a welding bump 32 (μbump, also called micro bump) formed by a micro-bump interconnection process, and the material of the welding bump 32 can be copper (Cu), tin (Sn), indium (In) or an alloy (such as tin-silver alloy).

[0091] In another example, refer to Figure 5 and Figure 8 , interconnection part 30 (reference Figure 6 ) A hybrid bonding structure formed by a hybrid bonding process (Hybrid Bonding) can be used. Compared with the welding bumps 32 formed by the micro-bump interconnection process, the hybrid bonding structure has a smaller size, higher density, stronger connection performance, and lower signal delay.

[0092] In some embodiments, Figure 3 , Figure 4 , Figure 5 , Figure 7 and Figure 8 As shown, the package structure 100 includes two chipsets 10, and the electrical connection parts 112 of the two chipsets 10 exposed on the side walls are arranged opposite to each other. The side walls of the electrical connection parts 112 of the two chipsets 10 exposed to the outside are provided with interconnection parts 30, so that the semiconductor chips 11 respectively arranged in the two chipsets 10 are electrically connected through the interconnection parts 30.

[0093] This does not limit the technical solution of the present disclosure. The number of chipsets 10 may be other. For example, when the package structure 100 has three chipsets 10, two chipsets 10 may be arranged on both sides of another chipset 10. The three chipsets 10 may be arranged in a line or in an L shape. For another example, when the package structure 100 has four chipsets 10, two chipsets 10 may be arranged relative to each other to form an electrical connection, and the other two chipsets 10 may be arranged relative to each other to form an electrical connection.

[0094] In one example, referring to Figures 3 to 5 , in the thickness direction of the chipset 10 ( Figure 3 In the z direction shown in FIG. 1 , the electrical connection portions 112 of the plurality of semiconductor chips 11 in each chipset 10 are facing each other, that is, the plurality of semiconductor chips 11 in the same chipset 10 are electrically connected. Figure 4 When the two chipsets 10 are arranged relative to each other, the two chipsets 10 are located at the same level ( Figure 3 The electrical connection parts 112 of the semiconductor chip 11 (in the z direction shown in FIG. 1 ) are also arranged opposite to each other, so that the interconnection part 30 (refer to FIG. 1 ) can be arranged between the side walls of the electrical connection parts 112 facing each other. Figure 6 ), so that all the semiconductor chips 11 in the two chip groups 10 are electrically connected.

[0095] In another example, referring to Figure 7 and Figure 8 , the electrical connection parts 112 of two adjacent semiconductor chips 11 in the same chipset 10 are staggered, that is, no electrical connection is formed between the adjacent semiconductor chips 11 in the same chipset 10 (no signal transmission is performed). By staggering the electrical connection parts 112 of adjacent semiconductor chips 11, signal crosstalk between the electrical connection parts 112 can be reduced, and the integrity of signal transmission can be improved. In this embodiment, when the two chipsets 10 are arranged relative to each other, they are located at the same vertical height ( Figure 7 The electrical connection portions 112 of the semiconductor chips 11 (in the z direction shown in FIG. 1 ) are aligned with each other, so that the semiconductor chips 11 disposed in the two chip groups 10 can be electrically connected to each other to transmit signals to each other.

[0096] According to an exemplary embodiment of the present disclosure, Fig.12As shown, an embodiment of the present disclosure provides a method for manufacturing a semiconductor chip, which is used to manufacture the semiconductor chip 11 in the packaging structure provided by any of the above embodiments of the present disclosure.

[0097] Reference Fig.12 , the method for manufacturing a semiconductor chip comprises the following steps:

[0098] Step S110 : providing an initial semiconductor chip, wherein the initial semiconductor chip comprises an initial chip body and a plurality of initial electrical connection portions disposed in the initial chip body.

[0099] In this step, refer to Fig. 9 The initial semiconductor chip 50 includes an initial chip body 51 and a plurality of initial electrical connection parts 52 disposed in the initial chip body 51. The initial chip body 51 includes a complete integrated circuit, and the initial electrical connection parts 52 are electrically connected to the integrated circuit of the initial chip body 51.

[0100] refer to Fig. 9 and Fig.10 , the initial electrical connection portion 52 may be formed in the initial chip body 51 by the following process:

[0101] Step S1: forming an etching hole in the initial chip body 51 by laser or ion etching.

[0102] The etched holes are used to form through silicon vias (TSVs).

[0103] Step S2 : forming an intermediate dielectric layer covering the sidewalls of the etched hole and the top surface of the initial chip body 51 by thermal oxidation or plasma enhanced chemical vapor deposition.

[0104] The material of the intermediate dielectric layer includes silicon oxide, TEOS (tetraethyl orthosilicate) oxide, silicon nitride, polyimide, or a combination thereof.

[0105] Step S3: forming a barrier layer and a seed layer in sequence by physical vapor deposition.

[0106] The material of the barrier layer is titanium, titanium nitride, tantalum nitride, tantalum, tungsten nitride, tungsten, etc. The material of the seed layer is palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), silver (Ag), cobalt (Co), molybdenum (Mo), chromium (Cr) and tungsten (W).

[0107] Step S4: Fill the etched holes with conductive material by electroplating or physical vapor deposition.

[0108] Conductive materials such as metal materials, polysilicon, etc.

[0109] Step S5 , removing part of the conductive material by chemical mechanical polishing, and the remaining conductive material in the etched hole forms a conductive plug, ie, an initial electrical connection portion 52 .

[0110] It can be determined from the above that the initial chip body 51 can be a finished chip that can be used for packaging in conventional technology.

[0111] In one example, when two initial semiconductor chips 50 are packaged, the initial electrical connection portion 52 of one of the initial semiconductor chips 50 faces upward ( Fig. 9 The initial electrical connection portion 52 of another initial semiconductor chip 50 faces downward ( Fig. 9 ), the two initial semiconductor chips 50 are buckled together so that the initial electrical connection portions 52 of the two initial semiconductor chips 50 form an electrical connection.

[0112] That is to say, the manufacturing method provided in the embodiment of the present disclosure can be processed based on the existing finished chip (that is, the initial semiconductor chip 50) without affecting the front-end process technology of the chip, so that the semiconductor chip manufacturing method can process initial semiconductor chips 50 with various different parameters.

[0113] Step S120, removing part of the sidewall of the initial chip body, so that the sidewall of at least one of the multiple initial electrical connection parts is exposed outside the initial chip body, the retained initial chip body forms a chip body, and the retained initial electrical connection parts form multiple electrical connection parts.

[0114] In this step, refer to Fig. 9 It can be determined that the initial electrical connection portion 52 is disposed at a position close to the edge of the initial chip body 51. Therefore, by removing part of the side wall of the initial chip body 51, the side wall of the initial electrical connection portion 52 can be exposed outside the initial chip body 51. The side wall of the initial electrical connection portion 52 can be used to set the interconnection portion 30 (refer to Figure 6 ).

[0115] Among them, refer to Figure 4 and Fig. 9 After removing part of the side wall of the initial chip body 51, the retained initial chip body 51 forms a chip body 111, and the retained initial electrical connection part 52 forms an electrical connection part 112. The chip body 111 and the electrical connection part 112 arranged in the chip body 111 constitute a semiconductor chip 11.

[0116] In the disclosed embodiment, the side wall of the electrical connection portion of the semiconductor chip is exposed to the outside of the side wall of the semiconductor chip, and the semiconductor chip can be electrically connected to other devices through the side wall of the electrical connection portion, making the packaging method more flexible.

[0117] In an exemplary embodiment, this embodiment is a further description of step S120 in the above embodiment. Step S120 may include the following steps:

[0118] Step S121, removing the area between the sidewall of the initial chip body and the sidewall of the initial electrical connection part, and a partial area of ​​the initial electrical connection part, exposing the remaining sidewall of the initial electrical connection part, and the retained initial electrical connection part forms the electrical connection part.

[0119] In this step, refer to Figure 4 and Fig. 9 , the area between the side wall of the initial chip body 51 and the side wall of the initial electrical connection part 52 can be removed, and a partial area of ​​the initial electrical connection part 52 can be removed, and the side wall of the retained initial electrical connection part 52 is exposed to the side wall of the chip body 111.

[0120] In one embodiment, the specific execution steps of step S120 or step S121 are as follows: cutting the initial chip body along the thickness direction of the initial chip body, and the cutting track 40 is parallel to the first direction.

[0121] In this step, refer to Fig. 9 , and combined with Figure 4 , the first direction ( Fig. 9 The x direction shown in FIG. 1 is the arrangement direction of the plurality of electrical connection portions 112, and the first direction is parallel to the thickness direction of the chip body 111 ( Fig. 9 In other words, Fig. 9 The initial chip body 51 is cut at the AA section shown in , and the initial chip body 51 with a larger size is retained, and the retained initial chip body 51 forms the chip body 111.

[0122] In another embodiment, the specific execution steps of step S120 or step S121 may also be as follows: grinding the side wall of the initial chip body close to the initial electrical connection portion to remove a part of the structure of the initial chip body and the initial electrical connection portion.

[0123] Among them, refer to Fig. 9 , in the second direction ( Fig. 9 The width of the initial chip body 51 removed is 29 μm to 31 μm, and the second direction is perpendicular to the first direction ( Fig. 9 The x direction shown in the figure) and the thickness direction of the chip body ( Fig. 9 The width dimension of the initial chip body 51 to be removed can be flexibly set according to the shape and setting position of the initial electrical connection portion 52 .

[0124] In an exemplary embodiment, a method for manufacturing a semiconductor chip includes the following steps:

[0125] Step S110 : providing an initial semiconductor chip, wherein the initial semiconductor chip comprises an initial chip body and a plurality of initial electrical connection portions disposed in the initial chip body.

[0126] Step S120, removing part of the sidewall of the initial chip body, so that the sidewall of at least one of the multiple initial electrical connection parts is exposed outside the initial chip body, the retained initial chip body forms a chip body, and the retained initial electrical connection parts form multiple electrical connection parts.

[0127] Step S130 , removing a portion of the initial chip body in the thickness direction of the initial chip body, so that the top surface and / or the bottom surface of the electrical connection portion is exposed outside the initial chip body.

[0128] First, it should be noted that step S130 may be executed between step S110 and step S120, or may be executed after step S120, and the present disclosure does not impose any further limitations thereto.

[0129] In this step, a portion of the initial chip body 51 may be removed by laser cutting, grinding or other processes.

[0130] Reference Fig. 9 , and combined with Figure 6 The top and bottom surfaces of the electrical connection portion 112 are exposed outside the initial chip body 51 so that when multiple semiconductor chips 11 need to be stacked, the semiconductor chip 11 in the middle layer can be electrically connected to the semiconductor chips 11 on the upper layer and the semiconductor chips 11 on the lower layer through the electrical connection portion 112.

[0131] In one example, referring to Figure 6 , four semiconductor chips 11 are stacked together to form a chipset 10. Figure 6 As an example, in the thickness direction of the chipset 10 ( Figure 6 In the z direction shown in FIG, the bottom surface of the electrical connection portion 112 of the semiconductor chip 11 of the second layer (adjacent to the bottom layer) needs to be connected to the semiconductor chip 11 of the bottom layer, and the top surface of the electrical connection portion 112 of the semiconductor chip 11 of the second layer needs to be connected to the semiconductor chip 11 of the third layer. The top surface of the electrical connection portion 112 of the semiconductor chip 11 of the third layer needs to be connected to the semiconductor chip 11 of the bottom layer. That is, in the stacked state, the semiconductor chips 11 located in the middle layers (the second layer and the third layer) all need to be electrically connected to the two semiconductor chips 11 at the same time.

[0132] In some optional embodiments, referring to Figure 6 The bottom semiconductor chip 11 may be processed by the process described in step S130 so that the bottom surface of the electrical connection portion 112 of the bottom semiconductor chip 11 can contact the top surface of the substrate 20 to form an electrical connection.

[0133] In some embodiments, reference Figure 5 and Figure 8 When a plurality of semiconductor chips 11 are stacked and packaged, the electrical connection portion 112 between two connected chip bodies 111 can be electrically connected through a hybrid bonding process. At present, the hybrid bonding process usually uses copper for hybrid bonding. For example, the electrical connection portions 112 of the two chip bodies 111 can be attached together at room temperature, the temperature is increased and the area of ​​the electrical connection portion 112 is annealed. During this process, the copper will expand to form a hybrid bonding structure. The electrical connection portions 112 of the two chip bodies 111 can be firmly bonded together through the hybrid bonding structure and form an electrical connection.

[0134] In other embodiments, reference Figure 4 and Figure 7 When a plurality of semiconductor chips 11 are stacked and packaged, the electrical connection portion 112 between two connected chip bodies 111 can be electrically connected by a micro-bump interconnection process. The interconnection portion made by the micro-bump interconnection process is referred to as a soldering bump, a micro-bump (μbump, also known as a microbump), etc. by those skilled in the art. For example, a solder ball can be planted on the electrical connection portion 112 of the chip body 111, and the electrical connection portions 112 of the two chip bodies 111 are aligned so that the electrical connection portions 112 of the two chip bodies 111 are connected by the solder ball. Then, a process such as reflow soldering can be used to melt the solder ball, and the solidified solder ball forms a soldering bump, so that the two chip bodies 111 are firmly bonded together and form an electrical connection.

[0135] In some other embodiments, when multiple semiconductor chips are stacked and packaged, according to actual process requirements, the electrical connection parts between two connected chip bodies can partially use a hybrid bonding process and partially use a micro-bump interconnection process to form electrical connections.

[0136] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0137] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0138] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0139] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0140] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0141] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A packaging structure, characterized in that: comprising at least one chipset, each of the chipset comprising a plurality of semiconductor chips stacked; The plurality of semiconductor chips in each chip group and / or the connected chip groups are connected via electrical connection portions exposed to the outside of the sidewalls of the semiconductor chips.

2. The packaging structure according to claim 1, characterized in that: The semiconductor chip comprises: Chip body; A plurality of electrical connection parts are arranged in the chip body, and each of the electrical connection parts extends along the thickness direction of the chip body; A side wall of at least one of the plurality of electrical connection portions is exposed outside the chip body.

3. The packaging structure according to claim 2, characterized in that: The chip body comprises a first type chip body, and in a thickness direction of the first type chip body, a bottom surface of the electrical connection portion is located inside the first type chip body; The top surface of the electrical connection portion is flush with the top surface of the first type chip body, or the top surface of the electrical connection portion protrudes from the top surface of the first type chip body.

4. The packaging structure according to claim 2, characterized in that: The chip body comprises a second type chip body, and in a thickness direction of the second type chip body, a bottom surface of the electrical connection portion is exposed outside the chip body; Wherein, the top surface of the electrical connection portion is flush with the top surface of the second type chip body, or the top surface of the electrical connection portion protrudes from the top surface of the second type chip body; The bottom surface of the electrical connection portion is flush with the bottom surface of the second-type chip body, or the bottom surface of the electrical connection portion protrudes from the bottom surface of the second-type chip body.

5. The packaging structure according to any one of claims 1 to 4, characterized in that: The electrical connection portion includes a conductive plug disposed in a through silicon via.

6. The packaging structure according to claim 1, characterized in that: In the thickness direction of the semiconductor chip, the electrical connection parts of the plurality of semiconductor chips in the chipset are directly opposite to each other; The packaging structure further includes a signal line, one end of which is connected to an electrical connection portion of any semiconductor chip in the chipset; The other end of the signal line is connected to a substrate of the packaging structure, and the substrate is used to carry the chipset.

7. The packaging structure according to claim 1, characterized in that: The packaging structure further includes an interconnection portion, and the two connected electrical connection portions are electrically connected via the interconnection portion.

8. The packaging structure according to claim 7, characterized in that: The number of the chipsets is two, the electrical connection parts of the two chipsets exposed to the outside are arranged opposite to each other, the electrical connection parts of the two chipsets exposed to the outside are electrically connected through the interconnection part, and the interconnection part is connected to the side wall of the electrical connection part.

9. The packaging structure according to claim 8, characterized in that: In the thickness direction of the chipset, the electrical connection parts of the plurality of semiconductor chips in the chipset are facing each other; or, The electrical connection parts of two adjacent semiconductor chips in the same chip group are staggered.

10. The packaging structure according to any one of claims 7 to 9, characterized in that: The interconnection portion includes a hybrid bonding structure or a welding bump.

11. A method for manufacturing a semiconductor chip, characterized in that: include: Providing an initial semiconductor chip, the initial semiconductor chip comprising an initial chip body and a plurality of initial electrical connection portions disposed in the initial chip body; Part of the side wall of the initial chip body is removed to expose the side wall of at least one of the multiple initial electrical connection parts outside the initial chip body, the retained initial chip body forms a chip body, and the retained initial electrical connection parts form multiple electrical connection parts.

12. The method for manufacturing a semiconductor chip according to claim 11, characterized in that: Removing part of the side wall of the initial chip body so that the side wall of at least one of the plurality of initial electrical connection parts is exposed outside the initial chip body, comprising: The area between the side wall of the initial chip body and the side wall of the initial electrical connection part, as well as a partial area of ​​the initial electrical connection part are removed to expose the remaining side wall of the initial electrical connection part, and the retained initial electrical connection part forms the electrical connection part.

13. The method for manufacturing a semiconductor chip according to claim 11 or 12, characterized in that: The plurality of electrical connection portions are arranged along a first direction, and the first direction is perpendicular to the thickness direction of the chip body; Removing part of the side wall of the initial chip body so that the side wall of at least one of the plurality of initial electrical connection parts is exposed outside the initial chip body, comprising: The initial chip body is cut along a thickness direction of the initial chip body, with a cutting track being parallel to the first direction.

14. The method for manufacturing a semiconductor chip according to claim 13, characterized in that: In the second direction, the width of the removed initial chip body is 29 μm to 31 μm; The second direction is perpendicular to the first direction and a thickness direction of the chip body.

15. The method for manufacturing a semiconductor chip according to claim 11, characterized in that: The method for manufacturing the semiconductor chip further includes: In the thickness direction of the initial chip body, a portion of the initial chip body is removed so that the top surface and / or the bottom surface of the electrical connection portion is exposed outside the initial chip body.

16. The method for manufacturing a semiconductor chip according to claim 11, characterized in that: When multiple semiconductor chips are stacked and packaged, the electrical connection parts of two connected chip bodies are electrically connected through a hybrid bonding process or a micro-bump interconnection process.

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