BCD device and preparation method thereof

Abstract

The invention provides a BCD device and a preparation method thereof, the BCD device comprises a substrate, an epitaxial layer, a super junction VDMOS unit and a plurality of planar transistor units, the epitaxial layer is located on a first surface of the substrate, the epitaxial layer is internally provided with a first region and at least one second region, and the second region is internally provided with at least one first medium voltage well; the super-junction VDMOS unit comprises at least two second medium-voltage traps and a back metal layer, the second medium-voltage traps are transversely arranged in the first region at intervals, and the back metal layer is located on the second surface of the substrate and electrically connected with the substrate; part of composition structures of the planar transistor units are located in the first medium-voltage traps in the corresponding second regions. The super-junction VDMOS unit is integrated in the BCD device, compared with a conventional LDMOS unit, the super-junction VDMOS unit has better current capacity, smaller area occupation and higher reliability, the performance and reliability of the BCD device are improved, the first medium-voltage well and the second medium-voltage well are prepared synchronously, and the BCD device has the advantages of being simple in manufacturing method, low in cost, high in reliability and the like.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a BCD device and a preparation method thereof. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integrated process technology. This technology can produce diodes (Bipolar), CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor field effect transistor) and DMOS (Double-diffused Metal Oxide Semiconductor, double diffused metal oxide semiconductor field effect transistor) on the same chip, so it is referred to as BCD technology.

[0003] BCD devices with an operating voltage of 45V to 100V are widely used in automotive electronic products such as DCDC power supplies and motor drives. LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) units are widely used in BCD processes because of the good compatibility brought by their planar structure, but their current capacity is limited and can only meet the use of low-power scenarios. Compared with LDMOS units, VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) units have higher reliability and lower specific on-resistance due to their internal withstand voltage junctions and vertical on-current paths. The super-junction VDMOS unit introduces a super junction structure based on the traditional VDMOS unit, which not only has the characteristics of high input impedance, fast switching speed, high operating frequency, voltage control, good thermal stability, and simple driving circuit of the VDMOS unit, but also overcomes the disadvantage that the on-resistance of the VDMOS unit increases sharply with the breakdown voltage, thereby improving the system efficiency.

[0004] However, the compatibility of superjunction VDMOS cells with traditional BCD processes is poor. Currently, in BCD devices using superjunction VDMOS cells, independent superjunction VDMOS cells are usually packaged together with chips made by BCD processes. Sealing VDMOS cells will increase chip area, increase packaging costs and reduce reliability. Although some BCD devices directly prepare superjunction VDMOS cells on substrates, their manufacturing methods are relatively complex, costly and have low reliability. Summary of the invention

[0005] The object of the present invention is to provide a BCD device and a preparation method thereof, so as to solve the problems of high packaging cost, low reliability, and complex preparation method of the existing BCD device.

[0006] In order to achieve the above object, the present invention provides a BCD device, comprising:

[0007] substrate;

[0008] An epitaxial layer, located on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region, wherein the second region has at least one first medium-voltage well;

[0009] A super junction VDMOS unit, wherein a part of the structure of the super junction VDMOS unit is located in the first region, and the super junction VDMOS unit further comprises a back metal layer, wherein the back metal layer is located on the second surface of the substrate and is electrically connected to the substrate;

[0010] a plurality of planar transistor units, wherein partial constituent structures of the planar transistor units are respectively located in corresponding first medium voltage wells in the second region; and

[0011] The substrate and the epitaxial layer have a first doping type, and the first medium voltage well has a second doping type.

[0012] Optionally, the super junction VDMOS unit includes:

[0013] at least two second medium-pressure wells, the second medium-pressure wells being laterally spaced and arranged in the first region;

[0014] at least two first low-pressure wells, each of which is located on the corresponding second medium-pressure well and in contact with the corresponding second medium-pressure well;

[0015] A first body contact region and a first source contact region are arranged side by side in each of the first low voltage wells; and,

[0016] The first gate structure is located on the epitaxial layer between two adjacent first source contact regions and covers a portion of the two adjacent first source contact regions.

[0017] Optionally, the super junction VDMOS unit further includes:

[0018] a dielectric layer, located on the epitaxial layer;

[0019] a first interconnect structure, located on the dielectric layer and electrically connected to the first body contact region and the first source contact region in the corresponding first low voltage well; and

[0020] The second interconnect structure is located on the dielectric layer and is electrically connected to the corresponding first gate structure.

[0021] Optionally, the epitaxial layer has at least a first sub-epitaxial layer and a second sub-epitaxial layer stacked in sequence from bottom to top, the first medium-pressure well and the second medium-pressure well are both located in the first sub-epitaxial layer and part of the second sub-epitaxial layer, and the bottoms of the first medium-pressure well and the second medium-pressure well are located in the first sub-epitaxial layer.

[0022] Optionally, the first source contact region has the first doping type, and the second medium voltage well, the first low voltage well and the first body contact region all have the second doping type.

[0023] Optionally, the plurality of planar transistor units include at least one of a MOS unit, a triode unit and a diode unit.

[0024] Optionally, the MOS cell includes at least one of a CMOS cell, an NMOS cell and a PMOS cell.

[0025] Optionally, the transistor unit includes at least one of a longitudinal / transverse NPN transistor unit and a longitudinal / transverse PNP transistor unit.

[0026] Optionally, the diode unit includes at least one of a conventional diode unit and a Zener diode unit.

[0027] Optionally, the CMOS unit includes:

[0028] A second low-pressure well and a third low-pressure well are arranged side by side in the corresponding first medium-pressure well;

[0029] A second source contact region and a first drain contact region are located in the second low voltage well;

[0030] A third source contact region and a second drain contact region are located in the third low voltage well; and,

[0031] a second gate structure, located on the epitaxial layer between the second source contact region and the first drain contact region and covering a portion of the second source contact region and the first drain contact region; and,

[0032] The third gate structure is located on the epitaxial layer between the third source contact region and the second drain contact region and covers a portion of the third source contact region and the second drain contact region.

[0033] Optionally, the CMOS unit further includes:

[0034] a dielectric layer, located on the epitaxial layer;

[0035] a third interconnect structure and a fourth interconnect structure, located on the dielectric layer and electrically connected to the second source contact region and the first drain contact region respectively; and,

[0036] a fifth interconnect structure and a sixth interconnect structure, located on the dielectric layer and electrically connected to the third source contact region and the second drain contact region, respectively; and,

[0037] The seventh interconnection structure and the eighth interconnection structure are located on the dielectric layer and are electrically connected to the second gate structure and the third gate structure respectively.

[0038] Optionally, the third low voltage well, the second source contact region and the first drain contact region all have the first doping type, and the second low voltage well, the third source contact region and the second drain contact region all have the second doping type.

[0039] Optionally, the NMOS unit includes:

[0040] A fourth low-pressure well and a fifth low-pressure well are arranged side by side in the corresponding first medium-pressure well;

[0041] A second body contact region and a fourth source contact region are arranged side by side in the fourth low voltage well;

[0042] A third drain contact region is located in the fifth low voltage well, a portion of the fifth low voltage well between the fourth source contact region and the third drain contact region and a portion of the corresponding first medium voltage well are covered by a field oxide layer; and

[0043] A fourth gate structure is located on the epitaxial layer between the fourth source contact region and the third drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fourth source contact region, a portion of the fourth low voltage well and the fifth low voltage well.

[0044] Optionally, the NMOS unit further includes:

[0045] a dielectric layer, located on the epitaxial layer;

[0046] a ninth interconnect structure, located on the dielectric layer and electrically connected to the second body contact region and the fourth source contact region; and

[0047] a tenth interconnect structure, located on the dielectric layer and electrically connected to the third drain contact region; and

[0048] An eleventh interconnect structure is located on the dielectric layer and is electrically connected to the fourth gate structure.

[0049] Optionally, the fifth low voltage well, the fourth source contact region and the third drain contact region all have the first doping type, and the fourth low voltage well and the second body contact region all have the second doping type.

[0050] Optionally, the PMOS unit includes:

[0051] The sixth low-pressure well and the seventh low-pressure well are arranged side by side in the corresponding first medium-pressure well, or the sixth low-pressure well is located outside the first medium-pressure well and extends from the surface of the epitaxial layer to the corresponding first medium-pressure well, and the seventh low-pressure well is located in the first medium-pressure well;

[0052] A third body contact region and a fifth source contact region are arranged side by side in each of the sixth low voltage wells;

[0053] a fourth drain contact region, located in the seventh low voltage well, the seventh low voltage well between the fifth source contact region and the fourth drain contact region being covered by a field oxide layer; and,

[0054] A fifth gate structure is located on the epitaxial layer between the fifth source contact region and the fourth drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fifth source contact region and the seventh low voltage well.

[0055] Optionally, the PMOS unit further includes:

[0056] a dielectric layer, located on the epitaxial layer;

[0057] a twelfth interconnect structure, located on the dielectric layer and electrically connected to the third body contact region and the fifth source contact region;

[0058] a thirteenth interconnect structure, located on the dielectric layer and electrically connected to the fourth drain contact region; and

[0059] A fourteenth interconnect structure is located on the dielectric layer and is electrically connected to the fifth gate structure.

[0060] Optionally, the seventh low voltage well and the third body contact region both have the first doping type, and the sixth low voltage well, the fifth source contact region and the fourth drain contact region all have the second doping type.

[0061] Optionally, the triode unit includes:

[0062] an eighth low-pressure well, a ninth low-pressure well and a tenth low-pressure well, arranged side by side in the corresponding first medium-pressure well; and,

[0063] The emitter contact region, the base contact region and the collector contact region are respectively located in the eighth low-voltage well, the ninth low-voltage well and the tenth low-voltage well.

[0064] Optionally, the triode unit further includes:

[0065] a dielectric layer, located on the epitaxial layer;

[0066] The fifteenth interconnection structure, the sixteenth interconnection structure and the seventeenth interconnection structure are all located on the dielectric layer and are electrically connected to the emitter contact region, the base contact region and the collector contact region, respectively.

[0067] Optionally, the ninth low-voltage well and the base contact region both have the first doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the second doping type; or, the ninth low-voltage well and the base contact region both have the second doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the first doping type.

[0068] Optionally, the epitaxial layer further has a third region, and the third region is covered by a field oxide layer. The BCD device further includes a polysilicon diode unit, and the polysilicon diode unit is located on the field oxide layer covering the third region.

[0069] Optionally, the polysilicon diode unit includes:

[0070] a polysilicon layer located on the field oxide layer covering the third region; and

[0071] The anode contact region and the cathode contact region are respectively located at two ends of the polysilicon layer.

[0072] Optionally, the anode contact region has the first doping type, and the cathode contact region has the second doping type.

[0073] Optionally, the polysilicon diode unit further includes:

[0074] a dielectric layer, located on the epitaxial layer;

[0075] an eighteenth interconnect structure, located on the dielectric layer and electrically connected to the anode contact region; and

[0076] A nineteenth interconnect structure is located on the dielectric layer and is electrically connected to the cathode contact region.

[0077] Optionally, the BCD device further includes a passive device, and the passive device is located in the first area and / or the second area.

[0078] The present invention also provides a method for preparing a BCD device, comprising:

[0079] providing a substrate;

[0080] Forming an epitaxial layer on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region;

[0081] At least two second medium-voltage wells are formed in the first region and are arranged in a laterally spaced manner, and at least one first medium-voltage well is simultaneously formed in the second region, wherein the second medium-voltage well is a part of the structure of the superjunction VDMOS unit;

[0082] forming another part of the structure of the super junction VDMOS unit on the first region and in the second medium voltage well, and simultaneously forming a planar transistor unit on the second region and in the corresponding first medium voltage well; and,

[0083] A back metal layer of the super junction VDMOS unit is formed on the second surface of the substrate, and the back metal layer is electrically connected to the substrate.

[0084] Optionally, the substrate and the epitaxial layer have a first doping type, and the first medium voltage well has a second doping type.

[0085] Optionally, the step of forming another part of the structure of the super junction VDMOS unit on the first region and in the second medium voltage well, and simultaneously forming the planar transistor unit on the second region and in the corresponding first medium voltage well includes: forming a low voltage well of the super junction VDMOS unit in the second medium voltage well, and simultaneously forming a corresponding low voltage well of the planar transistor unit in the corresponding first medium voltage well;

[0086] forming a contact region of the super junction VDMOS unit in the low voltage well of the super junction VDMOS unit, and simultaneously forming a contact region of the planar transistor unit in the low voltage well of the planar transistor unit; and,

[0087] A gate structure of the super junction VDMOS unit is formed on the first region, and a gate structure of the planar transistor unit is simultaneously formed on the second region.

[0088] Optionally, after forming the gate structures of the super junction VDMOS unit and the planar transistor unit, the method further includes:

[0089] forming a dielectric layer on the epitaxial layer; and,

[0090] An interconnection structure of the super junction VDMOS unit and an interconnection structure of the planar transistor unit are formed on the dielectric layer, the interconnection structure of the super junction VDMOS unit is electrically connected to the contact area and gate structure of the super junction VDMOS unit, and the interconnection structure of the planar transistor unit is electrically connected to the contact area and gate structure of the planar transistor unit.

[0091] Optionally, the step of forming the epitaxial layer, the first medium-voltage well and the second medium-voltage well includes:

[0092] forming a first sub-epitaxial layer on the first surface of the substrate, forming a portion of the first medium-voltage well and the second medium-voltage well in the first sub-epitaxial layer, wherein the bottoms of the first medium-voltage well and the second medium-voltage well are located in the first sub-epitaxial layer; and,

[0093] A second sub-epitaxial layer is formed on the first sub-epitaxial layer, and remaining parts of the first medium-voltage well and the second medium-voltage well are formed in the second sub-epitaxial layer.

[0094] Optionally, the planar transistor unit includes at least one of a MOS unit, a triode unit and a diode unit.

[0095] Optionally, the epitaxial layer also has a third region, and the third region is covered by a field oxide layer. When another part of the structure of the super junction VDMOS unit is formed on the first region and in the second medium voltage well, a polysilicon diode unit is also synchronously formed on the field oxide layer on the third region.

[0096] Optionally, the step of forming the polysilicon diode unit on the field oxide layer on the third region includes:

[0097] forming a polysilicon layer on the field oxide layer in the third region; and,

[0098] Contact regions of the polysilicon diode unit are formed at both ends of the polysilicon layer.

[0099] Optionally, after forming the contact region of the polysilicon diode unit, the method further includes:

[0100] forming a dielectric layer on the epitaxial layer; and,

[0101] An interconnection structure of the polysilicon diode unit is formed on the dielectric layer, and the interconnection structure of the polysilicon diode unit is electrically connected to the contact region of the polysilicon diode unit.

[0102] In the BCD device and its preparation method provided by the present invention, a substrate, an epitaxial layer, a superjunction VDMOS unit and a plurality of planar transistor units are included, wherein the epitaxial layer is located on the first surface of the substrate, the epitaxial layer has a first region and at least one second region, and the second region has at least one first medium voltage well; the superjunction VDMOS unit includes at least two second medium voltage wells and a back metal layer, the second medium voltage wells are arranged laterally and spaced in the first region, the back metal layer is located on the second surface of the substrate and is electrically connected to the substrate; and part of the component structure of the planar transistor unit is located in the first medium voltage well in the corresponding second region. The present invention integrates the superjunction VDMOS unit in the BCD device, and the superjunction VDMOS unit has better current capability, less area occupation and higher reliability than the conventional LDMOS unit, which can improve the performance and reliability of the BCD device. Moreover, the first medium voltage well and the second medium voltage well are prepared synchronously, that is, the second medium voltage well is prepared at the same time as the first medium voltage well is prepared, so as to manufacture the superjunction VDMOS unit, which has the advantages of simple manufacturing method, low cost and high reliability.

[0103] In addition, after the back metal layer and the substrate are electrically connected, they can serve as the drain electrode of the super junction VDMOS unit. In the working state, the drain electrode of the super junction VDMOS unit will be connected to a high potential. Since the substrate and the epitaxial layer have a first doping type and the first medium voltage well has a second doping type, the several planar transistor units are fabricated in the first medium voltage well. The epitaxial layer, the substrate and the first medium voltage well are reverse biased to form an isolation island to avoid adverse effects on the several planar transistor units when the substrate is connected to a high potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] Figure 1 A flow chart of a method for preparing a BCD device provided in Embodiment 1 of the present invention;

[0105] Figure 2 to Figure 7 The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the BCD device provided in the first embodiment of the present invention, wherein: Figure 7 A schematic diagram of the structure of a BCD device provided in Embodiment 1 of the present invention;

[0106] Figure 8 A schematic diagram of the structure of a BCD device provided in Embodiment 2 of the present invention;

[0107] Wherein, the accompanying drawings are marked as follows:

[0108] 100-substrate; 101-epitaxial layer; 1011-first sub-epitaxial layer; 1012-second sub-epitaxial layer; 101a-first region; 101b, 101c, 101d, 101e-second region; 101f-third region; 11-1-second medium-pressure well; 11-2, 11-3, 11-4, 11-5-first medium-pressure well; 120-first low-pressure well; 121-second low-pressure well; 122-third low-pressure well; 123-fourth low-pressure well; 124-fifth low-pressure well; 125-sixth low-pressure well ; 126-seventh low-voltage well; 127-eighth low-voltage well; 128-ninth low-voltage well; 129-tenth low-voltage well; 130-first body contact region; 131-first source contact region; 132-second source contact region; 133-first drain contact region; 134-third source contact region; 135-second drain contact region; 136-second body contact region; 137-fourth source contact region; 138-third drain contact region; 139-third body contact region; 140-fifth source contact region; 141-fourth drain contact region ; 142-emitter contact region; 143-base contact region; 144-collector contact region; 145-anode contact region; 146-cathode contact region; 201-first gate structure; 202-second gate structure; 203-third gate structure; 204-fourth gate structure; 205-fifth gate structure; 206-polysilicon layer; 301-first interconnection structure; 302-second interconnection structure; 303-third interconnection structure; 304-seventh interconnection structure; 305-fourth interconnection structure; 306-fifth interconnection structure structure; 307-eighth interconnection structure; 308-sixth interconnection structure; 309-ninth interconnection structure; 310-eleventh interconnection structure; 311-tenth interconnection structure; 312-twelfth interconnection structure; 313-fourteenth interconnection structure; 314-thirteenth interconnection structure; 315-fifteenth interconnection structure; 316-sixteenth interconnection structure; 317-seventeenth interconnection structure; 318-eighteenth interconnection structure; 319-nineteenth interconnection structure; 400-dielectric layer; 500-back metal layer; 600-field oxide layer. DETAILED DESCRIPTION

[0109] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0110] Figure 7 Schematic diagram of the structure of the BCD device provided in this embodiment. Figure 7 As shown, the BCD device includes a substrate 100 , an epitaxial layer 101 , a super junction VDMOS unit, a plurality of planar transistor units and a field oxide layer 600 .

[0111] The substrate 100 has a first surface and a second surface. Figure 7 In the embodiment, the first surface of the substrate 100 is its upper surface, and the second surface of the substrate 100 is its lower surface. In this embodiment, the substrate 100 has a first doping type, and the first doping type is N-type. In some embodiments, the first doping type may also be P-type.

[0112] The epitaxial layer 101 is located on the first surface of the substrate 100. The epitaxial layer 101 has a first region 101a and at least one second region. The first region 101a and the second region are different regions in the epitaxial layer 101, and are used to form various units. In this embodiment, there are four second regions. For the convenience of description, the four second regions are respectively referred to as the second region 101b, the second region 101c, the second region 101d, and the second region 101e.

[0113] In this embodiment, the epitaxial layer 101 also has the first doping type, and the epitaxial layer 101 is a single-layer structure, and the thickness may be, for example, 4 um to 12 um.

[0114] Furthermore, part of the structure of the super junction VDMOS unit is located in the first region 101a. Specifically, the super junction VDMOS unit includes a second medium voltage well 11-1, a first low voltage well 120, a first body contact region 130, a first source contact region 131 and a first gate structure 201. There are at least two second medium voltage wells 11-1, which are arranged in the first region 101a at intervals in the horizontal direction, and the second medium voltage wells 11-1 and the epitaxial layer 101 are arranged in an interval-repeated manner in the horizontal direction to form a super junction structure. The top of the second medium-pressure well 11-1 is at a certain distance from the surface of the epitaxial layer 101. There are at least two first low-pressure wells 120, and the first low-pressure wells 120 correspond to the second medium-pressure wells 11-1 one by one. Each first low-pressure well 120 is located on the corresponding second medium-pressure well 11-1. The first low-pressure well 120 extends from the surface of the epitaxial layer 101 to the inside of the epitaxial layer 101 and contacts the corresponding second medium-pressure well 11-1. The first source contact region 131 and the first body contact region 130 are arranged side by side in each first low-pressure well 120. The first gate structure 201 is located on the epitaxial layer 101 and covers part of the two adjacent first source contact regions 131, covers part of the surface of the two adjacent first low-pressure wells 120, and the epitaxial layer 101 between the two adjacent first low-pressure wells 120.

[0115] Optionally, the depth of the second medium-pressure well 11 - 1 may be 2-8 um.

[0116] In some embodiments, the second medium-pressure well 11 - 1 may also extend from the surface of the epitaxial layer 101 to the inside of the epitaxial layer 101 . In this case, the first low-pressure well 120 is at least partially located in the second medium-pressure well 11 - 1 .

[0117] In this embodiment, the first source contact region 131 has the first doping type, the second medium voltage well 11-1, the first low voltage well 120 and the first body contact region 130 all have the second doping type, and the second doping type is P type, but should not be limited to this. In some embodiments, the second doping type may also be N type.

[0118] The super junction VDMOS unit further includes a first interconnect structure 301, a second interconnect structure 302 and a back metal layer 500, wherein the first interconnect structure 301 and the second interconnect structure 302 are located on the dielectric layer 400, and the back metal layer 500 is located on the second surface of the substrate 100. The first interconnect structure 301 corresponds to the first low voltage well 120 one by one, and is electrically connected to the first source contact region 131 and the first body contact region 130 in the corresponding first low voltage well 120, so as to apply voltage to the corresponding first low voltage well 120 and the second medium voltage well 11-1 through the first source contact region 131 and the first body contact region 130, so as to serve as the source electrode and body electrode of the super junction VDMOS unit. The second interconnect structure 302 corresponds to the first gate structure 201 one by one, and is electrically connected to the corresponding first gate structure 201, so as to apply voltage to the first gate structure 201, so as to serve as the gate electrode of the super junction VDMOS unit. The back metal layer 500 is electrically connected to the substrate 100 and is used to apply a voltage to the substrate 100 to serve as a drain electrode of the super junction VDMOS unit.

[0119] In some embodiments, the material of the back metal layer 500 can be Ti / Ni / Ag or the like.

[0120] In this embodiment, the super junction VDMOS unit is a medium voltage unit, and its operating voltage may be 20V to 100V, but it should not be limited thereto. The super junction VDMOS unit may also be a high voltage unit or a low voltage unit.

[0121] Please continue reading Figure 7In this embodiment, each of the second regions has a first medium-voltage well, and the first medium-voltage well extends from the surface of the epitaxial layer 101 to the inside of the epitaxial layer 101. One of the second regions is used to prepare one of the planar transistor units, and part of the component structures of the planar transistor unit are respectively located in the corresponding first medium-voltage wells in the second region. In this embodiment, the first medium-voltage well has the second doping type.

[0122] It can be understood that after the back metal layer 500 and the substrate 100 are electrically connected, they serve as the drain electrode of the super junction VDMOS unit. In the working state, the drain electrode of the super junction VDMOS unit will be connected to a high potential. Therefore, the planar transistor unit is made in the first medium voltage well, and the substrate 100, the epitaxial layer 101 and the first medium voltage well are reverse biased to form an isolation island to avoid adverse effects on the planar transistor unit when the substrate 100 is connected to a high potential.

[0123] Optionally, the planar transistor structure may be at least one of a MOS cell, a triode cell and a diode cell, wherein the MOS cell may include at least one of a CMOS cell, an NMOS cell and a PMOS cell, the triode cell may include at least one of a longitudinal / lateral NPN triode cell and a longitudinal / lateral PNP triode cell, and the diode cell may include at least one of a conventional diode cell and a Zener diode cell.

[0124] For ease of description, the first medium voltage wells in the second region 101b, the second region 101c, the second region 101d, and the second region 101e are respectively referred to as the first medium voltage well 11-2, the first medium voltage well 11-3, the first medium voltage well 11-4, and the first medium voltage well 11-5. In this embodiment, the second region 11-2 is used to prepare a CMOS cell, and at least part of the structure of the CMOS cell is located in the first medium voltage well 11-2; the second region 101c is used to prepare an NMOS cell, and at least part of the structure of the NMOS cell is located in the first medium voltage well 11-3; the second region 101d is used to prepare a PMOS cell, and at least part of the structure of the PMOS cell is located in the first medium voltage well 11-4; the second region 101e is used to prepare a lateral PNP triode cell, and at least part of the structure of the lateral PNP triode cell is located in the first medium voltage well 11-5.

[0125] Optionally, the depth of each of the first medium-pressure wells may be 2-8 um.

[0126] Specifically, the CMOS cell includes a second low-voltage well 121, a third low-voltage well 122, a second source contact region 132, a first drain contact region 133, a third source contact region 134, a second drain contact region 135, a second gate structure 202, and a third gate structure 203. The second low-voltage well 121 and the third low-voltage well 122 are arranged side by side in the first medium-voltage well 11-2, and both the second low-voltage well 121 and the third low-voltage well 122 extend from the surface of the epitaxial layer 101 to the first medium-voltage well 11-2. The second source contact region 132 and the first drain contact region 133 are located in the second low-voltage well 121 and extend from the surface of the epitaxial layer 101 to the second low-voltage well 121; the third source contact region 134 and the second drain contact region 135 are located in the third low-voltage well 122 and extend from the surface of the epitaxial layer 101 to the third low-voltage well 122. The second gate structure 202 and the third gate structure 203 are both located on the epitaxial layer 101, and the second gate structure 202 is located between the second source contact region 132 and the first drain contact region 133, covering a portion of the epitaxial layer 101 between the second source contact region 132 and the first drain contact region 133; the third gate structure 203 is located between the third source contact region 134 and the second drain contact region 135, covering a portion of the epitaxial layer 101 between the third source contact region 134 and the second drain contact region 135. The epitaxial layer 101 between the first drain contact region 133 and the third source contact region 134 is covered by the field oxide layer 600, and the field oxide layer 600 can isolate the NMOS transistor and the PMOS transistor in the CMOS unit.

[0127] In this embodiment, the third low voltage well 122, the second source contact region 132 and the first drain contact region 133 all have the first doping type, and the second low voltage well 121, the third source contact region 134 and the second drain contact region 135 all have the second doping type.

[0128] The CMOS unit further includes a third interconnect structure 303, a fourth interconnect structure 305, a fifth interconnect structure 306, a sixth interconnect structure 308, a seventh interconnect structure 304 and an eighth interconnect structure 307, and the third interconnect structure 303, the fourth interconnect structure 305, the fifth interconnect structure 306, the sixth interconnect structure 308, the seventh interconnect structure 304 and the eighth interconnect structure 307 are all located on the dielectric layer 400. The third interconnect structure 303, the fourth interconnect structure 305 and the seventh interconnect structure 304 are electrically connected to the second source contact region 132, the first drain contact region 133 and the second gate structure 202, respectively, and respectively serve as the source electrode, the drain electrode and the gate electrode of a MOS tube (NMOS tube in this embodiment) in the CMOS unit. The fifth interconnect structure 306, the sixth interconnect structure 308 and the eighth interconnect structure 307 are electrically connected to the third source contact region 134, the second drain contact region 135 and the third gate structure 203, respectively, and serve as the source electrode, drain electrode and gate electrode of another MOS tube (PMOS tube in this embodiment) in the CMOS unit.

[0129] In this embodiment, the CMOS unit is a low voltage unit, and its operating voltage may be 3V to 5V, but it should not be limited thereto. The CMOS unit may also be a high voltage unit or a medium voltage unit.

[0130] Please continue reading Figure 7The NMOS cell includes a fourth low-voltage well 123, a fifth low-voltage well 124, a second body contact region 136, a fourth source contact region 137, a third drain contact region 138 and a fourth gate structure 204. The fourth low-voltage well 123 and the fifth low-voltage well 124 are arranged side by side in the first medium-voltage well 11-3, and both the fourth low-voltage well 123 and the fifth low-voltage well 124 extend from the surface of the epitaxial layer 101 to the first medium-voltage well 11-3. The second body contact region 136 and the fourth source contact region 137 are arranged side by side in the fourth low-voltage well 123, and extend from the surface of the epitaxial layer 101 to the fourth low-voltage well 123; the third drain contact region 138 is located in the fifth low-voltage well 124, and extends from the surface of the epitaxial layer 101 to the fifth low-voltage well 124. The portion of the fifth low-voltage well 124 and the portion of the corresponding first medium-voltage well 11-3 between the fourth source contact region 137 and the third drain contact region 138 are covered by the field oxide layer 600, and the surface electric field of the fifth low-voltage well 124 is reduced by the field oxide layer 600, thereby increasing the withstand voltage of the NMOS unit. The fourth gate structure 204 is located on the portion of the epitaxial layer 101 between the fourth source contact region 137 and the third drain contact region 138 and on the portion of the surface of the field oxide layer 600 on the fifth low-voltage well 124, covering the portions of the surface of the fourth low-voltage well 123 and the fifth low-voltage well 124, the epitaxial layer 101 between the fourth low-voltage well 123 and the fifth low-voltage well 124, and the portion of the surface of the field oxide layer 600 covering the fifth low-voltage well 124.

[0131] In this embodiment, the fifth low voltage well 124 , the fourth source contact region 137 and the third drain contact region 138 all have the first doping type, and the fourth low voltage well 123 and the second body contact region 136 all have the second doping type.

[0132] The NMOS unit further includes a ninth interconnect structure 309, a tenth interconnect structure 311 and an eleventh interconnect structure 310, and the ninth interconnect structure 309, the tenth interconnect structure 311 and the eleventh interconnect structure 310 are all located on the epitaxial layer 101. The ninth interconnect structure 309 is electrically connected to the second body contact region 136 and the fourth source contact region 137, and serves as the source electrode and body electrode of the NMOS unit. The tenth interconnect structure 311 is electrically connected to the third drain contact region 138, and serves as the drain electrode of the NMOS unit. The eleventh interconnect structure 310 is electrically connected to the fourth gate structure 204, and serves as the gate electrode of the NMOS unit.

[0133] In this embodiment, the NMOS unit is a medium voltage unit, and its operating voltage may be 20V to 100V, but it should not be limited thereto. The NMOS unit may also be a high voltage unit or a low voltage unit.

[0134] Please continue reading Figure 7 The PMOS cell includes a sixth low-voltage well 125, a seventh low-voltage well 126, a third body contact region 139, a fifth source contact region 140, a fourth drain contact region 141 and a fifth gate structure 205. The sixth low-voltage well 125 is located in the epitaxial layer 101 outside the first medium-voltage well 11-4, the seventh low-voltage well 126 is located in the first medium-voltage well 11-4, and the sixth low-voltage well 125 and the seventh low-voltage well 126 both extend from the surface of the epitaxial layer 101 to the first medium-voltage well 11-4. The third body contact region 139 and the fifth source contact region 140 are located in the sixth low-voltage well 125 and extend from the surface of the epitaxial layer 101 to the sixth low-voltage well 125; the fourth drain contact region 141 is located in the seventh low-voltage well 126 and extends from the surface of the epitaxial layer 101 to the seventh low-voltage well 126. The seventh low-voltage well 126 between the fifth source contact region 140 and the fourth drain contact region 141 is covered by the field oxide layer 600, and the surface electric field of the seventh low-voltage well 126 is reduced by the field oxide layer 600, thereby increasing the withstand voltage of the PMOS unit. The fifth gate structure 205 is located on the epitaxial layer 101 between the fifth source contact region 140 and the fourth drain contact region 141 and on a portion of the surface of the field oxide layer 600 covering the seventh low-voltage well 126, and covers a portion of the surface of the sixth low-voltage well 125 and the seventh low-voltage well 126, the epitaxial layer 101 between the sixth low-voltage well 125 and the seventh low-voltage well 126, and a portion of the surface of the field oxide layer 600 on the seventh low-voltage well 126.

[0135] It should be noted that Figure 7 In the embodiment, the side walls of the sixth low-pressure well 125 and the seventh low-pressure well 126 are in direct contact, so the fifth gate structure 205 only covers a portion of the surface of the sixth low-pressure well 125 and the seventh low-pressure well 126 and a portion of the surface of the field oxide layer 600 on the seventh low-pressure well 126.

[0136] In some embodiments, the sixth low-pressure well 125 and the seventh low-pressure well 126 may also be arranged side by side in the first medium-pressure well 11 - 4 .

[0137] In this embodiment, the seventh low voltage well 126 and the third body contact region 139 both have the first doping type, and the sixth low voltage well 125 , the fifth source contact region 140 and the fourth drain contact region 141 all have the second doping type.

[0138] The PMOS unit further includes a twelfth interconnect structure 312, a thirteenth interconnect structure 314 and a fourteenth interconnect structure 313, and the twelfth interconnect structure 312, the thirteenth interconnect structure 314 and the fourteenth interconnect structure 313 are all located on the epitaxial layer 101. The twelfth interconnect structure 312 is electrically connected to the third body contact region 139 and the fifth source contact region 140, and serves as the source electrode and body electrode of the PMOS unit. The thirteenth interconnect structure 314 is electrically connected to the fourth drain contact region 141, and serves as the drain electrode of the PMOS unit. The fourteenth interconnect structure 313 is electrically connected to the fifth gate structure 205, and serves as the gate electrode of the PMOS unit.

[0139] In this embodiment, the PMOS unit is a medium voltage unit, and its operating voltage may be 20V to 100V, but it should not be limited thereto. The PMOS unit may also be a high voltage unit or a low voltage unit.

[0140] Please continue reading Figure 7 The lateral PNP transistor unit includes an eighth low-voltage well 127, a ninth low-voltage well 128, a tenth low-voltage well 129, an emitter contact region 142, a base contact region 143, and a collector contact region 144. The eighth low-voltage well 127, the ninth low-voltage well 128, and the tenth low-voltage well 129 are arranged side by side in the first medium-voltage well 11-5, and the eighth low-voltage well 127, the ninth low-voltage well 128, and the tenth low-voltage well 129 all extend from the surface of the epitaxial layer 101 to the first medium-voltage well 11-5. The emitter contact region 142 is located in the eighth low-pressure well 127 and extends from the surface of the epitaxial layer 101 to the eighth low-pressure well 127; the base contact region 143 is located in the ninth low-pressure well 128 and extends from the surface of the epitaxial layer 101 to the ninth low-pressure well 128; the collector contact region 144 is located in the tenth low-pressure well 129 and extends from the surface of the epitaxial layer 101 to the tenth low-pressure well 129.

[0141] In this embodiment, the ninth low-voltage well 128 and the base contact region 143 have the first doping type, and the eighth low-voltage well 127, the tenth low-voltage well 129, the emitter contact region 142, and the collector contact region 144 all have the second doping type. In some embodiments, the ninth low-voltage well 128 and the base contact region 143 have the second doping type, and the eighth low-voltage well 127, the tenth low-voltage well 129, the emitter contact region 142, and the collector contact region 144 all have the first doping type, thereby forming a lateral NPN transistor unit.

[0142] The lateral PNP triode unit further includes a fifteenth interconnection structure 315, a sixteenth interconnection structure 316 and a seventeenth interconnection structure 317, and the fifteenth interconnection structure 315, the sixteenth interconnection structure 316 and the seventeenth interconnection structure 317 are all located on the epitaxial layer 101. The fifteenth interconnection structure 315 is electrically connected to the emitter contact region 142 and serves as the emitter region electrode of the lateral PNP triode unit. The sixteenth interconnection structure 316 is electrically connected to the base contact region 143 and serves as the base region electrode of the lateral PNP triode unit. The seventeenth interconnection structure 317 is electrically connected to the collector contact region 144 and serves as the collector region electrode of the lateral PNP triode unit.

[0143] As an optional embodiment, a diode unit may be further provided in the second region. The diode unit may be formed by using two well regions with different doping types in the second region, for example, which will not be elaborated herein.

[0144] Please continue reading Figure 7 The epitaxial layer 101 further includes a third region 101f, the third region 101f is covered by the field oxide layer 600, and the BCD device further includes a polysilicon diode unit, the polysilicon diode unit in the third region 101f is located on the field oxide layer 600 covering the third region 101f. In this embodiment, the polysilicon diode unit is used to collect temperature.

[0145] Specifically, the polysilicon diode unit includes an anode contact area 145, a polysilicon layer 206 and a cathode contact area 146. The polysilicon layer 206 is located on the field oxide layer 600 covering the third region 101f. The anode contact area 145 and the cathode contact area 146 are respectively located at two ends of the polysilicon layer 206.

[0146] In this embodiment, the anode contact region 145 has the first doping type, and the cathode contact region 146 has the second doping type.

[0147] The polysilicon diode unit further includes an eighteenth interconnect structure 318 and a nineteenth interconnect structure 319. The eighteenth interconnect structure 318 is electrically connected to the anode contact region 145 and serves as the anode of the polysilicon diode unit. The nineteenth interconnect structure 319 is electrically connected to the cathode contact region 146 and serves as the cathode of the polysilicon diode unit.

[0148] Further, the field oxide layer 600 is also located on the epitaxial layer 101 between two adjacent devices, for isolating the two adjacent devices. For example, in this embodiment, the field oxide layer 600 is also located on the epitaxial layer 101 between the super junction VDMOS unit and the CMOS unit, on the epitaxial layer 101 between the CMOS unit and the NMOS unit, on the epitaxial layer 101 between the NMOS unit and the PMOS unit, on the epitaxial layer 101 between the PMOS unit and the lateral PNP triode unit, and on the epitaxial layer 101 between the lateral PNP triode unit and the polysilicon diode unit. The field oxide layer 600 may extend from the surface of the epitaxial layer 101 to the inside of the epitaxial layer 101, and the top of the field oxide layer 600 may also be higher than the surface of the epitaxial layer 101.

[0149] In this embodiment, the structures of the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204 and the fifth gate structure 205 are similar, and can include a gate oxide layer, a gate electrode layer and a gate dielectric layer 400. The gate oxide layer and the gate electrode layer are stacked from bottom to top to form a stacked structure, and the gate dielectric layer 400 covers the sidewalls and the top of the stacked structure. The portion of the gate electrode layer covering the epitaxial layer 101 is used to form a device channel, and the portion of the gate electrode layer covering the field oxide layer 600 forms a field plate, which helps to optimize the surface electric field and improve the withstand voltage of the device.

[0150] Optionally, the thickness of the field oxide layer 600 may be

[0151] Please continue reading Figure 7The BCD device further includes a dielectric layer 400, and the dielectric layer 400 completely covers the epitaxial layer 101. The first interconnection structure 301, the second interconnection structure 302, the third interconnection structure 303, the fourth interconnection structure 305, the fifth interconnection structure 306, the sixth interconnection structure 308, the seventh interconnection structure 304, the eighth interconnection structure 307, the ninth interconnection structure 309, the tenth interconnection structure 311, the eleventh interconnection structure 310, the twelfth interconnection structure 312, the thirteenth interconnection structure 314, the fourteenth interconnection structure 313, the fifteenth interconnection structure 315, the sixteenth interconnection structure 316, the seventeenth interconnection structure 317, the eighteenth interconnection structure 318, and the nineteenth interconnection structure 319 are all located on the dielectric layer 400, and all have at least a portion of the top surface exposed from the dielectric layer 400. The first interconnect structure 301, the second interconnect structure 302, the third interconnect structure 303, the fourth interconnect structure 305, the fifth interconnect structure 306, the sixth interconnect structure 308, the seventh interconnect structure 304, the eighth interconnect structure 307, the ninth interconnect structure 309, the tenth interconnect structure 311, the eleventh interconnect structure 310, the twelfth interconnect structure 312, the thirteenth interconnect structure 314, the fourteenth interconnect structure 313, the fifteenth interconnect structure 315, the sixteenth interconnect structure 316, the seventeenth interconnect structure 317, the eighteenth interconnect structure 318 and the nineteenth interconnect structure 319 may all include electrically connected plugs and interconnect metal layers, the plugs are located in the dielectric layer 400, and at least a portion of the top surface of the interconnect metal layer is exposed from the dielectric layer 400.

[0152] Furthermore, the dielectric layer 400 may be a single-layer structure or a multi-layer structure. For example, the material of the dielectric layer 400 may be at least one of silicon oxide and silicon nitride.

[0153] Optionally, the BCD device can be applied to new energy vehicles and photovoltaic fields, used in power supplies and motor drive products, and its operating voltage can be 45V to 120V.

[0154] In some embodiments, the BCD device may further include a passive device, which may be located on at least one of the first region 101a, the second region and the third region 101f, thereby forming an ESD structure with the super junction VDMOS unit or the planar transistor unit.

[0155] Based on this, this embodiment also provides a method for preparing the BCD device. Figure 1 Flow chart of the method for preparing the BCD device provided in this embodiment. Figure 1 As shown, the preparation method of the BCD device includes:

[0156] Step S100: providing a substrate;

[0157] Step S200: forming an epitaxial layer on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region;

[0158] Step S300: forming at least two second medium-voltage wells arranged laterally at intervals in the first region, and simultaneously forming at least one first medium-voltage well in the second region, wherein the second medium-voltage well is a part of the structure of the super junction VDMOS unit;

[0159] Step S400: forming another part of the structure of the super junction VDMOS unit on the first region and in the second medium voltage well, and simultaneously forming a planar transistor unit on the second region and in the corresponding first medium voltage well; and,

[0160] Step S500: forming a back metal layer of the super junction VDMOS unit on the second surface of the substrate, wherein the back metal layer is electrically connected to the substrate.

[0161] Figure 2 to Figure 7 The structural diagram corresponding to the corresponding steps of the method for preparing the BCD device provided in this embodiment is shown below. Figure 2 to Figure 7 The preparation method of the BCD device provided in this embodiment is described in detail.

[0162] like Figure 2 As shown, step S100 and step S200 are performed to provide the substrate 100, and epitaxially grow the epitaxial layer 101 of the same doping type on the substrate 100, that is, the substrate 100 and the epitaxial layer 101 have the first doping type. The epitaxial layer 101 includes the first region 101a, at least one of the second regions and the third region 101f.

[0163] like Figure 3 As shown, the field oxide layer 600 is formed on the epitaxial layer 101. For example, the field oxide layer 600 may be formed by a thermal oxidation method, and the third region 101f is covered by the field oxide layer 600.

[0164] like Figure 4As shown, step S300 is performed to synchronously form all the first medium-voltage wells (including the first medium-voltage wells 11-2, 11-3, 11-4, and 11-5) and the second medium-voltage well 11-1 in the epitaxial layer 101 through ion implantation and high-temperature push-junction processes. All the first medium-voltage wells are located in the second region, the second medium-voltage well 11-1 is located in the first region 101a, and the second medium-voltage well 11-1 is a part of the structure of the super junction VDMOS unit. The specific process of forming the first medium-voltage well and the second medium-voltage well 11-1 can be: using a photolithography process to locate the regions of the first medium-voltage well and the second medium-voltage well 11-1, then performing high-energy ion implantation on the located regions, and then performing a high-temperature push-junction process to form the first medium-voltage well and the second medium-voltage well 11-1.

[0165] Optionally, when high-energy ion implantation is performed on the positioning area, the ion implantation can be performed multiple times at different depths of the positioning area, thereby improving the uniformity of the doped ions in the first medium-pressure well and the second medium-pressure well 11-1. For example: ion implantation can be performed six times at different depths of the positioning area, and the positioning area is divided into a first sub-region, a second sub-region, a third sub-region, a fourth sub-region, a fifth sub-region and a sixth sub-region along the depth direction. The first sub-region, the second sub-region, the third sub-region, the fourth sub-region, the fifth sub-region and the sixth sub-region are arranged in sequence from bottom to top, and there is an intersection between two adjacent sub-regions; the first ion implantation process implants ions into the first sub-region, and the implantation energy range is preferably 100keV to 600keV; the second ion implantation process implants ions into the second sub-region, and the implantation energy range is preferably 100keV to 600keV. It is preferably 300keV~900keV. The third ion implantation process performs ion implantation on the third sub-region, and the implantation energy range is preferably 600keV~1200keV. The fourth ion implantation process performs ion implantation on the fourth sub-region, and the implantation energy range is preferably 1100keV~1700keV. The fifth ion implantation process performs ion implantation on the fifth sub-region, and the implantation energy range is preferably 1500keV~2100keV. The sixth ion implantation process performs ion implantation on the sixth sub-region, and the implantation energy range is preferably 1900keV~2500keV.

[0166] Please continue reading Figure 4 , perform step S400, form another part of the structure of the super junction VDMOS unit on the first region 101a and in the second medium voltage well 11-1, and simultaneously form a planar transistor unit on the second region and in the corresponding first medium voltage well. At the same time, a polysilicon diode unit can also be formed on the field oxide layer 600 on the third region 101f.

[0167] First, a low voltage well of the super junction VDMOS unit is formed in the second medium voltage well 11 - 1 , and simultaneously a corresponding low voltage well of the planar transistor unit is formed in the corresponding first medium voltage well.

[0168] Specifically, the first low-pressure well 120 is formed on each of the second medium-pressure wells 11-1 through ion implantation and high-temperature push-junction processes, and the second low-pressure well 121 and the third low-pressure well 122 are formed in the first medium-pressure well 11-2, the fourth low-pressure well 123 and the fifth low-pressure well 124 are formed in the first medium-pressure well 11-3, the sixth low-pressure well 125 is formed in the epitaxial layer 101, the seventh low-pressure well 126 is formed in the first medium-pressure well 11-4, and the eighth low-pressure well 127, the ninth low-pressure well 128 and the tenth low-pressure well 129 are formed in the first medium-pressure well 11-5.

[0169] like Figure 5 As shown, the gate structure of the super junction VDMOS unit is formed on the first region 101a, and the gate structure of the planar transistor unit is simultaneously formed on the second region. At the same time, a polysilicon layer 206 can also be formed on the field oxide layer 600 of the third region 101f.

[0170] In this embodiment, the planar transistor unit includes at least one of a MOS unit, a triode unit and a diode unit.

[0171] Specifically, the first gate structure 201 , the second gate structure 202 , the third gate structure 203 , the fourth gate structure 204 and the fifth gate structure 205 are formed on the epitaxial layer 101 , and the polysilicon layer 206 is also formed at the same time. The method for forming the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204, the fifth gate structure 205 and the polysilicon layer 206 may include: forming gate oxide layers of the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204 and the fifth gate structure 205 on the epitaxial layer 101 by a thermal oxidation method; depositing polysilicon on the epitaxial layer 101, the gate oxide layer and the field oxide layer 600, and then removing part of the polysilicon and retaining the polysilicon on each of the gate oxide layers to form gate electrodes of the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204 and the fifth gate structure 205, retaining the polysilicon on the field oxide layer 600 on the surface of the third region 101f to form the polysilicon layer 206; and forming a gate dielectric layer 400 on the top and sidewall of each of the gate electrodes.

[0172] like Figure 6 As shown, a contact region of the super junction VDMOS unit is formed in the low voltage well of the super junction VDMOS unit, and a contact region of the planar transistor unit is simultaneously formed in the low voltage well of the planar transistor unit. In this step, contact regions of the polysilicon diode unit can also be formed at both ends of the polysilicon layer 206.

[0173] Specifically, the first body contact region 130 and the first source contact region 131 are formed in the first low-pressure well 120 by ion implantation and activation processes, the second source contact region 132 and the first drain contact region 133 are formed in the second low-pressure well 121, the third source contact region 134 and the second drain contact region 135 are formed in the third low-pressure well 122, the second body contact region 136 and the fourth source contact region 137 are formed in the fourth low-pressure well 123, and the fifth low-pressure well 124 is formed. The third drain contact region 138 is formed, the third body contact region 139 and the fifth source contact region 140 are formed in the sixth low-voltage well 125, the fourth drain contact region 141 is formed in the seventh low-voltage well 126, the emitter contact region 142, the base contact region 143 and the collector contact region 144 are formed in the eighth low-voltage well 127, the ninth low-voltage well 128 and the tenth low-voltage well 129, respectively, and the anode contact region 145 and the cathode contact region 146 are formed at both ends of the polysilicon layer 206. All contact regions can be formed simultaneously.

[0174] like Figure 7 As shown, a dielectric layer 400 is formed on the epitaxial layer 101. The dielectric layer 400 entirely covers the epitaxial layer 101, the field oxide layer 600, the first gate structure 201, the second gate structure 202, the third gate structure 203, the fourth gate structure 204, the fifth gate structure 205 and the polysilicon layer 206.

[0175] Afterwards, an interconnection structure of the super junction VDMOS unit, an interconnection structure of the planar transistor unit and an interconnection structure of the polysilicon diode unit are formed on the dielectric layer 101, the interconnection structure of the super junction VDMOS unit is electrically connected to the contact area and gate structure of the super junction VDMOS unit, the interconnection structure of the planar transistor unit is electrically connected to the contact area and gate structure of the planar transistor unit, and the interconnection structure of the polysilicon diode unit is electrically connected to the contact area of ​​the polysilicon diode unit.

[0176] Specifically, the dielectric layer 400 is etched to form a plurality of contact holes, and then the contact holes are filled with conductive materials to form the first interconnection structure 301, the second interconnection structure 302, the third interconnection structure 303, the fourth interconnection structure 305, the fifth interconnection structure 306, the sixth interconnection structure 308, the seventh interconnection structure 304, the eighth interconnection structure 307, the ninth interconnection structure 309, the tenth interconnection structure 311, the eleventh interconnection structure 310, the twelfth interconnection structure 312, the thirteenth interconnection structure 314, the fourteenth interconnection structure 313, the fifteenth interconnection structure 315, the sixteenth interconnection structure 316, the seventeenth interconnection structure 317, the eighteenth interconnection structure 318, and the nineteenth interconnection structure 319. The electrical connection relationship between each interconnection structure and the corresponding contact area and gate structure has been described in detail above and will not be repeated here.

[0177] Next, step S500 is performed to grind the second surface of the substrate 100 to thin the substrate 100 , and evaporate the back metal layer 500 on the second surface of the substrate 100 .

[0178] It should be noted that the preparation method of the above-mentioned BCD device integrates the super junction VDMOS unit, CMOS unit, NMOS unit, PMOS unit, lateral PNP triode unit and polysilicon diode unit in the BCD device. However, those skilled in the art can understand that, depending on the type of device, the above-mentioned method can be slightly modified to integrate other different types of devices in the BCD device.

[0179] The preparation method of the BCD device provided in this embodiment is simple and controllable, with simple process, low cost and high reliability, which improves the compatibility of the traditional BCD process with the super junction VDMOS unit, and can integrate conventional transistor units such as NMOS unit, PMOS unit, CMOS unit, triode unit and diode unit in the BCD device, and can also integrate the super junction VDMOS unit in the BCD device at a lower cost. In addition, the first medium voltage well and the second medium voltage well 11-1 are prepared synchronously, that is, the second medium voltage well 11-1 is prepared at the same time as the first medium voltage well is prepared, so as to manufacture the super junction VDMOS unit, which has the advantages of simple manufacturing method, low cost and high reliability.

[0180] Embodiment 2

[0181] Figure 8 Schematic diagram of the structure of the BCD device provided in this embodiment. Figure 8 As shown, the difference from the first embodiment is that in this embodiment, the epitaxial layer 101 has at least two sub-epitaxial layers, and each of the sub-epitaxial layers has a part of the first medium-voltage well and the second medium-voltage well 11 - 1 .

[0182] Specifically, the epitaxial layer 101 includes a first sub-epitaxial layer 1011 and a second sub-epitaxial layer 1012, the first sub-epitaxial layer 1011 and the second sub-epitaxial layer 1012 are formed by two epitaxy processes, and the first sub-epitaxial layer 1011 and the second sub-epitaxial layer 1012 are arranged in sequence from bottom to top. A portion of the first medium-pressure well and the second medium-pressure well 11-1 are located in the first sub-epitaxial layer 1011, and another portion is located in the second sub-epitaxial layer 1012. That is, the first medium-pressure well and the second medium-pressure well 11-1 are both located in the first sub-epitaxial layer 1011 and a portion of the second sub-epitaxial layer 1012, and the bottoms of the first medium-pressure well and the second medium-pressure well 11-1 are located in the first sub-epitaxial layer 1012.

[0183] Compared with the single-layer epitaxial layer 101, the multi-layer epitaxial layer 101 formed by multiple epitaxy can improve the breakdown voltage of the super junction VDMOS unit and improve the isolation voltage between the substrate 100 and the first medium voltage well and the second medium voltage well 11-1.

[0184] When the BCD device is prepared, the epitaxial layer 101 is formed by at least two epitaxy processes, each time forming a sub-epitaxial layer. After each sub-epitaxial layer is formed, an ion implantation process is performed to form a portion of the first medium-voltage well and the second medium-voltage well 11-1. The thickness of each sub-epitaxial layer can be 3um to 6um, and the total thickness of the formed epitaxial layer 101 can be 6um to 12um. The depth of the first medium-voltage well and the second medium-voltage well 11-1 located in the first sub-epitaxial layer 1011 or in the second sub-epitaxial layer 1012 can be 1um to 4um. The two parts of the first medium-voltage well or the second medium-voltage well 11-1 are connected up and down to form the first medium-voltage well or the second medium-voltage well 11-1 with a total depth of 2um to 4um.

[0185] In this embodiment, the step of forming the epitaxial layer 101, the first medium-voltage well, and the second medium-voltage well 11-1 includes: forming a first sub-epitaxial layer 1011 on the first surface of the substrate 100, forming a portion of the first medium-voltage well and the second medium-voltage well 11-1 in the first sub-epitaxial layer 1011, and the bottoms of the first medium-voltage well and the second medium-voltage well 11-1 are located in the first sub-epitaxial layer 1011. Then, forming a second sub-epitaxial layer 1012 on the first sub-epitaxial layer 1011, and forming the remaining portions of the first medium-voltage well and the second medium-voltage well 11-1 in the second sub-epitaxial layer 1012.

[0186] In the example of the present invention, a two-epitaxy method is used to form the epitaxial layer 101, and ion implantation is performed after each epitaxy to form the first medium-voltage well or the second medium-voltage well 11-1, thereby reducing the difficulty of preparing the first medium-voltage well or the second medium-voltage well 11-1 and forming the first medium-voltage well or the second medium-voltage well 11-1 with a deeper junction depth, thereby improving the isolation voltage between the first medium-voltage well or the second medium-voltage well 11-1 and the substrate 100.

[0187] In summary, the BCD device and its preparation method provided in the embodiment of the present invention include a substrate, an epitaxial layer, a superjunction VDMOS unit and a plurality of planar transistor units, wherein the epitaxial layer is located on the first surface of the substrate, the epitaxial layer has a first region and at least one second region, and the second region has at least one first medium voltage well; the superjunction VDMOS unit includes at least two second medium voltage wells and a back metal layer, the second medium voltage wells are arranged laterally and spaced in the first region, the back metal layer is located on the second surface of the substrate and is electrically connected to the substrate; part of the component structure of the planar transistor unit is located in the first medium voltage well in the corresponding second region. The present invention integrates the superjunction VDMOS unit in the BCD device, and the superjunction VDMOS unit has better current capability, less area occupation and higher reliability than the conventional LDMOS unit, and can improve the performance and reliability of the BCD device. Moreover, the first medium voltage well and the second medium voltage well are prepared synchronously, that is, the second medium voltage well is prepared while the first medium voltage well is prepared, thereby manufacturing the super junction VDMOS unit, which has the advantages of simple manufacturing method, low cost and high reliability.

[0188] In addition, after the back metal layer and the substrate are electrically connected, they can serve as the drain electrode of the super junction VDMOS unit. In the working state, the drain electrode of the super junction VDMOS unit will be connected to a high potential. Since the substrate and the epitaxial layer have a first doping type and the first medium voltage well has a second doping type, the several planar transistor units are fabricated in the first medium voltage well. The epitaxial layer, the substrate and the first medium voltage well are reverse biased to form an isolation island to avoid adverse effects on the several planar transistor units when the substrate is connected to a high potential.

[0189] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0190] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0191] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0192] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A BCD device, characterized in that: include: substrate; An epitaxial layer, located on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region, wherein the second region has at least one first medium-voltage well; A super junction VDMOS unit, comprising at least two second medium voltage wells and a back metal layer, wherein the second medium voltage wells are laterally spaced and arranged in the first region, and the back metal layer is located on the second surface of the substrate and is electrically connected to the substrate; a plurality of planar transistor units, wherein partial constituent structures of the planar transistor units are respectively located in corresponding first medium voltage wells in the second region; and The first medium-pressure well and the second medium-pressure well are prepared synchronously.

2. The BCD device according to claim 1, characterized in that: The substrate and the epitaxial layer have a first doping type, and the first medium voltage well has a second doping type.

3. The BCD device according to claim 2, characterized in that: The super junction VDMOS unit also includes: at least two first low-pressure wells, each of which is located on the corresponding second medium-pressure well and in contact with the corresponding second medium-pressure well; A first body contact region and a first source contact region are arranged side by side in each of the first low voltage wells; and, The first gate structure is located on the epitaxial layer between two adjacent first source contact regions and covers a portion of the two adjacent first source contact regions.

4. The BCD device according to claim 3, characterized in that: The super junction VDMOS unit also includes: a dielectric layer, located on the epitaxial layer; a first interconnect structure, located on the dielectric layer and electrically connected to the first body contact region and the first source contact region in the corresponding first low voltage well; and The second interconnect structure is located on the dielectric layer and is electrically connected to the corresponding first gate structure.

5. The BCD device according to claim 3, characterized in that: The epitaxial layer has at least a first sub-epitaxial layer and a second sub-epitaxial layer stacked in sequence from bottom to top, the first medium-pressure well and the second medium-pressure well are both located in the first sub-epitaxial layer and part of the second sub-epitaxial layer, and the bottoms of the first medium-pressure well and the second medium-pressure well are located in the first sub-epitaxial layer.

6. The BCD device according to claim 3, characterized in that: The first source contact region has the first doping type, and the second medium voltage well, the first low voltage well, and the first body contact region all have the second doping type.

7. The BCD device according to claim 2, characterized in that: The planar transistor unit includes at least one of a MOS unit, a triode unit and a diode unit.

8. The BCD device according to claim 7, characterized in that: The MOS cell includes at least one of a CMOS cell, an NMOS cell and a PMOS cell.

9. The BCD device according to claim 7, characterized in that: The transistor unit includes at least one of a longitudinal / lateral NPN transistor unit and a longitudinal / lateral PNP transistor unit.

10. The BCD device according to claim 7, characterized in that: The diode cell includes at least one of a conventional diode cell and a Zener diode cell.

11. The BCD device according to claim 8, characterized in that: The CMOS unit comprises: A second low-pressure well and a third low-pressure well are arranged side by side in the corresponding first medium-pressure well; A second source contact region and a first drain contact region are located in the second low voltage well; A third source contact region and a second drain contact region are located in the third low voltage well; and, a second gate structure, located on the epitaxial layer between the second source contact region and the first drain contact region and covering a portion of the second source contact region and the first drain contact region; and, The third gate structure is located on the epitaxial layer between the third source contact region and the second drain contact region and covers a portion of the third source contact region and the second drain contact region.

12. The BCD device according to claim 11, characterized in that: The CMOS unit further comprises: a dielectric layer, located on the epitaxial layer; a third interconnect structure and a fourth interconnect structure, located on the dielectric layer and electrically connected to the second source contact region and the first drain contact region respectively; and, a fifth interconnect structure and a sixth interconnect structure, located on the dielectric layer and electrically connected to the third source contact region and the second drain contact region, respectively; and, The seventh interconnection structure and the eighth interconnection structure are located on the dielectric layer and are electrically connected to the second gate structure and the third gate structure respectively.

13. The BCD device according to claim 11, characterized in that: The third low voltage well, the second source contact region and the first drain contact region all have the first doping type, and the second low voltage well, the third source contact region and the second drain contact region all have the second doping type.

14. The BCD device according to claim 8, characterized in that: The NMOS unit comprises: A fourth low-pressure well and a fifth low-pressure well are arranged side by side in the corresponding first medium-pressure well; A second body contact region and a fourth source contact region are arranged side by side in the fourth low voltage well; A third drain contact region is located in the fifth low voltage well, a portion of the fifth low voltage well between the fourth source contact region and the third drain contact region and a portion of the corresponding first medium voltage well are covered by a field oxide layer; and A fourth gate structure is located on the epitaxial layer between the fourth source contact region and the third drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fourth source contact region, a portion of the fourth low voltage well and the fifth low voltage well.

15. The BCD device according to claim 14, characterized in that: The NMOS unit further comprises: a dielectric layer, located on the epitaxial layer; a ninth interconnect structure, located on the dielectric layer and electrically connected to the second body contact region and the fourth source contact region; and a tenth interconnect structure, located on the dielectric layer and electrically connected to the third drain contact region; and An eleventh interconnect structure is located on the dielectric layer and is electrically connected to the fourth gate structure.

16. The BCD device according to claim 14, characterized in that: The fifth low voltage well, the fourth source contact region and the third drain contact region all have the first doping type, and the fourth low voltage well and the second body contact region all have the second doping type.

17. The BCD device according to claim 8, characterized in that: The PMOS unit comprises: The sixth low-pressure well and the seventh low-pressure well are arranged side by side in the corresponding first medium-pressure well, or the sixth low-pressure well is located outside the first medium-pressure well and extends from the surface of the epitaxial layer to the corresponding first medium-pressure well, and the seventh low-pressure well is located in the first medium-pressure well; A third body contact region and a fifth source contact region are arranged side by side in each of the sixth low voltage wells; a fourth drain contact region, located in the seventh low voltage well, the seventh low voltage well between the fifth source contact region and the fourth drain contact region being covered by a field oxide layer; and, A fifth gate structure is located on the epitaxial layer between the fifth source contact region and the fourth drain contact region and on a portion of the surface of the field oxide layer covering a portion of the fifth source contact region and the seventh low voltage well.

18. The BCD device according to claim 17, characterized in that: The PMOS unit further comprises: a dielectric layer, located on the epitaxial layer; a twelfth interconnect structure, located on the dielectric layer and electrically connected to the third body contact region and the fifth source contact region; a thirteenth interconnect structure, located on the dielectric layer and electrically connected to the fourth drain contact region; and A fourteenth interconnect structure is located on the dielectric layer and is electrically connected to the fifth gate structure.

19. The BCD device according to claim 17, wherein: The seventh low voltage well and the third body contact region both have the first doping type, and the sixth low voltage well, the fifth source contact region and the fourth drain contact region all have the second doping type.

20. The BCD device according to claim 8, characterized in that: The triode unit comprises: an eighth low-pressure well, a ninth low-pressure well and a tenth low-pressure well, arranged side by side in the corresponding first medium-pressure well; and, The emitter contact region, the base contact region and the collector contact region are respectively located in the eighth low-voltage well, the ninth low-voltage well and the tenth low-voltage well.

21. The BCD device according to claim 20, characterized in that: The triode unit also includes: a dielectric layer, located on the epitaxial layer; The fifteenth interconnect structure, the sixteenth interconnect structure and the seventeenth interconnect structure are all located on the dielectric layer and are electrically connected to the emitter contact region, the base contact region and the collector contact region, respectively.

22. The BCD device according to claim 20, wherein: The ninth low-voltage well and the base contact region both have the first doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the second doping type; or, the ninth low-voltage well and the base contact region both have the second doping type, and the eighth low-voltage well, the tenth low-voltage well, the emitter contact region and the collector contact region all have the first doping type.

23. The BCD device according to claim 2, characterized in that: The epitaxial layer also has a third region, which is covered by a field oxide layer. The BCD device also includes a polysilicon diode unit, which is located on the field oxide layer covering the third region.

24. The BCD device according to claim 23, characterized in that The polysilicon diode unit comprises: a polysilicon layer located on the field oxide layer covering the third region; and The anode contact region and the cathode contact region are respectively located at two ends of the polysilicon layer.

25. The BCD device according to claim 24, characterized in that The anode contact region has the first doping type, and the cathode contact region has the second doping type.

26. The BCD device according to claim 24, characterized in that The polysilicon diode unit further comprises: a dielectric layer, located on the epitaxial layer; an eighteenth interconnect structure, located on the dielectric layer and electrically connected to the anode contact region; and A nineteenth interconnect structure is located on the dielectric layer and is electrically connected to the cathode contact region.

27. The BCD device according to claim 2, characterized in that: The BCD device further includes a passive device, and the passive device is located on the first area and / or the second area.

28. A method for preparing a BCD device, characterized in that: include: providing a substrate; Forming an epitaxial layer on the first surface of the substrate, wherein the epitaxial layer has a first region and at least one second region; At least two second medium-voltage wells are formed in the first region and are arranged in a laterally spaced manner, and at least one first medium-voltage well is simultaneously formed in the second region, wherein the second medium-voltage well is a part of the structure of the superjunction VDMOS unit; forming another part of the structure of the super junction VDMOS unit on the first region and in the second medium voltage well, and simultaneously forming a planar transistor unit on the second region and in the corresponding first medium voltage well; as well as, A back metal layer of the super junction VDMOS unit is formed on the second surface of the substrate, and the back metal layer is electrically connected to the substrate.

29. The method for preparing a BCD device according to claim 28, characterized in that: The substrate and the epitaxial layer have a first doping type, and the first medium voltage well has a second doping type.

30. The method for preparing a BCD device according to claim 29, wherein: The steps of forming another part of the structure of the super junction VDMOS unit on the first region and in the second medium voltage well, and simultaneously forming the planar transistor unit on the second region and in the corresponding first medium voltage well include: forming a low voltage well of the super junction VDMOS unit in the second medium voltage well, and simultaneously forming a corresponding low voltage well of the planar transistor unit in the corresponding first medium voltage well; forming a gate structure of the super junction VDMOS unit on the first region, and simultaneously forming a gate structure of the planar transistor unit on the second region; and, A contact region of the super junction VDMOS unit is formed in the low voltage well of the super junction VDMOS unit, and a contact region of the planar transistor unit is simultaneously formed in the low voltage well of the planar transistor unit.

31. The method for preparing a BCD device according to claim 30, wherein: After forming the gate structures of the super junction VDMOS unit and the planar transistor unit, the method further includes: forming a dielectric layer on the epitaxial layer; and, An interconnection structure of the super junction VDMOS unit and an interconnection structure of the planar transistor unit are formed on the dielectric layer, the interconnection structure of the super junction VDMOS unit is electrically connected to the contact area and gate structure of the super junction VDMOS unit, and the interconnection structure of the planar transistor unit is electrically connected to the contact area and gate structure of the planar transistor unit.

32. The method for preparing a BCD device according to claim 29, wherein: The steps of forming the epitaxial layer, the first medium-voltage well and the second medium-voltage well include: forming a first sub-epitaxial layer on the first surface of the substrate, forming a portion of the first medium-voltage well and the second medium-voltage well in the first sub-epitaxial layer, wherein the bottoms of the first medium-voltage well and the second medium-voltage well are located in the first sub-epitaxial layer; and, A second sub-epitaxial layer is formed on the first sub-epitaxial layer, and remaining parts of the first medium-voltage well and the second medium-voltage well are formed in the second sub-epitaxial layer.

33. The method for preparing a BCD device according to claim 29, wherein: The planar transistor unit includes at least one of a MOS unit, a triode unit and a diode unit.

34. The method for preparing a BCD device according to claim 29, wherein: The epitaxial layer also has a third region, which is covered by a field oxide layer. When another part of the structure of the super junction VDMOS unit is formed on the first region and in the second medium voltage well, a polysilicon diode unit is also synchronously formed on the field oxide layer on the third region.

35. The method for preparing a BCD device according to claim 34, characterized in that: The step of forming the polysilicon diode unit on the field oxide layer on the third region comprises: forming a polysilicon layer on the field oxide layer in the third region; and, Contact regions of the polysilicon diode unit are formed at both ends of the polysilicon layer.

36. The method for preparing a BCD device according to claim 35, characterized in that: After forming the contact region of the polysilicon diode unit, the method further comprises: forming a dielectric layer on the epitaxial layer; and, An interconnection structure of the polysilicon diode unit is formed on the dielectric layer, and the interconnection structure of the polysilicon diode unit is electrically connected to the contact region of the polysilicon diode unit.

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