Junction termination extension structure, preparation method thereof and power device

Abstract

The invention provides a junction termination extension structure and a preparation method thereof, and a power device, the junction termination extension structure comprises a silicon carbide epitaxial drift layer, a main junction and a plurality of junction termination extension regions, the main junction and the plurality of junction termination extension regions are arranged on the silicon carbide epitaxial drift layer, and the plurality of junction termination extension regions sequentially surround the outer side of the main junction. Each junction termination extension region comprises a surface far away from one side of the silicon carbide epitaxial drift layer, the heights of the surfaces of the plurality of junction termination extension regions are sequentially reduced along the direction from inside to outside, the plurality of junction termination extension regions form a multi-step shape, and the effective implantation dose is distributed in a progressively decreasing manner. Each junction termination extension region comprises a floating region and a plurality of auxiliary rings, the plurality of auxiliary rings sequentially surround the outer side of the floating region, and the junction termination extension region has a spatial modulation type structure, so that an electric field in the junction termination extension structure is uniformly distributed. The junction terminal expansion structure can be applied to a power device, the problem of electric field concentration of a terminal area is relieved, and the breakdown voltage of the device can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of silicon carbide power devices, and in particular to a junction terminal extension structure and a preparation method thereof, and a power device. Background Art

[0002] Ultra-high voltage (≥10kV) silicon carbide power devices have shown great application potential in smart grids and high-voltage DC transmission systems. Breakdown voltage is a core indicator of ultra-high voltage devices. Due to the influence of junction curvature effect, high electric fields often appear at the edge of the main junction of power devices, resulting in the actual breakdown voltage of the device being much lower than the theoretical value.

[0003] Based on this, how to alleviate the electric field concentration effect at the edge of the main junction of the device and make the electric field as evenly distributed as possible to increase the breakdown voltage of the device has become an urgent problem to be solved in the field. Summary of the invention

[0004] The present application proposes a junction terminal extension structure and a preparation method thereof, and a power device, aiming to improve the breakdown voltage of the device.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] In the first aspect, an embodiment of the present application provides a junction terminal extension structure, which includes a silicon carbide epitaxial drift layer, a main junction, and a plurality of junction terminal extension regions, wherein the main junction and the plurality of junction terminal extension regions are arranged on the silicon carbide epitaxial drift layer, and the silicon carbide epitaxial drift layer includes a first surface away from a side of the plurality of junction terminal extension regions, and on a reference plane parallel to the first surface, the plurality of junction terminal extension regions sequentially surround the outside of the main junction. The junction terminal extension region includes a second surface away from a side of the silicon carbide epitaxial drift layer, and along a direction from the inside to the outside, the height of the second surfaces of the plurality of junction terminal extension regions decreases sequentially compared to the first surface. Each junction terminal extension region includes a floating region and a plurality of auxiliary rings, and on the reference plane, the plurality of auxiliary rings sequentially surround the outside of the floating region.

[0007] The junction terminal extension structure provided in the above-mentioned embodiments of the present application is provided with a plurality of junction terminal extension regions on the silicon carbide epitaxial drift layer, wherein the plurality of junction terminal extension regions form a multi-step morphology, and the plurality of junction terminal extension regions all have a spatially modulated structure, so that the electric field in the junction terminal extension structure is evenly distributed, effectively alleviating the electric field concentration phenomenon in the terminal area, and being beneficial to improving the breakdown voltage and power density of the device equipped with the junction terminal extension structure.

[0008] Furthermore, the junction terminal extension structure has a smaller area on the reference plane and has a smaller terminal area ratio, which is beneficial to reducing the size and cost of the device.

[0009] In some embodiments, the junction terminal extension region further includes a third surface close to one side of the silicon carbide epitaxial drift layer, and the third surfaces of the plurality of junction terminal extension regions are flush. The floating region and the auxiliary ring include doping elements, and the floating region and the auxiliary ring respectively form PN junctions with the silicon carbide epitaxial drift layer. In the plurality of junction terminal extension regions, the concentration depth distribution and junction depth of the doping elements in the floating region and the auxiliary ring are the same, and are both smaller than the concentration depth distribution and junction depth of the doping elements in the main junction.

[0010] In some embodiments, in at least two junction terminal extension regions, the width of the floating region is the same. From the inside to the outside, the junction terminal extension region includes the floating region, the 1st auxiliary ring to the nth auxiliary ring in sequence, and in at least two junction terminal extension regions, the width of the i-th auxiliary ring is the same, 1≤i≤n, n≥5, i and n are both natural numbers. In at least two junction terminal extension regions, the spacing between the j-th auxiliary ring and the j+1-th auxiliary ring is the same, 1≤j≤n-1, j is a natural number.

[0011] In some embodiments, a plurality of junction termination extension regions are arranged at equal intervals on the reference plane.

[0012] In some embodiments, the height differences between the second surfaces of any two adjacent junction termination extension regions are equal.

[0013] In some embodiments, in the junction termination extension region, a width of the floating region is less than or equal to a sum of widths and spacings of the plurality of auxiliary rings.

[0014] In some embodiments, the junction terminal extension region includes at least five auxiliary rings, and along the direction from the inside to the outside, the widths of the auxiliary rings in the same junction terminal extension region decrease successively, and the distance between two adjacent auxiliary rings increases successively.

[0015] In some embodiments, along the direction from inside to outside, the junction terminal extension area includes a floating area, the first auxiliary ring to the nth auxiliary ring in sequence, n≥5, and n is a natural number. Let the distance between the i-th auxiliary ring and the i-1-th auxiliary ring be S i , the distance between the first auxiliary ring and the floating area is S1, and the increment of the auxiliary ring spacing is S, then S i =S1+(i-1)×S, where 1<i≤n, and i is a natural number. Let the width of the i-th auxiliary ring be W i , the width of the first auxiliary ring is W1, and the increment of the width of the auxiliary ring is W, then W i =W1-(i-1)×W.

[0016] In a second aspect, an embodiment of the present application provides a method for preparing a junction terminal extension structure, the preparation method comprising: forming a main junction on a silicon carbide epitaxial drift layer.

[0017] A photolithography process is combined with an ion implantation process to simultaneously form N junction terminal extension regions on a silicon carbide epitaxial drift layer, wherein N≥3 and N is a natural number, the silicon carbide epitaxial drift layer includes a first surface away from one side of the plurality of junction terminal extension regions, on a reference plane parallel to the first surface, the N junction terminal extension regions sequentially surround the outside of a main junction, the junction terminal extension region includes a second surface away from one side of the silicon carbide epitaxial drift layer, the junction terminal extension region includes a floating region and a plurality of auxiliary rings, and on the reference plane, the plurality of auxiliary rings sequentially surround the outside of the floating region.

[0018] Combined with N-1 photolithography, the second surfaces of the N junction terminal extension regions are etched N-1 times respectively, and the heights of the second surfaces of the N junction terminal extension regions decrease successively compared to the first surface along the direction from the inside to the outside.

[0019] The above-mentioned preparation method of the present application first forms a main junction on the silicon carbide epitaxial drift layer, and then combines a photolithography process with an ion implantation process to simultaneously form multiple junction terminal extension areas on the silicon carbide epitaxial drift layer, and the multiple junction terminal extension areas are sequentially surrounded by the outside of the main junction, and the depth of ion implantation and the effective implantation dose in the multiple junction terminal extension areas are roughly the same. In addition, each junction terminal extension area includes a floating area and multiple auxiliary rings, and the multiple auxiliary rings are sequentially surrounded by the outside of the floating area to form a spatially modulated junction terminal extension area. At present, in order to minimize the lattice damage caused by ion implantation and increase the activation rate, it is usually necessary to implement ion implantation of silicon carbide wafers in a single-chip operation at a high temperature of 500°C, which leads to high implantation costs. However, the multiple junction terminal extension areas of the present application are realized by only one ion implantation, which can undoubtedly significantly reduce the manufacturing cost.

[0020] Then, the upper surfaces of the multiple junction terminal extension regions are etched, and along the direction from the inside to the outside, the heights of the upper surfaces of the multiple junction terminal extension regions are successively reduced to form a step morphology, so that the effective injection doses of the multiple junction terminal extension regions are distributed in a decreasing manner. The step-etched spatially modulated junction terminal extension structure formed by this preparation method reduces the sensitivity of the breakdown voltage to the ion injection dose, which is beneficial to improving the breakdown voltage of the device and widening the process window of ion injection, thereby improving the device's yield, power density, repeatability and consistency.

[0021] In addition, the junction terminal extension structure obtained by the above-mentioned preparation method has a smaller terminal area ratio and its preparation cost is lower.

[0022] In a third aspect, an embodiment of the present application provides a power device, the power device comprising a substrate, an active region and a junction terminal extension structure in any of the above embodiments, wherein the active region is disposed on the substrate, and the active region comprises a plurality of power device cell structures. The junction terminal extension structure is disposed on the substrate and is located outside the active region.

[0023] The above-mentioned power device has the same structure and beneficial technical effects as the junction terminal extension structure provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0025] Figure 1 A structural diagram of a junction terminal extension structure provided in an embodiment of the present application;

[0026] Figure 2A to Figure 2C A diagram of the steps of preparing a junction terminal extension structure provided in an embodiment of the present application;

[0027] Figure 3 A structural diagram of a power device provided in an embodiment of the present application;

[0028] Figure 4 A schematic diagram of a dual-zone junction terminal extension structure of a silicon carbide IGBT provided in an embodiment of the present application;

[0029] Figure 5 A schematic diagram of a spatial modulation junction terminal extension structure of a silicon carbide IGBT provided in an embodiment of the present application;

[0030] Figure 6 Schematic diagram of the step-etched junction terminal extension structure of the silicon carbide IGBT provided in the embodiment of the present application

[0031] Figure 7 Provided for the embodiments of this application Figure 3 to Figure 6 The breakdown voltage of the four junction terminal extension structures varies with the ion implantation dose;

[0032] Figure 8 Provided for the embodiments of this application Figure 3 to Figure 6 Comparison of electric field distribution of four junction terminal extension structures under the same voltage and the same doping concentration.

[0033] Reference numerals:

[0034] 1. Silicon carbide epitaxial drift layer; 10. Junction terminal extension structure; 11. First surface; 2. Main junction; 3. Junction terminal extension region; 30. Second surface; 31. First junction terminal extension region; 32. Second junction terminal extension region; 33. Third junction terminal extension region; 34. Floating region; 35. Auxiliary ring; 36. Third surface; 4. First mask layer; 5. Second mask layer; 6. Third mask layer; 101. Substrate; 102. Buffer layer; 103. Active region; 104. Base region; 105. First contact region; 106. Second contact region; 107. Gate; 108. Emitter; 109. Collector; 110. Gate oxide layer; d. First junction terminal extension region The thickness of the extension area; d1, the step depth at the junction of the first junction terminal extension area and the second junction terminal extension area; d2, the step depth at the junction of the second junction terminal extension area and the third junction terminal extension area; S1, the distance between the first auxiliary ring and the floating area; S2, the distance between the second auxiliary ring and the first auxiliary ring; S3, the distance between the third auxiliary ring and the second auxiliary ring; S4, the distance between the fourth auxiliary ring and the third auxiliary ring; S5, the distance between the fifth auxiliary ring and the fourth auxiliary ring; W1, the width of the first auxiliary ring; W2, the width of the second auxiliary ring; W3, the width of the third auxiliary ring; W4, the width of the fourth auxiliary ring; W5, the width of the fifth auxiliary ring. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0036] The embodiment of the present application provides a junction terminal extension structure, Figure 1 A structural diagram of the junction terminal extension structure provided in an embodiment of the present application.

[0037] See also Figure 1 The junction terminal extension structure 10 includes a silicon carbide epitaxial drift layer 1, a main junction 2 and multiple junction terminal extension regions 3. The main junction 2 and the multiple junction terminal extension regions 3 are arranged on the silicon carbide epitaxial drift layer 1. The silicon carbide epitaxial drift layer 1 includes a first surface 11 away from the side of the multiple junction terminal extension regions 3, and the first surface 11 is used as the lower surface of the silicon carbide epitaxial drift layer 1.

[0038] Exemplarily, the conductivity type of the silicon carbide epitaxial drift layer 1 may be N-type or P-type.

[0039] Continue to see Figure 1, on a reference plane (e.g., plane XY) parallel to the first surface 11, a plurality of junction termination extension regions 3 sequentially surround the outer side of the main junction 2. The junction termination extension region 3 includes a second surface 30 away from the side of the silicon carbide epitaxial drift layer 1, and along the direction X from the inside to the outside, the height of the second surfaces 30 of the plurality of junction termination extension regions 3 decreases sequentially compared to the first surface 11.

[0040] That is, the plurality of junction termination extension regions 3 form a plurality of steps, and the second surface 30 of the junction termination extension region 3 serves as a step surface. Along the direction X from inside to outside, the heights of the step surfaces of the plurality of steps decrease sequentially.

[0041] Exemplarily, the junction terminal extension structure 10 includes at least three junction terminal extension areas 3. The following embodiments of the present application take the junction terminal extension structure 10 including three junction terminal extension areas 3 as an example. The three junction terminal extension areas 3 are respectively a first junction terminal extension area 31, a second junction terminal extension area 32 and a third junction terminal extension area 33. The first junction terminal extension area 31, the second junction terminal extension area 32 and the third junction terminal extension area 33 are sequentially surrounded by the outside of the main junction 2.

[0042] Along the direction X from inside to outside, the heights of the second surfaces 30 of the first junction termination extension region 31 , the second junction termination extension region 32 and the third junction termination extension region 33 decrease in sequence, forming three steps.

[0043] Continue to see Figure 1 Each junction terminal extension region 3 includes a floating region 34 and a plurality of auxiliary rings 35. On the reference plane, the plurality of auxiliary rings 35 sequentially surround the outer side of the floating region 34. This structure of the junction terminal extension region 3 can be called a "spatial modulation type" structure.

[0044] Exemplarily, in a plurality of junction termination extension regions 3 , the number of auxiliary rings 35 may be set to be the same or different.

[0045] The junction terminal extension structure 10 provided in the above-mentioned embodiment of the present application is provided with a plurality of junction terminal extension regions 3 on the silicon carbide epitaxial drift layer 1, wherein the plurality of junction terminal extension regions 3 form a multi-step morphology, and the plurality of junction terminal extension regions 3 all have a spatially modulated structure, so that the electric field in the junction terminal extension structure 10 is evenly distributed, effectively alleviating the electric field concentration phenomenon in the terminal area, which is beneficial to improving the breakdown voltage and power density of the device equipped with the junction terminal extension structure 10.

[0046] Furthermore, the junction terminal extension structure 10 has a smaller area on the reference plane and has a smaller terminal area ratio, which is beneficial to reducing the size and cost of the device.

[0047] In some embodiments, see Figure 1The junction termination extension region 3 further includes a third surface 36 close to one side of the silicon carbide epitaxial drift layer 1 , and the third surfaces 36 of the plurality of junction termination extension regions 3 are flush.

[0048] It can be understood that the second surface 30 of the junction terminal extension region 3 is its upper surface, and the third surface 36 is its lower surface. The lower surfaces of multiple junction terminal extension regions 3 are flush. Since there is a certain range of dimensional tolerance in the preparation process, in the direction Z, there is a certain range of height deviation in the lower surfaces of multiple junction terminal extension regions 3. Therefore, the lower surfaces of multiple junction terminal extension regions 3 are roughly flush.

[0049] Furthermore, a plurality of junction terminal extension regions 3 have upper surfaces that form multi-level stepped surfaces, and along the direction X from inside to outside, the heights of the upper surfaces of the plurality of junction terminal extension regions 3 decrease successively, that is, the volumes of the plurality of junction terminal extension regions 3 decrease successively.

[0050] In multiple junction terminal extension regions 3, both the floating region 34 and the auxiliary ring 35 include doping elements, and the concentration of the doping elements is distributed according to the depth. This distribution relationship can be called "concentration depth distribution". The concentration depth distribution of the doping elements in the floating region 34 and the auxiliary ring 35 is the same, that is, along the direction Z, at the position with the same distance from the first surface 11, the concentration of the doping elements in the floating region 34 and the auxiliary ring 35 is the same, and the junction depths of the floating region 34 and the auxiliary ring 35 are the same.

[0051] It is understandable that due to a certain range of errors in the preparation process, there are deviations in the concentration depth distribution and junction depth of the doped elements in the floating area 34 and the auxiliary ring 35. Therefore, the concentration depth distribution of the doped elements in the floating area 34 and the auxiliary ring 35 is roughly the same, and the junction depth is roughly the same.

[0052] For example, the concentration range of the doping elements in the floating region 34 and the auxiliary ring 35 is 1×10 16 cm -3 ~1×10 18 cm -3 Based on this, along the direction X from the inside to the outside, since the volumes of the plurality of junction terminal extension regions 3 decrease successively, the effective doses of the doping elements in the plurality of junction terminal extension regions 3 are distributed in a decreasing manner along the direction X from the inside to the outside.

[0053] Exemplarily, the conductive type of the doping elements in the floating region 34 and the auxiliary ring 35 is the same. For example, if the conductive type of the silicon carbide epitaxial drift layer 1 is set to N-type, the doping elements in the floating region 34 and the auxiliary ring 35 are all P-type, and the floating region 34 and the auxiliary ring 35 form a PN junction with the silicon carbide epitaxial drift layer 1. For another example, if the conductive type of the silicon carbide epitaxial drift layer 1 is set to P-type, the doping elements in the floating region 34 and the auxiliary ring 35 are all N-type, and the floating region 34 and the auxiliary ring 35 form a PN junction with the silicon carbide epitaxial drift layer 1.

[0054] In addition, the main junction 2 also includes doping elements, and the concentration depth distribution and junction depth of the doping elements in the floating region 34 and the auxiliary ring 35 are smaller than those in the main junction 2 .

[0055] In some embodiments, see Figure 1 , in at least two junction terminal extension regions 3, the width of the floating region 34 is the same, and the “width of the floating region 34” refers to the size of the floating region 34 along the direction X. Exemplarily, in the first junction terminal extension region 31, the second junction terminal extension region 32, and the third junction terminal extension region 33, the width of the floating region 34 is the same, for example, the width of the floating region 34 is 50 μm.

[0056] Continue to see Figure 1 , in multiple junction terminal extension areas 3, the number of auxiliary rings 35 is set to be the same. Along the direction X from the inside to the outside, each junction terminal extension area 3 includes a floating area 34, the first auxiliary ring to the nth auxiliary ring in sequence, n ≥ 5, and n is a natural number, that is, each junction terminal extension area 3 includes at least five auxiliary rings 35. Among them, in at least two junction terminal extension areas 3, the width of the i-th auxiliary ring is the same, 1 ≤ i ≤ n, and i is a natural number. "The width of the auxiliary ring 35" refers to the size of the auxiliary ring 35 along the direction X.

[0057] Exemplarily, each junction terminal extension area 3 includes five auxiliary rings 35, then in at least two junction terminal extension areas 3, the width of the first auxiliary ring is the same, the width of the second auxiliary ring is the same, the width of the third auxiliary ring is the same, the width of the fourth auxiliary ring is the same, and the width of the fifth auxiliary ring is the same.

[0058] Exemplarily, in the first junction terminal extension region 31 , the second junction terminal extension region 32 , and the third junction terminal extension region 33 , the width of the i-th auxiliary ring is the same.

[0059] See again Figure 1 , there are at least two junction terminal extension areas 3, the spacing between the jth auxiliary ring and the j+1th auxiliary ring is the same, 1≤j≤n-1, j is a natural number.

[0060] Exemplarily, each junction terminal extension area 3 includes five auxiliary rings 35, then in at least two junction terminal extension areas 3, the spacing between the first auxiliary ring and the second auxiliary ring is the same, the spacing between the second auxiliary ring and the third auxiliary ring is the same, the spacing between the third auxiliary ring and the fourth auxiliary ring is the same, and the spacing between the fourth auxiliary ring and the fifth auxiliary ring is the same.

[0061] Exemplarily, in the first junction terminal extension area 31 , the second junction terminal extension area 32 and the third junction terminal extension area 33 , the spacing between the j-th auxiliary ring and the j+1-th auxiliary ring is the same.

[0062] It can be understood that, in at least two junction terminal extension regions 3, by setting the width of the floating region 34 to be the same, the width of the corresponding auxiliary ring 35, and the spacing between the corresponding two auxiliary rings 35 to be the same, thus, by setting the upper surfaces of multiple junction terminal extension regions 3 to be multi-step surfaces, the heights of the floating regions 34 and the auxiliary rings 35 in different junction terminal extension regions 3 are different, and along the direction X from the inside to the outside, it is ensured that the volume range of the doped elements in the multiple junction terminal extension regions 3 is reduced successively.

[0063] Furthermore, in the multiple junction terminal extension regions 3, the concentration depth distribution of the doping elements in the floating region 34 and the auxiliary ring 35 is the same. In this case, along the direction X from the inside to the outside, since the volume range of the doping elements in the multiple junction terminal extension regions 3 is reduced successively, the effective dose of the doping elements in the multiple junction terminal extension regions 3 is distributed in a decreasing manner along the direction X from the inside to the outside.

[0064] In some embodiments, see Figure 1 , on a reference plane (eg, plane XY), a plurality of junction terminal extension regions 3 are arranged at equal intervals.

[0065] It can be understood that the distance between the first junction terminal extension area 31 and the second junction terminal extension area 32 refers to: along the direction X from the inside to the outside, the distance between the auxiliary ring 35 farthest from the floating area 34 in the first junction terminal extension area 31 and the floating area 34 of the second junction terminal extension area 32.

[0066] The distance between the second junction terminal extension area 32 and the third junction terminal extension area 33 refers to: along the direction X from inside to outside, the distance between the auxiliary ring 35 farthest from the floating area 34 in the second junction terminal extension area 32 and the floating area 34 of the third junction terminal extension area 33.

[0067] The distance between the first junction terminal expansion area 31 and the second junction terminal expansion area 32 is equal to the distance between the second junction terminal expansion area 32 and the third junction terminal expansion area 33 .

[0068] Exemplarily, the spacing between the plurality of junction terminal extension regions 3 ranges from 2 μm to 4 μm. For example, the spacing between the plurality of junction terminal extension regions 3 is 2 μm, 2.5 μm, 3 μm, 3.5 μm or 4 μm.

[0069] In some other embodiments, the plurality of junction terminal extension regions 3 may also be arranged at non-equidistant intervals, and the interval between the plurality of junction terminal extension regions 3 may also be less than 2 μm or greater than 4 μm.

[0070] In some embodiments, see Figure 1 , the height difference between the second surfaces 30 of any two adjacent junction terminal extension regions 3 is equal.

[0071] It can be understood that due to the dimensional tolerance within a certain range in the manufacturing process, there is a deviation in the height of the second surface 30 of the junction terminal extension region 3 in the direction Z, and there is a deviation in the height difference between the second surfaces 30 of two adjacent junction terminal extension regions 3. Therefore, the height difference between the second surfaces 30 of any two adjacent junction terminal extension regions 3 is approximately equal.

[0072] Exemplarily, the height difference between the second surface 30 of the first junction terminal extension area 31 and the second surface 30 of the second junction terminal extension area 32 is d1, that is, the step depth at the junction of the first junction terminal extension area 31 and the second junction terminal extension area 32 is d1. The height difference between the second surface 30 of the second junction terminal extension area 32 and the second surface 30 of the third junction terminal extension area 33 is d2, that is, the step depth at the junction of the second junction terminal extension area 32 and the third junction terminal extension area 33 is d2, and the step depth d1 is equal to the step depth d2.

[0073] Exemplarily, the thickness of the first junction terminal extension region 31 is d, the step depth d1 is equal to the step depth d2, and the step depth d1 and the step depth d2 are both equal to 0.35 times the thickness d. For example, if the thickness d of the first junction terminal extension region 31 is 1 μm, the step depth d1 and the step depth d2 are both equal to 350 nm.

[0074] In some embodiments, see Figure 1 In each junction terminal extension area 3, along the direction X from the inside to the outside, the distance between the outer boundary of the floating area 34 and the outer boundary of the outermost auxiliary ring 35 is the sum of the widths and spacings of the multiple auxiliary rings 35, and the width of the floating area 34 is less than or equal to the sum of the widths and spacings of the multiple auxiliary rings 35.

[0075] Exemplarily, in the first junction termination extension region 31 , the second junction termination extension region 32 , and the third junction termination extension region 33 , the width of the floating region 34 is equal to the sum of the widths and the spacings of the plurality of auxiliary rings 35 .

[0076] In some embodiments, see Figure 1Each junction terminal extension area 3 includes at least five auxiliary rings 35. Along the direction X from the inside to the outside, the width of the auxiliary rings 35 of the same junction terminal extension area 3 decreases successively, and the distance between two adjacent auxiliary rings 35 increases successively.

[0077] Exemplarily, along the direction X from inside to outside, each junction terminal extension region 3 includes a floating region 34, a first auxiliary ring to an nth auxiliary ring in sequence, where n≥5, and n is a natural number.

[0078] Let the width of the i-th auxiliary ring be W i , the width of the first auxiliary ring is W1, the width increment of the auxiliary ring 35 is W, then W i =W1-(i-1)×W, where 1<i≤n, and i is a natural number.

[0079] Taking the junction terminal extension area 3 including five auxiliary rings 35 as an example, according to the above formula, the width of the second auxiliary ring is W2=W1-W, the width of the third auxiliary ring is W3=W1-2W, the width of the fourth auxiliary ring is W4=W1-3W, and the width of the fifth auxiliary ring is W5=W1-4W. Along the direction X from the inside to the outside, the width of the auxiliary ring 35 decreases successively.

[0080] For example, the width W1 of the first auxiliary ring is 8 μm, and the width increment W of the auxiliary ring 35 is 1 μm, then the width W2 of the second auxiliary ring is 7 μm, the width W3 of the third auxiliary ring is 6 μm, the width W4 of the fourth auxiliary ring is 5 μm, and the width W5 of the fifth auxiliary ring is 4 μm. Along the direction X from the inside to the outside, the width of the auxiliary ring 35 decreases successively.

[0081] And, let the distance between the i-th auxiliary ring and the i-1-th auxiliary ring be S i , the distance between the first auxiliary ring and the floating area 34 is S1, and the increment of the distance between the auxiliary ring 35 is S, then S i =S1+(i-1)×S, where 1<i≤n, and i is a natural number.

[0082] Taking the junction terminal expansion area 3 including five auxiliary rings 35 as an example, according to the above formula, the distance between the second auxiliary ring and the first auxiliary ring is S2=S1+S, the distance between the third auxiliary ring and the second auxiliary ring is S3=S1+2S, the distance between the fourth auxiliary ring and the third auxiliary ring is S4=S1+3S, and the distance between the fifth auxiliary ring and the fourth auxiliary ring is S5=S1+4S. Along the direction X from the inside to the outside, the distance between two adjacent auxiliary rings 35 increases successively.

[0083] For example, the spacing S1 between the first auxiliary ring and the floating area 34 is 2μm, and the increment S of the spacing of the auxiliary rings 35 is 1μm, then the spacing S2 between the second auxiliary ring and the first auxiliary ring is 3μm, the spacing S3 between the third auxiliary ring and the second auxiliary ring is 4μm, the spacing S4 between the fourth auxiliary ring and the third auxiliary ring is 5μm, and the spacing S5 between the fifth auxiliary ring and the fourth auxiliary ring is 6μm. Along the direction X from the inside to the outside, the spacing between two adjacent auxiliary rings 35 increases successively.

[0084] In some embodiments, the junction termination extension structure 10 further includes a scribe groove, which is disposed outside the plurality of junction termination extension regions 3. For example, the upper surface (second surface 30) of the third junction termination extension region 33 located at the outermost side is equal to the height of the upper surface of the scribe groove, that is, the upper surface of the third junction termination extension region 33 is coplanar with the upper surface of the scribe groove.

[0085] The embodiment of the present application also provides a method for preparing the above-mentioned junction terminal extension structure 10. Figure 2A to Figure 2C The steps of preparing the junction terminal extension structure provided in the embodiment of the present application are shown in FIG. 1 . The method for preparing the junction terminal extension structure 10 includes the following steps S1 to S3:

[0086] Step S1: See Figure 2A , a main junction 2 is formed on the silicon carbide epitaxial drift layer 1.

[0087] Exemplarily, the main junction 2 is formed on the silicon carbide epitaxial drift layer 1 by using an ion implantation process.

[0088] Step S2: Continue to see Figure 2A , a photolithography process is combined with an ion implantation process to simultaneously form N junction terminal extension regions 3 on the silicon carbide epitaxial drift layer 1, where N ≥ 3, and N is a natural number. On a reference plane (e.g., plane XY), the N junction terminal extension regions 3 surround the outside of the main junction 2 in sequence, and the junction terminal extension region 3 includes a second surface 30 away from the side of the silicon carbide epitaxial drift layer 1. Each junction terminal extension region 3 includes a floating region 34 and a plurality of auxiliary rings 35, and on the reference plane, the plurality of auxiliary rings 35 surround the outside of the floating region 34 in sequence.

[0089] Exemplarily, a first mask layer 4 is first formed on the silicon carbide epitaxial drift layer 1, and the first mask layer 4 is patterned in combination with a first photomask and a photolithography process to form a plurality of vias in the first mask layer 4. Then, a primary ion implantation process is adopted, with the first mask layer 4 as a shield, and ions with set energy and dosage are implanted into the silicon carbide epitaxial drift layer 1 through the plurality of vias of the first mask layer 4, so as to form a floating region 34 and a plurality of auxiliary rings 35 of a first junction terminal extension region 31, a floating region 34 and a plurality of auxiliary rings 35 of a second junction terminal extension region 32, and a floating region 34 and a plurality of auxiliary rings 35 of a third junction terminal extension region 33 arranged in sequence along a direction X from inside to outside.

[0090] It can be understood that the implanted ions in the floating region 34 and the auxiliary ring 35 are the “doping elements” mentioned above. For example, if the conductivity type of the silicon carbide epitaxial drift layer 1 is set to N type, the implanted ions can be P type ions, and the floating region 34 and the auxiliary ring 35 form a PN junction with the silicon carbide epitaxial drift layer 1. For another example, if the conductivity type of the silicon carbide epitaxial drift layer 1 is set to P type, the implanted ions can be N type ions, and the floating region 34 and the auxiliary ring 35 form a PN junction with the silicon carbide epitaxial drift layer 1.

[0091] Step S3: See Figure 2B to Figure 2C Combined with N-1 photolithography, the second surfaces 30 of the N junction terminal extension regions 3 are etched N-1 times respectively, and along the direction X from the inside to the outside, the heights of the second surfaces 30 of the N junction terminal extension regions 3 compared to the first surface 11 decrease successively.

[0092] Exemplarily, step S3 may include the following steps S31-S32:

[0093] Step S31: See Figure 2B First, a second mask layer 5 is formed on the silicon carbide epitaxial drift layer 1, and the second mask layer 5 is patterned by combining the second photomask and the photolithography process, so that the second mask layer 5 covers the main junction 2 and the first junction terminal extension region 31, and exposes the second junction terminal extension region 32 and the third junction terminal extension region 33. Then, a reactive ion etching process is used to etch the second surface 30 of the second junction terminal extension region 32 and the third junction terminal extension region 33, so that the height of the second surface 30 of the second junction terminal extension region 32 and the third junction terminal extension region 33 compared to the first surface 11 is lower than the height of the second surface 30 of the first junction terminal extension region 31 compared to the first surface 11, thereby forming a step at the junction of the first junction terminal extension region 31 and the second junction terminal extension region 32.

[0094] Step S32: See Figure 2CFirst, a third mask layer 6 is formed on the silicon carbide epitaxial drift layer 1, and the third mask layer 6 is patterned by combining the third photomask and the photolithography process, so that the third mask layer 6 covers the main junction 2, the first junction terminal extension region 31 and the second junction terminal extension region 32, and exposes the third junction terminal extension region 33. Then, a reactive ion etching process is used to etch the second surface 30 of the third junction terminal extension region 33, so that the height of the second surface 30 of the third junction terminal extension region 33 compared to the first surface 11 is lower than the height of the second surface 30 of the second junction terminal extension region 32 compared to the first surface 11, thereby forming a step at the junction of the second junction terminal extension region 32 and the third junction terminal extension region 33, so as to complete the preparation of the junction terminal extension structure 10.

[0095] The above-mentioned preparation method of the present application first forms the main junction 2 on the silicon carbide epitaxial drift layer 1 by using an ion implantation process, and then combines a photolithography process with an ion implantation process to simultaneously form multiple junction terminal extension regions 3 on the silicon carbide epitaxial drift layer 1, and the multiple junction terminal extension regions 3 are sequentially surrounded by the outside of the main junction 2, and the depth of ion implantation and the effective implantation dose in the multiple junction terminal extension regions 3 are substantially the same. In addition, each junction terminal extension region 3 includes a floating region 34 and multiple auxiliary rings 35, and the multiple auxiliary rings 35 are sequentially surrounded by the outside of the floating region 34 to form a spatially modulated junction terminal extension region 3.

[0096] Then, the upper surfaces of the plurality of junction terminal extension regions 3 are etched, and along the direction X from the inside to the outside, the heights of the upper surfaces of the plurality of junction terminal extension regions 3 are successively reduced to form a step morphology, so that the effective implantation doses of the plurality of junction terminal extension regions 3 are distributed in a decreasing manner. The step-etched spatially modulated junction terminal extension structure formed by the preparation method reduces the sensitivity of the breakdown voltage to the ion implantation dose, which is beneficial to improving the breakdown voltage of the device and broadening the process window of ion implantation, thereby improving the device yield, power density, repeatability and consistency.

[0097] In addition, the junction terminal extension structure 10 obtained by the above-mentioned preparation method has a smaller terminal area ratio and its preparation cost is relatively low.

[0098] In some embodiments, after step S3, the method for preparing the junction terminal extension structure 10 further includes the following step S4:

[0099] Step S4 : depositing dielectric material to form a protective passivation dielectric layer, the protective passivation dielectric layer covers the surface of the junction terminal extension structure 10 , and plays a role in protecting and passivating the surface of the junction terminal extension structure 10 .

[0100] An embodiment of the present application also provides a power device, which includes the above-mentioned junction terminal extension structure 10. The power device can be, for example, a silicon carbide insulated gate bipolar transistor (IGBT) or a metal-oxide semiconductor field-effect transistor (MOSFET) or various diodes, thyristors and other types of power devices.

[0101] Taking the power device as silicon carbide IGBT as an example, Figure 3 A structural diagram of a power device provided in an embodiment of the present application.

[0102] See also Figure 3 The power device 100 includes a substrate 101, a buffer layer 102 and an active region 103, wherein the substrate 101 may be a collector layer of an IGBT, and the buffer layer 102 is stacked on the substrate 101. For example, the collector layer is doped with P + ions, the buffer layer 102 is doped with N + ion.

[0103] The active region 103 includes a cellular structure of multiple power devices arranged on the substrate 101, each cellular structure includes a silicon carbide epitaxial drift layer 1 (also called a "drift region"), a base region 104, a first contact region 105, a second contact region 106, a gate 107, an emitter 108, and a collector 109. The base region 104 and the first contact region 105 are located in the silicon carbide epitaxial drift layer 1, the first contact region 105 is embedded in the base region 104, the second contact region 106 is arranged on the outside of the first contact region 105, the gate 107 and the emitter 108 are arranged on the silicon carbide epitaxial drift layer 1, a gate oxide layer 110 is spaced between the gate 107 and the silicon carbide epitaxial drift layer 1, the emitter 108 is in electrical contact with the first contact region 105 and the second contact region 106, and the collector 109 is arranged on the side of the substrate 101 away from the buffer layer 102.

[0104] For example, the silicon carbide epitaxial drift layer 1 is doped with N - ions, the concentration of ion doping is 2×10 14 cm -3 The thickness of the drift region is 100 μm. The base region 104 is doped with P - ions, the first contact region 105 is doped with N + ions, the second contact region 106 is doped with P + Ions. Exemplarily, the material of the gate oxide layer 110 may be silicon dioxide (chemical formula: SiO2).

[0105] The power device 100 further includes the junction terminal extension structure 10, which is stacked on the side of the buffer layer 102 away from the substrate 101, and the junction terminal extension structure 10 is located outside the active area 103. Exemplarily, the main junction 2, the floating area 34 in the junction terminal extension area 3, and the auxiliary ring 35 are all doped with P + ions, the main junction 2, the floating region 34 and the auxiliary ring 35 all form a PN junction with the silicon carbide epitaxial drift layer 1, and the number of the auxiliary rings 35 is five. Exemplarily, along the direction X from the inside to the outside, the total length of the first junction terminal extension region 31, the second junction terminal extension region 32 and the third junction terminal extension region 33 is 300 μm, and the first junction terminal extension region 31, the second junction terminal extension region 32 and the third junction terminal extension region 33 are arranged at equal intervals, and the interval is 2 μm.

[0106] It is understandable that the second contact region 106 in the cell structure and the main junction 2 in the junction terminal extension structure 10 can be formed simultaneously, for example, by using a single ion implantation process to implant P into the silicon carbide epitaxial drift layer 1. + ions, and the second contact region 106 and the main junction 2 are formed synchronously, and the second contact region 106 and the main junction 2 may be connected.

[0107] In order to verify the performance of the junction terminal extension structure 10 in the power device 100, the inventors of the present application conducted the following comparative numerical simulations:

[0108] Figure 4 A schematic diagram of a dual-zone junction terminal extension structure of a silicon carbide IGBT provided in an embodiment of the present application; Figure 5 A schematic diagram of a spatial modulation junction terminal extension structure of a silicon carbide IGBT provided in an embodiment of the present application; Figure 6 A schematic diagram of a stepped etched junction terminal extension structure of a silicon carbide IGBT provided in an embodiment of the present application.

[0109] See also Figure 4 , which is similar to the above-mentioned power device 100 in that: N of the silicon carbide IGBT device - The thickness of the drift region is also 100 μm, and the ion doping concentration is 2×10 14 cm -3 , the total length of the junction terminal extension structure is 300 μm.

[0110] The difference from the above power device 100 is that the silicon carbide IGBT device has a dual-zone junction terminal extension structure, which includes a junction terminal extension 1 and a junction terminal extension 2, respectively. The lengths of the junction terminal extension 1 and the junction terminal extension 2 are both 150 μm, and the surface heights of the junction terminal extension 1 and the junction terminal extension 2 are the same. The junction terminal extension 1 and the junction terminal extension 2 are formed by two ion implantation processes, respectively, wherein the implantation dose of the junction terminal extension 1 is greater than the implantation dose of the junction terminal extension 2, and the implantation dose ratio of the junction terminal extension 1 to the junction terminal extension 2 is 1.5, and the effective implantation dose of the dual-zone junction terminal extension structure formed is distributed in a decreasing manner from the inside to the outside.

[0111] See also Figure 5 , which is similar to the above-mentioned power device 100 in that: N of the silicon carbide IGBT device - The thickness of the drift region is also 100 μm, and the ion doping concentration is 2×10 14 cm -3 , the total length of the junction terminal extension structure is 300 μm.

[0112] The difference from the above-mentioned power device 100 is that the silicon carbide IGBT device has a spatial modulation junction terminal extension structure, wherein the length of the floating region is 250 μm, the number of auxiliary rings is five, the sum of the width and spacing of the five auxiliary rings is 50 μm, and the setting rules of the width and spacing of the auxiliary rings are the same as described above.

[0113] See also Figure 6 , which is similar to the above-mentioned power device 100 in that: N of the silicon carbide IGBT device - The thickness of the drift region is also 100 μm, and the ion doping concentration is 2×10 14 cm -3 The total length of the junction terminal extension structure is 300 μm. The silicon carbide IGBT device also has three junction terminal extension regions, which are arranged at equal intervals and have a spacing of 2 μm to form a step-etched junction terminal extension structure.

[0114] The difference from the above-mentioned power device 100 is that in each junction terminal extension region of the silicon carbide IGBT device, only a floating region is provided, and no auxiliary ring is provided.

[0115] right Figure 3 to Figure 6 The junction terminal extension structures of four SiC IGBT devices in the numerical simulation are shown in Figure 2. Figure 7 The breakdown voltage of the four devices shown varies with the ion implantation dose.

[0116] Depend on Figure 7 Available, Figure 3The junction terminal extension structure of the device (the terminal structure of the present invention) has a process window of ion implantation of 1.4×10 13 cm -2 (0.8×10 13 cm -2 ~2.2×10 13 cm -2 ), approximately Figure 4 The process window of the dual-zone junction termination extension structure is three times that of the conventional structure, and is about Figure 5 The process window of the spatial modulation type junction termination extension structure is eight times larger. And, Figure 6 The process window of the middle step etched junction terminal extension structure is also smaller than the process window of the terminal structure of the present invention, which indicates that the step etched spatial modulation junction terminal extension structure proposed by the present invention reduces the sensitivity of the breakdown voltage to the ion implantation dose and enhances the resistance of the terminal structure to process fluctuations and material defects, thereby effectively improving the yield, repeatability and consistency of the device. In addition, the maximum breakdown voltage of the step etched spatial modulation junction terminal extension structure in the present invention is 13.8 kV, which is about 92% of the theoretical value.

[0117] Figure 8 It is a comparison diagram of the electric field distribution of the step-etched spatial modulation type junction terminal extension structure, the dual-zone junction terminal extension structure, the spatial modulation type junction terminal extension structure and the step-etched type junction terminal extension structure under the same doping concentration and the same voltage.

[0118] See also Figure 8 , the horizontal axis is the horizontal distance between the junction terminal extension structure and its main junction, the unit is (μm); the vertical axis is the electric field intensity of the junction terminal extension structure, the unit is (MV / cm). It can be seen that Figure 4 The peak value of the electric field strength of the dual-zone junction terminal extension structure is 1.93MV / cm, which appears on the junction terminal extension structure at a distance of about 300μm from the main junction, which is the outer edge of the junction terminal extension structure. Figure 5 The peak value of the electric field intensity of the spatially modulated junction terminal extension structure is 2.27MV / cm, which also appears on the junction terminal extension structure at a distance of about 300μm from the main junction, at the outer edge of the junction terminal extension structure, showing an obvious electric field concentration effect. Figure 6 The peak value of the electric field intensity of the step-etched junction terminal extension structure is 1.44MV / cm, which appears on the junction terminal extension structure at a distance of about 200μm from the main junction.

[0119] The electric field distribution in the step-etched spatial modulation type junction terminal extension structure of the present invention is more uniform, which effectively improves the problem of electric field concentration in the terminal area. For example, under the condition that the voltage of the collector is 10kV, the peak value of its electric field strength is only 1.37MV / cm, which is significantly lower than the peak value of the electric field strength of the dual-zone junction terminal extension structure, the spatial modulation type junction terminal extension structure and the step-etched type junction terminal extension structure, and effectively improves the terminal efficiency. In addition, the terminal length of the step-etched spatial modulation type junction terminal extension structure is only three times the thickness of the drift region, and has a smaller terminal area ratio, which can effectively reduce the preparation cost of ultra-high voltage silicon carbide power devices. Therefore, the junction terminal extension structure in the present invention shows obvious advantages in terms of the compromise between process window, terminal efficiency, terminal area ratio and preparation process complexity.

[0120] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A junction terminal extension structure, characterized in that: include: Silicon carbide epitaxial drift layer; A main junction and a plurality of junction terminal extension regions are arranged on the silicon carbide epitaxial drift layer, the silicon carbide epitaxial drift layer comprises a first surface away from the plurality of junction terminal extension regions, and on a reference plane parallel to the first surface, the plurality of junction terminal extension regions sequentially surround the outside of the main junction; the junction terminal extension region comprises a second surface away from the silicon carbide epitaxial drift layer, and along a direction from inside to outside, the heights of the second surfaces of the plurality of junction terminal extension regions sequentially decrease compared to the first surface; The junction terminal extension area includes a floating area and a plurality of auxiliary rings. On the reference plane, the plurality of auxiliary rings sequentially surround the outer side of the floating area.

2. The junction terminal extension structure according to claim 1, characterized in that: The junction termination extension region further includes a third surface close to one side of the silicon carbide epitaxial drift layer, and the third surfaces of the plurality of junction termination extension regions are flush; The floating region and the auxiliary ring include doping elements, and the floating region and the auxiliary ring respectively form PN junctions with the silicon carbide epitaxial drift layer; in the multiple junction terminal extension regions, the concentration depth distribution and junction depth of the doping elements in the floating region and the auxiliary ring are the same, and are both smaller than the concentration depth distribution and junction depth of the doping elements in the main junction.

3. The junction terminal extension structure according to claim 1, characterized in that: In at least two of the junction terminal extension regions, the widths of the floating regions are the same; From the inside to the outside, the junction terminal extension area includes the floating area, the first auxiliary ring to the nth auxiliary ring in sequence, and in at least two of the junction terminal extension areas, the width of the i-th auxiliary ring is the same, 1≤i≤n, n≥5, i and n are both natural numbers; In at least two of the junction terminal extension areas, the spacing between the jth auxiliary ring and the j+1th auxiliary ring is the same, 1≤j≤n-1, and j is a natural number.

4. The junction terminal extension structure according to claim 1, characterized in that: On the reference plane, the plurality of junction termination extension regions are arranged at equal intervals.

5. The junction terminal extension structure according to claim 1, characterized in that: The height difference between the second surfaces of any two adjacent junction termination extension regions is equal.

6. The junction terminal extension structure according to claim 1, characterized in that: In the junction terminal extension region, the width of the floating region is less than or equal to the sum of the widths and spacings of the plurality of auxiliary rings.

7. The junction terminal extension structure according to claim 1, characterized in that: The junction terminal extension region includes at least five of the auxiliary rings; From the inside to the outside, the width of the auxiliary rings in the same junction terminal extension region decreases successively, and the distance between two adjacent auxiliary rings increases successively.

8. The junction terminal extension structure according to claim 7, characterized in that: Along the direction from inside to outside, the junction terminal extension area includes the floating area, the first auxiliary ring to the nth auxiliary ring in sequence, n≥5, and n is a natural number; Let the distance between the i-th auxiliary ring and the i-1-th auxiliary ring be S i , the distance between the first auxiliary ring and the floating area is S1, and the increment of the distance between the auxiliary rings is S, then S i =S1+(i-1)×S; where 1<i≤n, and i is a natural number; Let the width of the i-th auxiliary ring be W i , the width of the first auxiliary ring is W1, and the increment of the width of the auxiliary ring is W, then W i =W1-(i-1)×W.

9. A method for preparing a junction terminal extension structure, characterized in that: include: forming a main junction on the silicon carbide epitaxial drift layer; Combining a photolithography process with an ion implantation process, forming N junction terminal extension regions on the silicon carbide epitaxial drift layer at the same time, wherein N≥3, and N is a natural number; the silicon carbide epitaxial drift layer comprises a first surface away from one side of the N junction terminal extension regions, and on a reference plane parallel to the first surface, the N junction terminal extension regions sequentially surround the outside of the main junction, and the junction terminal extension region comprises a second surface away from one side of the silicon carbide epitaxial drift layer; the junction terminal extension region comprises a floating region and a plurality of auxiliary rings, and on the reference plane, the plurality of auxiliary rings sequentially surround the outside of the floating region; Combined with N-1 times of photolithography, the second surfaces of the N junction terminal extension regions are etched N-1 times respectively, and along the direction from inside to outside, the heights of the second surfaces of the N junction terminal extension regions decrease successively compared with the first surface.

10. A power device, characterized in that: include: substrate; An active region, comprising a plurality of power device cell structures, wherein the plurality of power device cell structures are arranged on the substrate; The junction termination extension structure according to any one of claims 1 to 8 is arranged on the substrate and located outside the active area.

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