High electron mobility transistor chip and preparation method thereof

Abstract

The invention discloses a high electron mobility transistor chip and a preparation method thereof, and belongs to the technical field of semiconductor photoelectricity. The high electron mobility transistor chip comprises a source electrode, a drain electrode and an epitaxial layer; the epitaxial layer comprises a channel layer, a barrier layer and a cap layer which are stacked in sequence, the epitaxial layer further comprises a contact groove, a groove opening of the contact groove is located in the cap layer, the groove bottom of the contact groove extends to the channel layer, an N-type heavily-doped GaN layer is arranged in the contact groove, and the N-type heavily-doped GaN layer covers the inner wall of the contact groove; and the source electrode and the drain electrode are respectively located in the corresponding contact grooves and are electrically connected with the N-type heavily doped GaN layer. According to the embodiment of the invention, ohmic contact resistance can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor optoelectronic technology, and in particular to a high electron mobility transistor chip and a preparation method thereof. Background Art

[0002] HEMT (High Electron Mobility Transistor) is a heterojunction field effect transistor, which is widely used in aerospace, communication technology, automotive electronics and switching power supply, especially in high power and high frequency application fields. HEMT chip is the basis for the preparation of electronic power devices.

[0003] In the related art, a HEMT chip mainly includes a gate, a source, a drain and an epitaxial layer.

[0004] The low ohmic contact resistance between the epitaxial layer and the source and drain in a high electron mobility transistor chip plays a vital role in achieving excellent device electrical properties, such as high transconductance and high saturation current. Therefore, how to reduce the ohmic contact resistance of a high electron mobility transistor chip is a problem worth studying. Summary of the invention

[0005] The embodiment of the present disclosure provides a high electron mobility transistor chip and a method for manufacturing the same, which can reduce ohmic contact resistance. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a high electron mobility transistor chip, including a source, a drain, and an epitaxial layer;

[0007] The epitaxial layer includes a channel layer, a barrier layer and a cap layer stacked in sequence, the epitaxial layer also includes a contact groove, the groove opening of the contact groove is located in the cap layer, and the groove bottom of the contact groove extends to the channel layer, the contact groove has an N-type heavily doped GaN layer, and the N-type heavily doped GaN layer covers the inner wall of the contact groove;

[0008] The source electrode and the drain electrode are respectively located in the corresponding contact grooves and are electrically connected to the N-type heavily doped GaN layer.

[0009] In an implementation of the present disclosure, the N-type heavily doped GaN layer is flush with the cap layer, and the N-type heavily doped GaN layer does not protrude from the notch of the contact groove.

[0010] In one implementation of the present disclosure, the doping concentration of the N-type heavily doped GaN layer is greater than 1e18;

[0011] The thickness of the N-type heavily doped GaN layer is 2-80 nm.

[0012] In one implementation of the present disclosure, the channel layer is a GaN layer, and the thickness of the channel layer is 150 to 350 nm;

[0013] The barrier layer is an AlGaN layer, and the thickness of the barrier layer is 15 to 35 nm;

[0014] The cap layer is a GaN layer, and the thickness of the cap layer is 1-5 nm.

[0015] In an implementation of the present disclosure, the high electron mobility transistor chip further includes a buffer layer and a stress release layer stacked in sequence, wherein the buffer layer and the stress release layer are both located on a side of the epitaxial layer facing away from the source and the drain;

[0016] The buffer layer is a GaN layer, and the thickness of the buffer layer is 3 to 6 μm;

[0017] The stress release layer is a periodically stacked AlN / AlGaN superlattice structure, and the thickness of each layer of the AlN / AlGaN superlattice structure is 8-12 nm.

[0018] On the other hand, an embodiment of the present disclosure provides a method for preparing a high electron mobility transistor chip, the method for preparing the high electron mobility transistor chip as described in the above aspect, the method comprising:

[0019] preparing a channel layer, a barrier layer and a cap layer stacked in sequence to obtain an epitaxial layer;

[0020] Etching a contact groove on one side of the epitaxial layer, wherein the opening of the contact groove is located in the cap layer, and the bottom of the contact groove extends to the channel layer;

[0021] Preparing an N-type heavily doped GaN layer in the contact groove, so that the N-type heavily doped GaN layer covers the inner wall of the contact groove;

[0022] A source electrode is prepared in one contact groove, and a drain electrode is prepared in another contact groove, so that the source electrode and the drain electrode are both electrically connected to the N-type heavily doped GaN layer in the corresponding contact groove.

[0023] In one implementation of the present disclosure, etching a contact groove on one side of the epitaxial layer includes:

[0024] preparing a dielectric layer on a side of the cap layer facing away from the barrier layer;

[0025] patterning the dielectric layer;

[0026] Using the patterned dielectric layer as a mask, etching the epitaxial layer to obtain the contact groove;

[0027] The excess dielectric layer is removed.

[0028] In one implementation of the present disclosure, preparing an N-type heavily doped GaN layer in the contact groove includes:

[0029] Prepare the N-type heavily doped GaN layer on a side of the cap layer facing away from the barrier layer;

[0030] The N-type heavily doped GaN layer is etched so that the N-type heavily doped GaN layer in the contact groove covers the inner wall of the contact groove, and the N-type heavily doped GaN layer on a side of the cap layer facing away from the barrier layer is completely removed.

[0031] In one implementation of the present disclosure, the N-type heavily doped GaN layer is prepared on a side of the cap layer facing away from the barrier layer, including:

[0032] Growing the N-type heavily doped GaN layer;

[0033] The temperature in the chamber is set to 900-1200° C. and annealing is performed for 5-30 minutes.

[0034] In one implementation of the present disclosure, etching the N-type heavily doped GaN layer includes:

[0035] The etching gas system is set to a Cl-based gas, and the auxiliary gas is set to at least one of argon, nitrogen, and helium.

[0036] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0037] The contact groove is used to accommodate the source or drain, so as to achieve ohmic contact between the two and the epitaxial layer. Since there is an N-type heavily doped GaN layer in the contact groove, and the N-type heavily doped GaN layer covers the inner wall of the contact groove, the source or drain accommodated in the contact groove achieves ohmic contact through the N-type heavily doped GaN layer. Since the doping concentration of the N-type heavily doped GaN layer is relatively high, the energy band at the N-type heavily doped GaN layer is pulled down, which greatly increases the probability of electron tunneling at the contact surface between the source or drain and the epitaxial layer, thereby achieving the purpose of reducing the ohmic contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 is a schematic structural diagram of a high electron mobility transistor provided by an embodiment of the present disclosure;

[0040] Figure 2 is a flow chart of a method for preparing a high electron mobility transistor provided by an embodiment of the present disclosure;

[0041] Figure 3 It is a flow chart of another method for preparing a high electron mobility transistor provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0043] As a representative of the third generation of semiconductor materials, GaN is an important semiconductor material that emerged after Si and GaAs materials. It has attracted widespread attention due to its excellent properties such as large bandgap, high critical field strength, high carrier saturation velocity, and high temperature and radiation resistance. Among them, the excellent performance of GaN-based heterojunction high electron mobility transistors (HEMT) in the microwave and millimeter wave fields has led to extensive and in-depth research at home and abroad. After years of efforts, the performance and stability of GaN-based heterojunction high electron mobility transistors have been greatly improved, especially AlGaN / GaN high electron mobility transistors have become the focus and hotspot of research.

[0044] Low ohmic contact resistance plays a vital role in achieving excellent electrical properties of high electron mobility transistors, such as high transconductance and high saturation current. Due to the wide band gap of GaN, it is relatively difficult to achieve low resistance ohmic contact. Many experiments have shown that multilayer metal structures such as Ti / Al / Ti / Au, Ti / Al / Pt / Au, TI / Al / Ti, etc. can achieve low resistance ohmic contact on n or i-AlGaN. It is generally believed that in the process of Ti / Al / Ti / Au forming ohmic contact with AlGaN, under high temperature alloy conditions, metal and nitride will react, and metal Al and Ti will react with the AlGaN layer to generate titanium nitride (TiN) and aluminum titanium nitrogen (AlTi2N), thereby obtaining a low ohmic contact resistivity. At the same time, a titanium aluminum alloy with a TiAl3 metallographic phase is formed between Ti and Al, further reducing the ohmic contact resistivity. The N element in the AlGaN layer diffuses into the metal layer, generating a large number of N vacancies, thereby forming a heavily doped semiconductor, and the metal will diffuse into AlGaN. Under different alloy temperature and time conditions, the degree of reaction between the metal and the AlGaN layer is different, the doping concentration caused by N vacancies and the diffusion depth of the metal into the AlGaN layer are also different, thus affecting the contact resistance.

[0045] According to the literature and experimental research, alloy temperature plays a key role in the level of ohmic contact resistance. For example, on the one hand, when the alloy temperature is low, the reaction of Al, Ti and AlGaN layer is relatively insufficient, the concentration of N vacancies formed is not high, the depth of metal diffusion into the AlGaN layer is shallow, the alloy does not damage the AlGaN layer lattice to a small extent, and the thickness of the AlGaN layer with a complete lattice can still maintain the original 2DEG concentration. At this time, there is still a barrier between the metal and AlGaN, and the ohmic contact is not fully formed, and the contact resistance is large. On the other hand, with the increase of alloy temperature or the increase of alloy time, the diffusion depth of metal into the AlGaN layer increases, the reaction degree of Al, Ti and AlGaN deepens, and the doping concentration introduced by N vacancies increases, forming a relatively good ohmic contact. However, with the step-up increase of annealing temperature or the extension of annealing time, the deep diffusion of metal into the AlGaN layer destroys the lattice integrity of the AlGaN layer. When the alloy temperature exceeds a certain temperature (795°C in the experiment), the destruction of the AlGaN lattice structure will affect the piezoelectric polarization and spontaneous polarization effects, thereby affecting the 2DEG concentration under the source and drain regions, resulting in a decrease in current.

[0046] Therefore, how to reduce the ohmic contact resistance of high electron mobility transistors is a problem worth studying.

[0047] Figure 1 is a schematic diagram of the structure of a high electron mobility transistor chip provided by an embodiment of the present disclosure, such as Figure 1 As shown, the high electron mobility transistor chip includes a source 1 , a drain 2 and an epitaxial layer 3 .

[0048] The epitaxial layer 3 includes a channel layer 31, a barrier layer 32 and a cap layer 33 stacked in sequence, and the epitaxial layer 3 also includes a contact groove 34, the groove opening of the contact groove 34 is located in the cap layer 33, and the groove bottom of the contact groove 34 extends to the channel layer 31, and the contact groove 34 has an N-type heavily doped GaN layer 35, and the N-type heavily doped GaN layer 35 covers the inner wall of the contact groove 34. The source 1 and the drain 2 are respectively located in the corresponding contact groove 34 and are electrically connected to the N-type heavily doped GaN layer 35.

[0049] The contact groove 34 is used to accommodate the source 1 or the drain 2, so as to achieve ohmic contact between the source 1 or the drain 2 and the epitaxial layer 3. Since the contact groove 34 has an N-type heavily doped GaN layer 35, and the N-type heavily doped GaN layer 35 covers the inner wall of the contact groove 34, the source 1 or the drain 2 accommodated in the contact groove 34 achieves ohmic contact through the N-type heavily doped GaN layer 35. Since the doping concentration of the N-type heavily doped GaN layer 35 is relatively high, the energy band at the N-type heavily doped GaN layer 35 is pulled down, which greatly increases the probability of electron tunneling at the contact surface between the source 1 or the drain 2 and the epitaxial layer 3, thereby achieving the purpose of reducing the ohmic contact resistance.

[0050] Continue to participate Figure 1 In this embodiment, the N-type heavily doped GaN layer 35 is flush with the cap layer 33 , and the N-type heavily doped GaN layer 35 does not protrude from the notch of the contact groove 34 .

[0051] In the above implementation, the N-type heavily doped GaN layer 35 is completely contained in the contact groove 34 to completely cover the inner wall of the contact groove 34. In addition, the N-type heavily doped GaN layer 35 cannot protrude from the notch of the contact groove 34, and especially cannot be located on the side of the cap layer 33 facing away from the barrier layer 32, so as to avoid the N-type heavily doped GaN layer 35 affecting the preparation of other thin film layers, thereby effectively improving reliability.

[0052] In this embodiment, the doping concentration of the N-type heavily doped GaN layer 35 is greater than 1e18, and the thickness of the N-type heavily doped GaN layer 35 is 2-80 nm.

[0053] In the above implementation, the doping concentration of the N-type heavily doped GaN layer 35 is designed to be relatively large, which can lower the energy band between the N-type heavily doped GaN layer 35 and the barrier layer 32, greatly increasing the probability of electron tunneling at the contact surface between the source 1 or the drain 2 and the epitaxial layer 3, thereby achieving the purpose of reducing the ohmic contact resistance. In addition, the N-type heavily doped GaN layer 35 is designed to have the above thickness, which can ensure its functionality on the one hand, and can also be conducive to improving the preparation efficiency on the other hand.

[0054] In this embodiment, the channel layer 31 is a GaN layer with a thickness of 150-350 nm. The barrier layer 32 is an AlGaN layer with a thickness of 15-35 nm. The cap layer 33 is a GaN layer with a thickness of 1-5 nm.

[0055] In the above implementation, an AlGaN / GaN heterojunction is formed between the channel layer 31 and the barrier layer 32. Due to the influence of surface traps, if the barrier layer 32 is thinner, the electric field strength of the barrier layer 32 is greater, the current collapse will be more serious, and the saturated output power will be lower. If the barrier layer 32 is thicker, the barrier layer 32 will increase the parasitic effect and reduce the small signal gain characteristics. Therefore, designing the barrier layer 32 to the above thickness can ensure better reliability. The cap layer 33 plays an important role in reducing the current collapse of the drain 2 and maintaining the 2DEG generated by the polarization characteristics. At the same time, the cap layer 33 can also reduce the leakage current of the gate 9. Therefore, designing the cap layer 33 to the above thickness can ensure its functionality on the one hand, and on the other hand, it can also be beneficial to improve the preparation efficiency.

[0056] Continue to see Figure 1In this embodiment, the high electron mobility transistor chip further includes a substrate 6 , which is located on a side of the epitaxial layer 3 facing away from the source 1 and the drain 2 .

[0057] In the above implementation, the substrate 6 provides a basis for the growth of the epitaxial layer 3 to ensure the reliability of the growth of the epitaxial layer 3 .

[0058] Exemplarily, the material of the substrate 6 is any one of Si, SiC, and GaN, which are easy to prepare and obtain.

[0059] Continue to see Figure 1 In this embodiment, the high electron mobility transistor chip further includes a buffer layer 4 and a stress release layer 5 stacked in sequence, and the buffer layer 4 and the stress release layer 5 are both located on the side of the epitaxial layer 3 facing away from the source 1 and the drain 2. The buffer layer 4 is a GaN layer, and the thickness of the buffer layer 4 is 3 to 6 μm. The stress release layer 5 is a periodically stacked AlN / AlGaN superlattice structure, and the thickness of each layer of the AlN / AlGaN superlattice structure is 8 to 12 nm.

[0060] In the above implementation, the buffer layer 4 and the stress release layer 5 are sequentially stacked between the substrate 6 and the epitaxial layer 3. The buffer layer 4 has high resistivity, which reduces the background carrier concentration to reduce the current collapse of the drain 2 caused by the trap effect of the buffer layer 4. The stress release layer 5 can release a certain amount of stress to improve the quality of the epitaxial layer 3 of the electron mobility transistor finally obtained.

[0061] Continue to see Figure 1 In this embodiment, the high electron mobility transistor chip further includes a first passivation layer 7 and a second passivation layer 8 stacked in sequence, wherein the first passivation layer 7 covers the region on the cap layer 33 except the source electrode 1 and the drain electrode 2. The second passivation layer 8 covers the region on the side of the first passivation layer 7 facing away from the epitaxial layer 3 except the gate electrode 9.

[0062] In the above implementation, on the one hand, it is beneficial to the insulation between the source 1, the drain 2, and the gate 9, and on the other hand, it can prevent the adverse effects of water vapor and oxygen on the high electron mobility transistor chip.

[0063] Exemplarily, the material of the first passivation layer 7 and the second passivation layer 8 can be one of silicon dioxide, hafnium dioxide, aluminum oxide, silicon nitride and lanthanum oxide, which can ensure good insulation effect.

[0064] Figure 2 A method for preparing a high electron mobility transistor chip provided in an embodiment of the present disclosure is provided. Figure 2 , the preparation method comprises:

[0065] Step 201 : preparing a channel layer 31 , a barrier layer 32 and a cap layer 33 stacked in sequence to obtain an epitaxial layer 3 .

[0066] Step 202 : etching a contact groove 34 on one side of the epitaxial layer 3 , wherein the opening of the contact groove 34 is located in the cap layer 33 , and the bottom of the contact groove 34 extends to the channel layer 31 .

[0067] Step 203 : preparing an N-type heavily doped GaN layer 35 in the contact groove 34 , so that the N-type heavily doped GaN layer 35 covers the inner wall of the contact groove 34 .

[0068] Step 204 : preparing a source electrode 1 in one contact groove 34 , and preparing a drain electrode 2 in another contact groove 34 , so that the source electrode 1 and the drain electrode 2 are both electrically connected to the N-type heavily doped GaN layer 35 in the corresponding contact groove 34 .

[0069] The contact groove 34 is used to accommodate the source 1 or the drain 2, so as to achieve ohmic contact between the source 1 or the drain 2 and the epitaxial layer 3. Since the contact groove 34 has an N-type heavily doped GaN layer 35, and the N-type heavily doped GaN layer 35 covers the inner wall of the contact groove 34, the source 1 or the drain 2 accommodated in the contact groove 34 achieves ohmic contact through the N-type heavily doped GaN layer 35. Since the doping concentration of the N-type heavily doped GaN layer 35 is relatively high, the energy band at the N-type heavily doped GaN layer 35 is pulled down, which greatly increases the probability of electron tunneling at the contact surface between the source 1 or the drain 2 and the epitaxial layer 3, thereby achieving the purpose of reducing the ohmic contact resistance.

[0070] Figure 3 Another method for preparing a high electron mobility transistor chip provided in the embodiment of the present disclosure is as follows: Figure 3 , the preparation method comprises:

[0071] Step 301: Provide a substrate 6.

[0072] Optionally, the material of the substrate 6 is sapphire, SiC, Si, GaN, etc. In this embodiment, the material of the substrate 6 is sapphire.

[0073] Step 302 : Prepare a buffer layer 4 on one side of the substrate 6 .

[0074] Exemplarily, the buffer layer 4 is grown by MOCVD (Metal Organic Chemical Vapor Deposition) equipment, the buffer layer 4 is a GaN layer, and the thickness of the buffer layer 4 is 3-6 μm.

[0075] Step 303 : preparing a stress release layer 5 on one side of the buffer layer 4 .

[0076] Exemplarily, the stress release layer 5 is a periodically stacked AlN / AlGaN superlattice structure, and the thickness of each layer of the AlN / AlGaN superlattice structure is 8-12 nm.

[0077] Step 303 : preparing a channel layer 31 , a barrier layer 32 and a cap layer 33 stacked in sequence on one side of the buffer layer 4 to obtain an epitaxial layer 3 .

[0078] Exemplarily, the channel layer 31, the barrier layer 32 and the cap layer 33 are all grown by MOCVD equipment, the channel layer 31 is a GaN layer, the thickness of the channel layer 31 is 150-350nm, the barrier layer 32 is an AlGaN layer, the thickness of the barrier layer 32 is 15-35nm, and the cap layer 33 is a GaN layer, the thickness of the cap layer 33 is 1-5nm.

[0079] Step 304 : etching a contact groove 34 on one side of the epitaxial layer 3 . The opening of the contact groove 34 is located in the cap layer 33 , and the bottom of the contact groove 34 extends to the channel layer 31 .

[0080] In this embodiment, step 304 includes the following steps:

[0081] Step 3041 : preparing a dielectric layer on the side of the cap layer 33 facing away from the barrier layer 32 .

[0082] Exemplarily, the dielectric layer is prepared by LPCVD (Low Pressure Chemical Vapor Deposition) equipment, the dielectric layer is a SiN layer, and the thickness of the dielectric layer is 20-100 nm.

[0083] In other embodiments, the dielectric layer may also be prepared by ALD (Atomic Layer Deposition) equipment, or by MOCVD equipment. The dielectric layer may also be a SiO2 layer.

[0084] Step 3042: Patterning the dielectric layer.

[0085] Exemplarily, through a photolithography process, two contact grooves 34 (one contact groove 34 is a source 1 contact groove 34 for accommodating the source 1, and the other contact groove 34 is a drain 2 contact groove 34 for accommodating the drain 2) are located, and dry etching technology is used to etch the dielectric layer to form grooves, thereby patterning the dielectric layer.

[0086] Step 3043 : using the patterned dielectric layer as a mask, etching the epitaxial layer 3 to obtain a contact groove 34 .

[0087] Exemplarily, during the etching process, the cap layer 33, the barrier layer 32 and the channel layer 31 are etched in sequence. The cap layer 33 (1-5 nm) and the barrier layer 32 (15-35 nm) need to be etched through, the barrier layer 32 is etched at an angle of 45-80°, and the channel layer 31 is continuously etched by no more than 10 nm, so that the total etching depth of the barrier layer 32 and the channel layer 31 is 16-50 nm.

[0088] Step 3044: remove the excess dielectric layer.

[0089] Exemplarily, the excess dielectric layer is etched using hot phosphoric acid until all the excess dielectric layer is removed.

[0090] Step 305 : preparing an N-type heavily doped GaN layer 35 in the contact groove 34 , so that the N-type heavily doped GaN layer 35 covers the inner wall of the contact groove 34 .

[0091] In this embodiment, step 305 includes the following steps:

[0092] Step 3051 : preparing an N-type heavily doped GaN layer 35 on the side of the cap layer 33 facing away from the barrier layer 32 .

[0093] Exemplarily, the N-type heavily doped GaN layer 35 is prepared by any one of MOCVD equipment, ALD equipment, and MBE (Molecular Beam Epitaxy) equipment. When growing N-type heavily doped GaN, the N-type doping concentration must be greater than 1e18, the thickness is 2 to 80nm, and the N-type doping atoms include but are not limited to elements such as N and P. After growing the N-type heavily doped GaN layer 35, the cavity temperature is set to 900 to 1200°C, and annealing is performed for 5 to 30 minutes. The annealing atmosphere is N2 or vacuum annealing. Through the annealing operation, the element activation of the N-type heavily doped GaN layer 35 can be achieved.

[0094] In other embodiments, RTA (Rapid Thermal Annealing) annealing may also be used to activate the doping elements of the N-type heavily doped GaN layer 35 .

[0095] Step 3052: Etch the N-type heavily doped GaN layer 35 so that the N-type heavily doped GaN layer 35 in the contact groove 34 covers the inner wall of the contact groove 34, and the N-type heavily doped GaN layer 35 on the side of the cap layer 33 facing away from the barrier layer 32 is completely removed.

[0096] Exemplarily, the N-type heavily doped GaN layer 35 is etched by an ICP (Inductively Coupled Plasma Etching Systems) device, the etching gas system is set to a Cl-based gas, and the auxiliary gas is set to at least one of argon, nitrogen, and helium, which can increase the vertical (anisotropic) etching capability.

[0097] Exemplarily, the Cl-based gas includes CL2 / BCL3 and the like.

[0098] Step 306 : preparing a source electrode 1 in one contact groove 34 , and preparing a drain electrode 2 in another contact groove 34 , so that the source electrode 1 and the drain electrode 2 are both electrically connected to the N-type heavily doped GaN layer 35 in the corresponding contact groove 34 .

[0099] Exemplarily, the evaporated metal used is a Ti / Al / X system metal, wherein the thickness of Ti is 10-100 nm, the thickness of Al is 100-500 nm, and the X metal can be a metal such as Ti / TiN / Pt / Ni / W.

[0100] Step 307: perform annealing treatment.

[0101] Exemplarily, the annealing furnace is in a pure nitrogen atmosphere or a vacuum atmosphere, the annealing temperature is 420 to 600° C., and the annealing time is 30 to 150 seconds.

[0102] Step 308: Conduct electrical performance test.

[0103] Exemplarily, the CTLM (Current-Voltage Titration Method) measurement method is used for linear fitting to determine the size of the ohmic contact.

[0104] After actual experiments, the ohmic resistance of the high electron mobility transistor chip provided in the related art was tested to be 0.5Ω·mm, and the ohmic resistance of the high electron mobility transistor chip provided in the embodiment of the present disclosure was tested to be 0.2Ω·mm. It can be seen that the ohmic resistance of the high electron mobility transistor chip provided in the embodiment of the present disclosure has been effectively reduced.

[0105] Step 309: Prepare the first passivation layer 7 and the second passivation layer 8 in sequence.

[0106] Exemplarily, the first passivation layer 7 is prepared by MOCVD equipment. The first passivation layer 7 is a SiN layer with a thickness of 35-60 nm. The first passivation layer 7 serves as a gate dielectric layer and can also repair lattice damage caused when etching the epitaxial layer 3.

[0107] Exemplarily, before preparing the first passivation layer 7 , SPM cleaning may be performed, and the surface of the epitaxial layer 3 may be repaired by potassium hydroxide.

[0108] Exemplarily, the second passivation layer 8 is prepared by one of MOCVD equipment, LPCVD equipment, and ALD. The second passivation layer 8 is a SiN layer with a thickness of 60-100 nm.

[0109] Step 310: Prepare the gate 9.

[0110] Exemplarily, the gate 9 is prepared by photolithography, etching, and metal evaporation processes, with the etching depth being 60-100 nm.

[0111] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0112] The above does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A high electron mobility transistor chip, characterized in that: It comprises a source electrode (1), a drain electrode (2) and an epitaxial layer (3); The epitaxial layer (3) comprises a channel layer (31), a barrier layer (32) and a cap layer (33) which are stacked in sequence, the epitaxial layer (3) further comprises a contact groove (34), the groove opening of the contact groove (34) is located in the cap layer (33), and the groove bottom of the contact groove (34) extends to the channel layer (31), the contact groove (34) has an N-type heavily doped GaN layer (35), and the N-type heavily doped GaN layer (35) covers the inner wall of the contact groove (34); The source electrode (1) and the drain electrode (2) are respectively located in the corresponding contact groove (34) and are electrically connected to the N-type heavily doped GaN layer (35).

2. The high electron mobility transistor chip according to claim 1, characterized in that: The N-type heavily doped GaN layer (35) is flush with the cap layer (33), and the N-type heavily doped GaN layer (35) does not protrude from the notch of the contact groove (34).

3. The high electron mobility transistor chip according to claim 1, characterized in that: The doping concentration of the N-type heavily doped GaN layer (35) is greater than 1e18; The thickness of the N-type heavily doped GaN layer (35) is 2-80 nm.

4. The high electron mobility transistor chip according to claim 1, characterized in that: The channel layer (31) is a GaN layer, and the thickness of the channel layer (31) is 150-350 nm; The barrier layer (32) is an AlGaN layer, and the thickness of the barrier layer (32) is 15 to 35 nm; The cap layer (33) is a GaN layer, and the thickness of the cap layer (33) is 1 to 5 nm.

5. The high electron mobility transistor chip according to claim 1, characterized in that: It also includes a buffer layer (4) and a stress release layer (5) stacked in sequence, wherein the buffer layer (4) and the stress release layer (5) are both located on a side of the epitaxial layer (3) facing away from the source electrode (1) and the drain electrode (2); The buffer layer (4) is a GaN layer, and the thickness of the buffer layer (4) is 3 to 6 μm; The stress release layer (5) is a periodically stacked AlN / AlGaN superlattice structure, and the thickness of each layer of the AlN / AlGaN superlattice structure is 8-12 nm.

6. A method for preparing a high electron mobility transistor chip, characterized in that: The preparation method is used to prepare the high electron mobility transistor chip according to claim 1, and the preparation method comprises: Separately preparing a channel layer (31), a barrier layer (32) and a cap layer (33) stacked in sequence to obtain an epitaxial layer (3); A contact groove (34) is obtained by etching on one side of the epitaxial layer (3), wherein the groove opening of the contact groove (34) is located in the cap layer (33), and the groove bottom of the contact groove (34) extends to the channel layer (31); Preparing an N-type heavily doped GaN layer (35) in the contact groove (34), so that the N-type heavily doped GaN layer (35) covers the inner wall of the contact groove (34); A source electrode (1) is prepared in one contact groove (34), and a drain electrode (2) is prepared in another contact groove (34), so that the source electrode (1) and the drain electrode (2) are both electrically connected to the N-type heavily doped GaN layer (35) in the corresponding contact groove (34).

7. The preparation method according to claim 6, characterized in that: A contact groove (34) is obtained by etching one side of the epitaxial layer (3), comprising: Preparing a dielectric layer on the side of the cap layer (33) facing away from the barrier layer (32); patterning the dielectric layer; Using the patterned dielectric layer as a mask, etching the epitaxial layer (3) to obtain the contact groove (34); The excess dielectric layer is removed.

8. The preparation method according to claim 6, characterized in that: Preparing an N-type heavily doped GaN layer (35) in the contact groove (34), comprising: Preparing the N-type heavily doped GaN layer (35) on a side of the cap layer (33) facing away from the barrier layer (32); The N-type heavily doped GaN layer (35) is etched so that the N-type heavily doped GaN layer (35) located in the contact groove (34) covers the inner wall of the contact groove (34), while the N-type heavily doped GaN layer (35) on the side of the cap layer (33) facing away from the barrier layer (32) is completely removed.

9. The preparation method according to claim 8, characterized in that: The N-type heavily doped GaN layer (35) is prepared on a side of the cap layer (33) facing away from the barrier layer (32), comprising: Growing the N-type heavily doped GaN layer (35); The temperature in the chamber is set to 900-1200° C. and annealing is performed for 5-30 minutes.

10. The preparation method according to claim 8, characterized in that: Etching the N-type heavily doped GaN layer (35), comprising: The etching gas system is set to a Cl-based gas, and the auxiliary gas is set to at least one of argon, nitrogen, and helium.

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