LED epitaxial wafer, preparation method thereof and LED chip
By thinning the InGaN layer thickness and optimizing the multi-quantum well layer structure, the luminous efficiency and brightness of the LED chip are improved, and the problem of low brightness of the LED epitaxial sheet in the prior art is solved.
Patent Information
- Application Number
- CN202411330526.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2024-12-27
AI Technical Summary
The brightness of existing LED epitaxial films is not high, which affects its competitiveness in application fields.
By thinning the thickness of an InGaN layer close to the N-type semiconductor layer in the LED epitaxial sheet, reducing defects and V-pits generation, improving the growth and radiation recombination probability of multi-quantum well layers, thereby improving the luminous efficiency. The specific method includes growing an N-type semiconductor layer, a stress relief layer and a light emitting layer on a semi-finished epitaxial sheet, wherein the light emitting layer includes first and second multi-quantum well layers of periodic overlapping structures, and the quantum well layer thickness of the first multi-quantum well layer. Less than the thickness of the second multi-quantum well layer.
The luminous efficiency and brightness of the LED chip are effectively improved, and the problem of low brightness of the LED epitaxial sheet in the prior art is solved.
Smart Images
Figure CN119208474A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor devices, and in particular to an LED epitaxial wafer and its preparation, and an LED chip. Background Art
[0002] LED chip is a semiconductor electronic component that can emit light. It has the characteristics of small size, high brightness and low energy consumption. It is widely used in lighting and other fields. LED chip is obtained by splitting LED epitaxial wafer. LED epitaxial wafer is a solid light source, which is a light-emitting device made of semiconductor PN junction. When the forward current is turned on, the minority carriers (i.e. electrons) and majority carriers (i.e. holes) in the semiconductor recombine, and the released energy is emitted in the form of photons or part of it in the form of photons. LED epitaxial wafer lighting has significant advantages such as high efficiency, energy saving, environmental protection and long service life. It has been widely used in various aspects such as street lamps, display screens, indoor lighting and car lights. Considering that the luminous brightness is the most important measure of the competitiveness of LED epitaxial wafers, how to improve the brightness of LED epitaxial wafers on the basis of existing technology is an eternal topic to increase the competitiveness of LED epitaxial wafers.
[0003] At present, sapphire, silicon or silicon carbide are commonly used as substrates. With the continuous increase in application fields, the requirements for the brightness of LED chips are getting higher and higher. How to improve the brightness of the chip has become the most important technical difficulty at present. The improvement of chip brightness mainly depends on epitaxy, so the optimization of epitaxial structure is also the most important technical means at present. Summary of the invention
[0004] Based on this, the purpose of the present invention is to provide an LED epitaxial wafer and a preparation method thereof, and an LED chip, so as to solve the problem of low brightness of LED epitaxial wafers in the prior art.
[0005] The present invention provides an LED epitaxial wafer, comprising an N-type semiconductor layer, a stress release layer and a light-emitting layer, wherein the light-emitting layer comprises a first multi-quantum well layer and a second multi-quantum well layer which are arranged in sequence, wherein the first multi-quantum well layer and the second multi-quantum well layer are both periodically overlapped structures, and both comprise a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer, and the thickness of the quantum well layer in the first multi-quantum well layer is less than the thickness of the quantum well layer in the second multi-quantum well layer.
[0006] The present invention reduces the generation of defects and the amplification of V-pits by appropriately thinning the thickness of the InGaN layer near the N side, thereby improving the growth of the subsequent multi-quantum well layer, increasing the probability of radiation recombination, and ultimately improving the luminous efficiency. Specifically, the luminous principle of the LED chip is that electrical energy is converted into light energy. When the power is on, electrons and holes meet in the multi-quantum well layer to undergo radiation recombination and emit light. Usually, electrons and holes are basically recombined in 2-5 groups of quantum well layers near the P-type semiconductor layer, while the holes in the quantum well layer near the N-type semiconductor layer cannot reach it, so they do not participate in the luminescence, and mainly play a role of stress release. Since the temperature is relatively low when the InGaN layer is grown, and the crystal quality of the layer is poor due to the doping of In, defects and V-pits will be generated and amplified at this place, thereby affecting the growth of the subsequent multi-quantum well layer; and the defects generated will also reduce the probability of radiation recombination and affect the luminous efficiency. Therefore, by specifically reducing the thickness of the InGaN layer close to the N-type semiconductor layer, the defects generated there are effectively reduced, and the amplification of V-pits is reduced, thereby improving the growth of the subsequent multi-quantum well layer, and finally achieving the effect of improving the luminous efficiency. Therefore, the present invention solves the problem of low brightness of LED epitaxial wafers in the prior art.
[0007] Preferably, the period number of the first multi-quantum well layer is 1-5, and the sum of the period numbers of the first multi-quantum well layer and the second multi-quantum well layer is 6-14.
[0008] Preferably, the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 82%-97%.
[0009] Preferably, in a single period, the thickness of the quantum well layer in the second multi-quantum well layer is 2nm-4nm, and the thickness of the quantum barrier layer is 8nm-12nm.
[0010] Preferably, the LED epitaxial wafer also includes a substrate, and an ALN layer, a buffer layer, a three-dimensional GaN layer, an undoped GaN layer, the N-type semiconductor layer, the stress release layer and the light-emitting layer, an electron blocking layer and a P-type semiconductor layer stacked sequentially on the substrate.
[0011] The present invention also provides a method for preparing an LED epitaxial wafer, the method comprising:
[0012] Provide semi-finished epitaxial wafers;
[0013] sequentially growing an N-type semiconductor layer, a stress release layer and a light-emitting layer on the semi-finished epitaxial wafer;
[0014] Among them, the light-emitting layer includes a first multi-quantum well layer and a second multi-quantum well layer arranged in sequence, the first multi-quantum well layer and the second multi-quantum well layer are both periodically overlapping structures, and both include quantum well layers and quantum barrier layers, the quantum well layer is an InGaN layer, the quantum barrier layer is a GaN layer, and the thickness of the quantum well layer in the first multi-quantum well layer is less than the thickness of the quantum well layer in the second multi-quantum well layer.
[0015] Preferably, the step of sequentially growing an N-type semiconductor layer, a stress release layer and a light-emitting layer on the semi-finished epitaxial wafer comprises:
[0016] placing the semi-finished epitaxial wafer in an MOCVD device, and sequentially growing the N-type semiconductor layer, the stress release layer and the light-emitting layer on the semi-finished epitaxial wafer,
[0017] When the InGaN layer in the light-emitting layer is grown, the growth temperature is 700°C-850°C, the In component is 10%-30%, the MO source is TEGa and TMIn, and the gas introduced is N 2 and NH 3 , NH 3 As the reaction gas, N 2 As carrier gas, the growth pressure is 100 torr-300 torr, and the thickness of the InGaN layer in the first multi-quantum well layer is less than the thickness of the InGaN layer in the second multi-quantum well layer.
[0018] Preferably, the thickness of the quantum well layer in the second multi-quantum well layer is 2nm-4nm, and the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 82%-97%.
[0019] Preferably, the period number of the first multi-quantum well layer is 1-5, and the sum of the period numbers of the first multi-quantum well layer and the second multi-quantum well layer is 6-14.
[0020] The present invention also provides an LED chip comprising the LED epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 Schematic diagram of the structure of the light-emitting layer in the LED epitaxial wafer in one embodiment of the present invention;
[0022] Figure 2 Schematic diagram of the structure of an LED epitaxial wafer in one embodiment of the present invention;
[0023] Figure 3 is a flow chart of a method for preparing an LED epitaxial wafer in one embodiment of the present invention;
[0024] Description of main component symbols:
[0025] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION
[0026] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.
[0027] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0029] like Figures 1 to 2 As shown, the present invention discloses a partial structural schematic diagram of an LED epitaxial wafer, which includes a substrate 10 and an ALN layer 20, a buffer layer 30, a three-dimensional GaN layer 40, an undoped GaN layer 50, an N-type semiconductor layer 60, a stress release layer 70, a light-emitting layer 80, an electron blocking layer 90 and a P-type semiconductor layer 100 arranged in sequence on the substrate.
[0030] In the present embodiment, the substrate 10 may be a sapphire substrate, a silicon substrate or a silicon carbide substrate, etc. Specifically, the thickness of the ALN layer 20 is 10 nm-30 nm, and illustratively, the thickness of the ALN layer 20 is 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, but not limited thereto; the thickness of the buffer layer 30 is 15 nm-35 nm, and illustratively, the thickness of the buffer layer 30 is 15 nm, 20 nm, 25 nm, 30 nm or 35 nm, but not limited thereto; the thickness of the three-dimensional GaN layer 40 is 500 nm-2000 nm, and illustratively, the thickness of the three-dimensional GaN layer 40 is 500 nm, 900 nm, 1300 nm, 1800 nm or 2000 nm, but not limited thereto; the thickness of the undoped GaN layer 50 is 800 nm-1200 nm, and illustratively, the thickness of the three-dimensional GaN layer 40 is 800 nm-1200 nm, and illustratively, the thickness of the three-dimensional GaN layer 40 is 1500 nm, 2000 nm, 2500 nm, 3000 nm or 3500 nm, but not limited thereto; The thickness of the undoped GaN layer 50 is 800nm, 900nm, 1000nm, 1100nm or 1200nm, but not limited to this. The thickness of the n-type doped GaN layer 60 is 1000nm-3000nm. Exemplarily, the thickness of the n-type doped GaN layer 60 is 1000nm, 1500nm, 2000nm, 2500nm or 3000nm, but not limited to this. The stress release layer 70 can be a periodic structure in which InGaN layers and GaN layers grow alternately. The electron blocking layer 90 can be a periodic structure in which AlGaN layers and GaN layers grow alternately. The thickness of the electron blocking layer 90 is 10nm-60nm. Exemplarily, the thickness of the electron blocking layer 90 is 10nm, 25nm, 40nm, 50nm or 60nm, but not limited to this. The thickness of the P-type doped GaN layer 100 is 5 nm-100 nm. Exemplarily, the thickness of the P-type doped GaN layer 100 is 5 nm, 30 nm, 60 nm, 90 nm or 100 nm, but is not limited thereto.
[0031] In this embodiment, the light-emitting layer 80 includes a first multi-quantum well layer 81 and a second multi-quantum well layer 82 arranged in sequence. The first multi-quantum well layer 81 and the second multi-quantum well layer 82 are both periodically overlapped structures, and both include a quantum well layer 83 and a quantum barrier layer 84. The quantum well layer 83 is an InGaN layer, and the quantum barrier layer 84 is a GaN layer. The thickness of the quantum well layer 83 in the first multi-quantum well layer 81 is less than the thickness of the quantum well layer 83 in the second multi-quantum well layer 82. It can be understood that the light-emitting principle of the LED chip is that electrical energy is converted into light energy. When the power is turned on, electrons and holes meet in the multi-quantum well layer to undergo radiation recombination and emit light. Usually, electrons and holes are basically recombined in 2-5 groups of quantum well layers 83 close to the P-type semiconductor layer 100 side, while the holes cannot reach the quantum well layer 83 close to the N-type semiconductor layer 60 side, so they do not participate in the light emission, and mainly play a role of stress release. Since the temperature is relatively low when the InGaN layer is grown, and the In doping causes the crystal quality of the layer to be poor, defects and V-pits will be generated and amplified at this location, thereby affecting the growth of the subsequent multi-quantum well layer; and the defects generated will also reduce the probability of radiation recombination and affect the luminous efficiency. Therefore, by specifically reducing the thickness of the InGaN layer close to the side of the N-type semiconductor layer 60, the generation of defects here is effectively reduced, and the amplification of V-pits is reduced, thereby improving the growth of the subsequent multi-quantum well layer, and ultimately achieving the effect of improving the luminous efficiency. Therefore, the problem of low brightness of LED epitaxial wafers in the prior art is solved.
[0032] In addition, the thickness reduction also has a range. If it is too small, the change is not obvious and the luminous efficiency cannot be reflected; if it is too large, the original stress release function of the layer is weakened and it has a counter-effect. The same is true for the number of cycles. In this embodiment, within a single period, the thickness of the quantum well layer 83 in the second multi-quantum well layer 82 is 2nm-4nm, and illustratively, the thickness of the quantum well layer 83 is 2nm, 2.5nm, 3nm, 3.5nm, 3.8nm or 4nm, etc., but not limited thereto; the thickness of the quantum barrier layer 84 in the second multi-quantum well layer 82 is 8nm-12nm, and illustratively, the thickness of the quantum barrier layer 84 is 8nm, 9nm, 10nm, 10.5nm, 11nm or 12nm, etc., but not limited thereto; the ratio of the thickness of the quantum well layer 83 in the first multi-quantum well layer 81 to the thickness of the quantum well layer 83 in the second multi-quantum well layer 82 is 82%-97%, and illustratively, the ratio of the thickness of the quantum well layer 83 in the first multi-quantum well layer 81 to the thickness of the quantum well layer 83 in the second multi-quantum well layer 82 is 82%, 87%, 90%, 91%, 93% and 97%, etc., but not limited thereto. The period number of the first multi-quantum well layer 81 is 1-5. Exemplarily, the period number of the first multi-quantum well layer 81 is 1, 3, 5, etc., but not limited thereto; the sum of the period numbers of the first multi-quantum well layer 81 and the second multi-quantum well layer 82 is 6-14. Exemplarily, the sum of the period numbers of the first multi-quantum well layer 81 and the second multi-quantum well layer 82 is 6, 8, 10, 12, 13 and 14, but not limited thereto.
[0033] Accordingly, refer to Figure 3 The present invention also discloses a method for preparing an LED epitaxial wafer, which is used to prepare the above-mentioned LED epitaxial wafer, wherein the preparation method comprises the following steps:
[0034] S100: providing a substrate;
[0035] Preferably, the substrate may be a sapphire substrate.
[0036] S200 sequentially grows an AlN layer, a buffer layer, a three-dimensional GaN layer, an undoped GaN layer, the N-type semiconductor layer, the stress release layer and the light-emitting layer, an electron blocking layer and a P-type semiconductor layer on the substrate along an epitaxial growth direction.
[0037] Specifically, S200 includes:
[0038] S201: placing the substrate in a PVD device to grow an ALN layer;
[0039] Specifically, the thickness of the AlN layer is 10 nm to 30 nm.
[0040] S202: growing a buffer layer on the ALN layer;
[0041] Specifically, after the buffer layer is grown, the epitaxial wafer is transferred to a MOCVD device to grow a buffer layer on the ALN layer, and the thickness of the buffer layer is 15 nm-35 nm.
[0042] S203: growing a three-dimensional GaN layer on the buffer layer;
[0043] Specifically, in an MOCVD device, a three-dimensional GaN layer is grown on the buffer layer, and the thickness of the three-dimensional GaN layer is 500nm-2000nm.
[0044] S204: growing a non-doped GaN layer on the three-dimensional GaN layer;
[0045] Specifically, in an MOCVD device, a non-doped GaN layer is grown on the three-dimensional GaN layer, and the thickness of the non-doped GaN layer is 800nm-1200nm.
[0046] S205: growing an N-type semiconductor layer on the non-doped GaN layer;
[0047] Specifically, an N-type semiconductor layer is grown on a non-doped GaN layer in an MOCVD device, the thickness of the N-type semiconductor layer is 1000nm-3000nm, and the N-type semiconductor layer is an N-type doped GaN layer.
[0048] S206: growing a stress release layer on the N-type semiconductor layer;
[0049] Specifically, a stress release layer is grown on the N-type semiconductor layer in an MOCVD device, and the stress release layer is a periodic structure in which InGaN layers and GaN layers are grown alternately.
[0050] S207: growing a light-emitting layer on the stress release layer;
[0051] Specifically, a light-emitting layer is grown on a stress release layer in an MOCVD device, and the light-emitting layer includes a first multi-quantum well layer and a second multi-quantum well layer arranged in sequence. The first multi-quantum well layer and the second multi-quantum well layer are both periodically overlapped structures, and both include a quantum well layer and a quantum barrier layer. The quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer. The thickness of the quantum well layer in the first multi-quantum well layer is less than the thickness of the quantum well layer in the second multi-quantum well layer. The thickness of the quantum well layer in the second multi-quantum well layer is 2nm-4nm, the thickness of the quantum barrier layer is 8nm-12nm, and the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 82%-97%. The period number of the first multi-quantum well layer is 1-5, and the sum of the period numbers of the first multi-quantum well layer and the second multi-quantum well layer is 6-14. In addition, when growing the InGaN layer in the light-emitting layer, the growth temperature is 700℃-850℃, the In component is 10%-30%, the MO source is TEGa and TMIn, and the gas introduced is N2 and NH 3 , NH 3 As the reaction gas, N 2 As a carrier gas, the growth pressure is 100torr-300torr.
[0052] S208: growing an electron blocking layer on the light-emitting layer;
[0053] Specifically, an electron blocking layer is grown on the light-emitting layer in an MOCVD device. The electron blocking layer is a periodic structure in which AlGaN layers and GaN layers are grown alternately, and has a thickness of 10 nm to 60 nm.
[0054] S209: growing a P-type semiconductor layer on the electron blocking layer;
[0055] Specifically, a P-type semiconductor layer is grown on the electron blocking layer in an MOCVD device, and the P-type semiconductor layer is a P-type doped GaN layer with a thickness of 5nm-100nm.
[0056] The present invention is further described below with specific embodiments:
[0057] Embodiment 1
[0058] The present embodiment provides an LED epitaxial wafer, which also includes a substrate and an AlN layer, a buffer layer, a three-dimensional GaN layer, an undoped GaN layer, an N-type semiconductor layer, a stress release layer, a light-emitting layer, an electron blocking layer and a P-type semiconductor layer sequentially arranged on the substrate.
[0059] In this embodiment, the substrate is a GaAs substrate, the thickness of the ALN layer is 20 nm, the thickness of the buffer layer is 25 nm, the thickness of the three-dimensional GaN layer is 1200 nm, the thickness of the non-doped GaN layer is 1000 nm, the N-type semiconductor layer is an N-type doped GaN layer, the thickness of the N-type semiconductor layer is 2000 nm, the stress release layer is a periodic structure in which an InGaN layer and a GaN layer are alternately grown, and the light-emitting layer includes a first multi-quantum well layer and a second multi-quantum well layer arranged in sequence, and the first multi-quantum well layer and the second multi-quantum well layer are periodically alternately grown. The stacked structures include quantum well layers and quantum barrier layers, the period number of the first multi-quantum well layer is 3, the sum of the period numbers of the first multi-quantum well layer and the second multi-quantum well layer is 12, the thickness of the quantum well layer in the second multi-quantum well layer is 3nm, the thickness of the quantum barrier layer is 12nm, the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 90%, the electron blocking layer is a periodic structure of alternately grown AlGaN layers and GaN layers, with a thickness of 40nm, and the P-type semiconductor layer is a P-type doped GaN layer with a thickness of 60nm.
[0060] The method for preparing the LED epitaxial wafer in this embodiment comprises the following steps:
[0061] (1): Providing a substrate;
[0062] In this embodiment, the substrate is a GaAs substrate.
[0063] (2): growing an AlN layer, a buffer layer, a three-dimensional GaN layer, an undoped GaN layer, the N-type semiconductor layer, the stress release layer and the light-emitting layer, an electron blocking layer and a P-type semiconductor layer in sequence on the substrate along the epitaxial growth direction;
[0064] Specifically, step (2) includes:
[0065] S201: placing the substrate in a PVD device to grow an ALN layer;
[0066] Specifically, the thickness of the AlN layer is 20 nm.
[0067] growing a buffer layer on the ALN layer;
[0068] Specifically, after the buffer layer is grown, the epitaxial wafer is transferred to a MOCVD device to grow a buffer layer on the ALN layer. The thickness of the buffer layer is 25 nm.
[0069] Growing a three-dimensional GaN layer on the buffer layer;
[0070] Specifically, in an MOCVD device, a three-dimensional GaN layer is grown on the buffer layer, and the thickness of the three-dimensional GaN layer is 1200 nm.
[0071] Growing a non-doped GaN layer on the three-dimensional GaN layer;
[0072] Specifically, in an MOCVD device, a non-doped GaN layer is grown on the three-dimensional GaN layer, and the thickness of the non-doped GaN layer is 1000 nm.
[0073] growing an N-type semiconductor layer on the non-doped GaN layer;
[0074] Specifically, an N-type semiconductor layer is grown on the non-doped GaN layer in an MOCVD device, the thickness of the N-type semiconductor layer is 2000 nm, and the N-type semiconductor layer is an N-type doped GaN layer.
[0075] growing a stress relief layer on the N-type semiconductor layer;
[0076] Specifically, a stress release layer is grown on the N-type semiconductor layer in an MOCVD device, and the stress release layer is a periodic structure in which InGaN layers and GaN layers are grown alternately.
[0077] growing a light-emitting layer on the stress release layer;
[0078] Specifically, a light-emitting layer is grown on a stress release layer in an MOCVD device. The light-emitting layer includes a first multi-quantum well layer and a second multi-quantum well layer arranged in sequence. The first multi-quantum well layer and the second multi-quantum well layer are both periodically overlapped structures, and both include a quantum well layer and a quantum barrier layer. The quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer. The thickness of the quantum well layer in the first multi-quantum well layer is less than the thickness of the quantum well layer in the second multi-quantum well layer. The thickness of the quantum well layer in the second multi-quantum well layer is 3nm, the thickness of the quantum barrier layer is 12nm, and the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 90%. The number of periods of the first multi-quantum well layer is 3, and the sum of the number of periods of the first multi-quantum well layer and the second multi-quantum well layer is 12. In addition, when growing the InGaN layer in the light-emitting layer, the growth temperature is 750°C, the In component is 20%, the MO source is TEGa and TMIn, and the gas introduced is N 2 and NH 3 , NH 3 As the reaction gas, N 2 As a carrier gas, the growth pressure was 200 torr.
[0079] growing an electron blocking layer on the light-emitting layer;
[0080] Specifically, an electron blocking layer is grown on the light-emitting layer in an MOCVD device. The electron blocking layer is a periodic structure in which AlGaN layers and GaN layers are grown alternately, and has a thickness of 40 nm.
[0081] growing a P-type semiconductor layer on the electron blocking layer;
[0082] Specifically, a P-type semiconductor layer is grown on the electron blocking layer in an MOCVD device, and the P-type semiconductor layer is a P-type doped GaN layer with a thickness of 60 nm.
[0083] Embodiment 2
[0084] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 97%.
[0085] Embodiment 3
[0086] This embodiment also provides an LED epitaxial wafer, which differs from the first embodiment in that the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 95%.
[0087] Embodiment 4
[0088] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 92%.
[0089] Embodiment 5
[0090] This embodiment also provides an LED epitaxial wafer, which differs from the first embodiment in that the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 88%.
[0091] Embodiment 6
[0092] This embodiment also provides an LED epitaxial wafer, which differs from the first embodiment in that the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 85%.
[0093] Embodiment 7
[0094] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 82%.
[0095] Embodiment 8
[0096] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the number of periods of the first multi-quantum well layer is 1.
[0097] Embodiment 9
[0098] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the number of periods of the first multi-quantum well layer is 2.
[0099] Embodiment 10
[0100] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the number of periods of the first multi-quantum well layer is 4.
[0101] Embodiment 11
[0102] This embodiment also provides an LED epitaxial wafer, which is different from the first embodiment in that the number of periods of the first multi-quantum well layer is 5.
[0103] Comparative Example 1
[0104] This comparative example provides an LED epitaxial wafer and a preparation method thereof, which is different from the first embodiment in that the thickness of the quantum well layer in the first multi-quantum well layer is consistent with the thickness of the quantum well layer in the second multi-quantum well layer.
[0105] The LED epitaxial wafers obtained in Examples 1 to 11 and Comparative Example 1 were used to prepare LED chips with a size of 22 mil*35 mil. The test current was 60 mA and the tests were carried out under the same conditions. The specific results are shown in Table 1:
[0106] Table 1
[0107]
[0108] It can be seen from Table 1 that the LED epitaxial wafer obtained by the method in the embodiment of the present invention is used to prepare an LED chip with a size of 22mil*35mil. Under the same test conditions, the LED chip prepared by the method in Example 1 of the present invention has a luminous efficiency that is effectively improved by 2.2% compared to the LED chip prepared by the traditional method in Comparative Example 1. At the same time, the luminous brightness of the LED chips prepared by the methods in other embodiments of the present invention is also mostly greater than the luminous brightness of the LED chips prepared by the traditional method.
[0109] An embodiment of the present invention further provides an LED chip, comprising the above-mentioned LED epitaxial wafer.
[0110] In summary, the LED epitaxial wafer and its preparation method, and the LED chip in the embodiment of the present invention, by appropriately thinning the thickness of the InGaN layer close to the N side, firstly, reduce the generation of defects, and secondly, reduce the amplification of V-pits, improve the growth of the subsequent multi-quantum well layer, increase the probability of radiation recombination, and finally improve the luminous efficiency. Specifically, the luminous principle of the LED chip is that electrical energy is converted into light energy. When the power is turned on, the electrons and holes meet in the multi-quantum well layer to undergo radiation recombination and emit light. Usually, the electrons and holes are basically recombined in 2-5 groups of quantum well layers close to the P-type semiconductor layer, while the holes in the quantum well layer close to the N-type semiconductor layer cannot reach it, so they do not participate in the luminescence, and mainly play a role of stress release. Since the temperature is relatively low when the InGaN layer is grown, and the crystal quality of the layer is poor due to the doping of In, defects and V-pits will be generated and amplified in this place, thereby affecting the growth of the subsequent multi-quantum well layer; and the defects generated will also reduce the probability of radiation recombination and affect the luminous efficiency. Therefore, by specifically reducing the thickness of the InGaN layer close to the N-type semiconductor layer, the defects generated there are effectively reduced, and the amplification of V-pits is reduced, thereby improving the growth of the subsequent multi-quantum well layer, and finally achieving the effect of improving the luminous efficiency. Therefore, the present invention solves the problem of low brightness of LED epitaxial wafers in the prior art.
[0111] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0112] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. An LED epitaxial wafer, characterized in that: It includes an N-type semiconductor layer, a stress release layer and a light-emitting layer, wherein the light-emitting layer includes a first multi-quantum well layer and a second multi-quantum well layer arranged in sequence, wherein the first multi-quantum well layer and the second multi-quantum well layer are both periodically overlapped structures, and both include a quantum well layer and a quantum barrier layer, wherein the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer, and the thickness of the quantum well layer in the first multi-quantum well layer is less than the thickness of the quantum well layer in the second multi-quantum well layer.
2. The LED epitaxial wafer according to claim 1, characterized in that: The period number of the first multi-quantum well layer is 1-5, and the sum of the period numbers of the first multi-quantum well layer and the second multi-quantum well layer is 6-14.
3. The LED epitaxial wafer according to claim 2, characterized in that: The ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 82%-97%.
4. The LED epitaxial wafer according to claim 1, characterized in that: In a single period, the thickness of the quantum well layer in the second multi-quantum well layer is 2nm-4nm, and the thickness of the quantum barrier layer is 8nm-12nm.
5. The LED epitaxial wafer according to claim 1, characterized in that: The LED epitaxial wafer also includes a substrate, and an AlN layer, a buffer layer, a three-dimensional GaN layer, a non-doped GaN layer, an electron blocking layer and a P-type semiconductor layer sequentially stacked on the substrate; The N-type semiconductor layer, the stress release layer and the light-emitting layer are sequentially stacked between the undoped GaN layer and the electron blocking layer.
6. A method for preparing an LED epitaxial wafer, characterized in that: Used to prepare the LED epitaxial wafer according to any one of claims 1 to 5, the preparation method comprising: Provide semi-finished epitaxial wafers; sequentially growing an N-type semiconductor layer, a stress release layer and a light-emitting layer on the semi-finished epitaxial wafer; Among them, the light-emitting layer includes a first multi-quantum well layer and a second multi-quantum well layer arranged in sequence, the first multi-quantum well layer and the second multi-quantum well layer are both periodically overlapping structures, and both include quantum well layers and quantum barrier layers, the quantum well layer is an InGaN layer, and the quantum barrier layer is a GaN layer, and the thickness of the quantum well layer in the first multi-quantum well layer is less than the thickness of the quantum well layer in the second multi-quantum well layer.
7. The method for preparing an LED epitaxial wafer according to claim 6, characterized in that: The step of sequentially growing an N-type semiconductor layer, a stress release layer and a light-emitting layer on the semi-finished epitaxial wafer comprises: placing the semi-finished epitaxial wafer in an MOCVD device, and sequentially growing the N-type semiconductor layer, the stress release layer and the light-emitting layer on the semi-finished epitaxial wafer, When the InGaN layer in the light-emitting layer is grown, the growth temperature is 700°C-850°C, the In component is 10%-30%, the MO source is TEGa and TMIn, the introduced gas is N2 and NH3, NH3 is used as the reaction gas, N2 is used as the carrier gas, the growth pressure is 100torr-300torr, and the thickness of the InGaN layer in the first multi-quantum well layer is less than the thickness of the InGaN layer in the second multi-quantum well layer.
8. The method for preparing an LED epitaxial wafer according to claim 7, characterized in that: The thickness of the quantum well layer in the second multi-quantum well layer is 2nm-4nm, and the ratio of the thickness of the quantum well layer in the first multi-quantum well layer to the thickness of the quantum well layer in the second multi-quantum well layer is 82%-97%.
9. The method for preparing an LED epitaxial wafer according to claim 8, characterized in that: The period number of the first multi-quantum well layer is 1-5, and the sum of the period numbers of the first multi-quantum well layer and the second multi-quantum well layer is 6-14.
10. An LED chip, characterized in that: The LED chip comprises the LED epitaxial wafer described in any one of claims 1 to 5.