Adaptive pseudo resistance circuit and amplifier circuit for acquiring physiological electrical signals

Abstract

The invention discloses a self-adaptive pseudo resistance circuit and an amplifier circuit used for collecting physiological electrical signals, the self-adaptive pseudo resistance circuit comprises a pseudo resistance unit, a floating power supply generation unit and a bias voltage generation unit, the floating power supply generation unit generates a first voltage and a second voltage after obtaining an output voltage of the pseudo resistance unit, and the first voltage and the second voltage are output by the bias voltage generation unit; the bias voltage generation unit generates at least one pair of bias voltages according to the first voltage and the second voltage and outputs the bias voltages to the pseudo resistance unit, so that the pseudo resistance unit presents a corresponding resistance value, and the first voltage and the second voltage change along with the output voltage, and the difference value between the first voltage and the second voltage is a fixed value. The resistance value of the pseudo resistor unit can be gradually increased along with the increase of the output voltage, so that the self-adaptive adjustment of the pseudo resistor is realized, and the starting speed of the amplifier can be improved after the pseudo resistor unit is applied to the amplifier.

Description

Technical Field

[0001] The present application relates to the technical field of physiological electrical signal acquisition, and in particular to an adaptive pseudo-resistance circuit and an amplifier circuit for acquiring physiological electrical signals. Background Art

[0002] At present, physiological electrical signals are generally collected by setting an amplifier. In order to produce a sufficiently low low-frequency cutoff point of the high-pass filter, a pseudo-resistor with a high resistance is usually set in the amplifier feedback loop. The change and voltage dependence of the pseudo-resistor cause the high-pass corner frequency to be set much lower than 0.5Hz, which prolongs the stabilization time of the amplifier input bias point to tens of seconds, resulting in a long amplifier startup time. Summary of the invention

[0003] An embodiment of the present application provides an adaptive pseudo-resistance circuit and an amplifier circuit for collecting physiological electrical signals. After the floating power supply generating unit obtains the output voltage of the pseudo-resistance unit, it generates a first voltage and a second voltage. The bias voltage generating unit generates at least one pair of bias voltages according to the first voltage and the second voltage and outputs them to the pseudo-resistance unit, so that the pseudo-resistance unit presents a corresponding resistance value, so as to improve the startup speed of the amplifier after the pseudo-resistance unit is applied to the amplifier.

[0004] In a first aspect, an adaptive pseudo-resistance circuit is provided, comprising: a pseudo-resistance unit, comprising an input terminal, an output terminal and at least one pair of bias voltage terminals, for presenting a resistance value corresponding to the bias voltage when an input voltage is connected to the input terminal and each bias voltage terminal is respectively connected to a bias voltage; a floating power supply generating unit, comprising a control terminal, a first voltage terminal and a second voltage terminal, the control terminal being connected to the output terminal and for generating a first voltage at the first voltage terminal and a second voltage at the second voltage terminal according to an output voltage obtained from the output terminal, the first voltage and the second voltage varying with the output voltage, and a difference between the first voltage and the second voltage being a fixed value; a bias voltage generating unit, connected to the first voltage terminal, the second voltage terminal and each bias voltage terminal, for generating at least one pair of bias voltages according to the first voltage obtained from the first voltage terminal and the second voltage obtained from the second voltage terminal, and inputting each bias voltage into a corresponding bias voltage terminal, respectively, and each pair of bias voltages corresponding to a pair of bias voltage terminals.

[0005] In a second aspect, an amplifier circuit for collecting physiological electrical signals is provided, comprising an operational amplifier and an adaptive pseudo-resistance circuit as described in the first aspect, wherein the operational amplifier has a differential input terminal and a differential output terminal, and the pseudo-resistance unit in the adaptive pseudo-resistance circuit is arranged between the differential input terminal and the differential output terminal.

[0006] By applying the above technical solution, the adaptive pseudo-resistance circuit includes a pseudo-resistance unit, a floating power supply generating unit and a bias voltage generating unit. After the floating power supply generating unit obtains the output voltage of the pseudo-resistance unit, it generates a first voltage and a second voltage and outputs them to the bias voltage generating unit, so that the bias voltage generating unit generates at least one pair of bias voltages and outputs them to the pseudo-resistance unit, so that the pseudo-resistance unit presents a corresponding resistance value. Since the first voltage and the second voltage change with the output voltage, and the difference between the first voltage and the second voltage is a fixed value. The resistance value of the pseudo-resistance unit can be gradually increased with the increase of the output voltage. After the output voltage increases to a stable value, the bias voltage generated by the bias voltage generating unit no longer changes, so that the pseudo-resistance unit presents a stable resistance value, so that the pseudo-resistance has a wide linear range and easy-to-tune characteristics. After the pseudo-resistance unit is applied to the amplifier, the charging can be accelerated, the startup speed of the amplifier can be improved, and the signal inconsistency caused by electrode offset, motion artifact or stimulation artifact can be effectively reduced, thereby improving the robustness and reliability of the physiological electrical signal acquisition system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0008] Figure 1 A schematic diagram of the structure of an adaptive pseudo-resistance circuit according to an embodiment of the present application;

[0009] Figure 2 A schematic diagram of the structure of a pseudo-resistance unit according to an embodiment of the present application;

[0010] Figure 3 This is a structural schematic diagram of a floating power supply generating unit according to an embodiment of the present application;

[0011] Figure 4 is a schematic structural diagram of a bias voltage generating unit according to an embodiment of the present application;

[0012] Figure 5 This is a schematic diagram of the structure of an amplifier circuit for collecting physiological electrical signals according to an embodiment of the present application;

[0013] Figure 6 The pseudo resistor unit of the embodiment of the present application has different output voltages V B Schematic diagram of resistance-voltage characteristics under ;

[0014] Figure 7A schematic diagram showing the influence of possible mismatches in the transistor manufacturing process due to process reasons on the final stable resistance value of the pseudo-resistance unit in the embodiment of the present application;

[0015] Figure 8 A schematic diagram showing a comparison of the reaction speed of a physiological electrical signal acquisition circuit entering a normal working state when using the pseudo-resistance unit of the embodiment of the present application and using a traditional pseudo-resistance;

[0016] Fig. 9 is the current I of the second current source of different embodiments of the present application 2 Schematic diagram for achieving different high-pass intercept points;

[0017] Fig.10 This is a schematic diagram of test results performed on a human body after tape-out using the amplifier circuit for collecting physiological electrical signals according to an embodiment of the present application. Fig.10 In the figure, (a) represents the acquisition of ECG signals, and (b) represents the acquisition of EMG signals. DETAILED DESCRIPTION

[0018] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0019] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0020] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0021] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0022] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0023] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0024] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0025] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0026] An adaptive pseudo-resistance circuit according to an embodiment of the present application includes a pseudo-resistance unit, a floating power supply generating unit and a bias voltage generating unit. After obtaining the output voltage of the pseudo-resistance unit, the floating power supply generating unit generates a first voltage and a second voltage and outputs the first voltage and the second voltage to the bias voltage generating unit, so that the bias voltage generating unit generates at least one pair of bias voltages and outputs the bias voltages to the pseudo-resistance unit, so that the pseudo-resistance unit presents a corresponding resistance value. Since the first voltage and the second voltage vary with the output voltage, and the difference between the first voltage and the second voltage is a fixed value, the resistance value of the pseudo-resistance unit can be gradually increased with the increase of the output voltage, thereby realizing adaptive adjustment of the pseudo-resistance. After the pseudo-resistance unit is applied to an amplifier, the startup speed of the amplifier can be improved.

[0027] like Figure 1 As shown, the adaptive pseudo-resistance circuit includes:

[0028] The pseudo resistor unit 10 includes an input terminal, an output terminal and at least one pair of bias voltage terminals, and is used to present a resistance value corresponding to the bias voltage when an input voltage is connected to the input terminal and each bias voltage terminal is connected to a bias voltage respectively;

[0029] A floating power supply generating unit 20 includes a control terminal, a first voltage terminal and a second voltage terminal, wherein the control terminal is connected to the output terminal and is used to generate a first voltage at the first voltage terminal and a second voltage at the second voltage terminal according to an output voltage obtained from the output terminal, wherein the first voltage and the second voltage vary with the output voltage, and a difference between the first voltage and the second voltage is a fixed value;

[0030] The bias voltage generating unit 30 is connected to the first voltage terminal, the second voltage terminal and each bias voltage terminal, and is used to generate at least one pair of bias voltages according to the first voltage obtained from the first voltage terminal and the second voltage obtained from the second voltage terminal, and input each bias voltage to the corresponding bias voltage terminal, respectively, and each pair of bias voltages corresponds to a pair of bias voltage terminals.

[0031] In this embodiment, after the input end of the pseudo-resistance unit 10 is connected to the input voltage, an output voltage is generated at the output end, and the output voltage gradually increases. After the control end of the floating power supply generating unit 20 obtains the output voltage, a first voltage is generated at the first voltage end, and a second voltage is generated at the second voltage end. The first voltage and the second voltage change with the output voltage, and the difference between the first voltage and the second voltage is a fixed value. Afterwards, the bias voltage generating unit 30 generates at least one pair of bias voltages according to the first voltage and the second voltage obtained from the floating power supply generating unit 20. Finally, the bias voltage generating unit 30 outputs the bias voltage to the pseudo-resistance unit 10, so that the pseudo-resistance unit 10 presents a resistance value corresponding to the bias voltage. During this process, the bias voltage generated by the bias voltage generating unit 30 will gradually increase with the increase of the output voltage, so that the resistance value of the pseudo-resistance unit 10 will also gradually increase. After the output voltage increases to a stable value, the bias voltage generated by the bias voltage generating unit 30 will no longer change, so that the pseudo-resistance unit 10 presents a stable resistance value, thereby realizing adaptive adjustment of the pseudo-resistance. After the pseudo-resistance unit 10 is applied to the amplifier, the startup speed of the amplifier can be improved, and the stability of the amplifier after the startup is completed is guaranteed.

[0032] Each pair of bias voltages corresponds to a pair of bias voltage terminals. For example, if the pseudo resistor unit 10 includes a pair of bias voltage terminals, the bias voltage generating unit 30 generates a pair of bias voltages. If the pseudo resistor unit 10 includes three pairs of bias voltage terminals, the bias voltage generating unit 30 generates three pairs of bias voltages.

[0033] The adaptive pseudo-resistance circuit of the embodiment of the present application includes a pseudo-resistance unit 10, a floating power supply generating unit 20 and a bias voltage generating unit 30. After the floating power supply generating unit 20 obtains the output voltage of the pseudo-resistance unit 10, it generates a first voltage and a second voltage and outputs them to the bias voltage generating unit 30, so that the bias voltage generating unit 30 generates at least one pair of bias voltages and outputs them to the pseudo-resistance unit 10, so that the pseudo-resistance unit 10 presents a corresponding resistance value. Since the first voltage and the second voltage change with the output voltage, and the difference between the first voltage and the second voltage is a fixed value, the resistance value of the pseudo-resistance unit 10 can be gradually increased with the increase of the output voltage. After the output voltage increases to a stable value, the bias voltage generated by the bias voltage generating unit 30 no longer changes, so that the pseudo-resistance unit 10 presents a stable resistance value, so that the pseudo-resistance has a wide linear range and easy to tune characteristics. After the pseudo-resistance unit 10 is applied to the amplifier, the charging can be accelerated, the startup speed of the amplifier can be improved, and the signal inconsistency caused by electrode offset, motion artifacts or stimulation artifacts can be effectively reduced, and the robustness and reliability of the physiological electrical signal acquisition system are improved.

[0034] In some embodiments of the present application, Figure 3As shown, the floating power generation unit 20 includes:

[0035] The first field effect tube M Sp , the first field effect tube M Sp The drain-source voltage and the second voltage V SSPR The sum is the first voltage V DDPR ;

[0036] The second field effect tube M Bn , output voltage V B Subtract the second field effect tube M Bn The gate-source voltage is the second voltage V SSPR ;

[0037] The first current mirror 21 and the second current mirror 22 are used to fix the current flowing through the first field effect transistor M Sp and the second field effect tube M Bn The current of the first field effect transistor M Sp The drain-source voltage of the second field effect transistor M Bn The gate-source voltage is a fixed value.

[0038] In this embodiment, the first current mirror 21 and the second current mirror 22 can be fixed to flow through the first field effect transistor M Sp and the second field effect tube M Bn The current of the first field effect transistor M Sp The drain-source voltage of the second field effect transistor M Bn The gate-source voltage of the first field effect transistor M is fixed. Sp The drain-source voltage and the second voltage V SSPR The sum is the first voltage V DDPR , and the output voltage V B Subtract the second field effect tube M Bn The gate-source voltage is the second voltage V SSPR , thereby ensuring that the first voltage V DDPR and the second voltage V SSPR With the output voltage V B changes, and the first voltage V DDPR and the second voltage V SSPR The difference between is a fixed value, which improves the reliability of the floating power generation unit 20.

[0039] In some embodiments of the present application, the first current mirror 21 includes a third field effect transistor M 3 , the fourth field effect tube M 4 and the first current source I 1 The second current mirror 22 includes a fifth effect transistor M 5 、The sixth field effect tube M 6 and the second current source I 2 ,

[0040] The third field effect tube M 3 The source of the fourth field effect tube M 4 The source of the second field effect tube M Bn The drain and the second current source I 2 The input terminal is connected to the first external voltage V DD06 , the third field effect tube M 3 The gate and drain of the fourth field effect transistor M 4 The gates of the first current source I 1 The input terminal of the fourth field effect tube M 4 The drain and the first field effect transistor M Sp The source of the first field effect transistor M is connected to the first voltage terminal. Sp The gate and drain of the fifth field effect transistor M are connected 5 The drain of the second field effect transistor M Bn The gate of the second field effect transistor M is the control terminal. Bn The source and the first field effect transistor M Sp The drain of the second current source I 2 The output end is connected to the sixth field effect transistor M 6 The drain and gate of the fifth field effect transistor M 5 The gate of the first current source I 1 The output end of the fifth field effect tube M 5 The source and the sixth field effect transistor M 6 The source of the second external voltage V SS06 , the second field effect tube M Bn The substrate is grounded.

[0041] In this embodiment, the first current mirror 21 and the second current mirror 22 are used to fix the current flowing through the first field effect transistor M. Sp and the second field effect tube M Bn When the input terminal of the pseudo resistor unit 10 enters the input voltage V A When the current flows into the output terminal, the output voltage V B Gradually begins to rise, without considering some secondary effects of the field effect tube, due to the flow through the second field effect tube M Bn The current of is locked by two current mirrors, so its gate-source voltage remains fixed, and its source voltage (i.e., the second voltage V SSPR ) is equal to the output voltage V B Subtract the second field effect tube M Bn The gate-source voltage, that is, the second voltage V SSPR As the output voltage V B The first voltage V DDPR Equal to the first field effect tube M SpThe drain-source voltage and the second voltage V SSPR The sum of the first field effect transistor M Sp The current value of the first field effect tube M is also fixed. Sp The drain-source voltage is also fixed, thereby achieving the first voltage V DDPR and the second voltage V SSPR The difference between them is a function of a fixed value, and because the second voltage V SSPR As the output voltage V B Therefore, the first voltage V DDPR Also as the output voltage V B changes, thereby further improving the reliability of the floating power generation unit 20. In addition, by adjusting the first field effect transistor M Sp and the second field effect tube M Bn The width-to-length ratio can control the second voltage V SSPR The starting voltage and the first voltage V DDPR and the second voltage V SSPR The difference between them increases flexibility.

[0042] In some embodiments of the present application, the third field effect transistor M 3 And the fourth field effect tube M 4 The width-to-length ratio is 1:1, and the fifth effect tube M 5 And the sixth field effect tube M 6 The width-to-length ratio is 2:1.

[0043] In this embodiment, the width-to-length ratio of the field effect transistor in the first current mirror 21 is different from the width-to-length ratio of the field effect transistor in the second current mirror 22, which can ensure that the first current mirror 21 and the second current mirror 22 reliably conduct the current passing through the first field effect transistor M. Sp and the second field effect tube M Bn The current is clamped, so that the first voltage V DDPR and the second voltage V SSPR The difference between them is a fixed value.

[0044] In some embodiments of the present application, Figure 4 As shown, the bias voltage generating unit 30 includes:

[0045] A reference voltage subunit 31, including a reference voltage terminal, for converting a bias current into a reference voltage;

[0046] The bias voltage subunit 32 is connected to the reference voltage terminal and is used to adjust the bias voltage according to the first voltage V DDPR and the second voltage V SSPR , and the reference voltage obtained from the reference voltage subunit 31, generate a bias voltage.

[0047] In this embodiment, the reference voltage subunit 31 obtains the bias current, converts the bias current into a reference voltage, and sends the reference voltage to the bias voltage subunit 32 through the reference voltage terminal. The bias voltage subunit 32 generates a reference voltage according to the first voltage V obtained from the floating power supply generating unit 20. DDPR and the second voltage V SSPR , and the reference voltage generates at least one pair of bias voltages, thereby improving the reliability of the bias voltage generating unit 30.

[0048] In some embodiments of the present application, Figure 4 As shown, the reference voltage subunit 31 includes a third current source I 0 And the seventh field effect tube M Dp , the bias current is provided by the third current source I 0 Provided that the third current source I 0 The input terminal is connected to a third external voltage V DD , the third current source I 0 The output terminal and the seventh field effect tube M Dp The source of the seventh field effect transistor M is connected to the reference voltage terminal. Dp The gate and drain are grounded.

[0049] In this embodiment, the third current source I 0 The output terminal and the seventh field effect tube M Dp The source of the seventh field effect transistor M is connected to the reference voltage terminal. Dp The gate and drain of the seventh field effect transistor M Dp As a diode, the seventh field effect transistor M Dp From the third current source I 0 The bias current is obtained and converted into a reference voltage with ground as the reference, and then the reference voltage is output to the bias voltage subunit 32 via the reference voltage terminal, thereby ensuring that the reference voltage subunit 31 reliably outputs the reference voltage.

[0050] In some embodiments of the present application, each pair of bias voltage terminals is composed of a first bias voltage terminal and a second bias voltage terminal, the bias voltage subunit 32 includes at least one eighth field effect transistor and at least one ninth field effect transistor, the number of the eighth field effect transistor and the number of the ninth field effect transistor are equal, and each group of the eighth field effect transistor and the ninth field effect transistor corresponds to a pair of bias voltages,

[0051] The drain of the eighth field effect transistor is connected to the first voltage terminal, the gate of the eighth field effect transistor is connected to the corresponding second bias voltage terminal, the source of the eighth field effect transistor is connected to the corresponding first bias voltage terminal, the source of the eighth field effect transistor is connected to the drain of the ninth field effect transistor, the gate of the ninth field effect transistor is connected to the reference voltage terminal, the source of the ninth field effect transistor is connected to the second voltage terminal, and the substrates of the eighth field effect transistor and the ninth field effect transistor are both grounded.

[0052] In this embodiment, the reference voltage is applied to the gate of the ninth field effect transistor, so that the ninth field effect transistor drives the eighth field effect transistor to generate a first bias voltage and a second bias voltage at the source and gate respectively, thereby ensuring that the bias voltage subunit 32 reliably generates a bias voltage.

[0053] For example, if Figure 4 As shown, the bias voltage subunit 32 includes three eighth field effect transistors (M n1 、M n2 、M n3 ) and 3 ninth field effect tubes (MD n1 ,MD n2 ,MD n3 ), the first group of eighth field effect tube M n1 And the ninth field effect tube MD n1 Generate the first pair of bias voltages (V l1 and V h1 ), I BIAS Represents the bias current. The eighth field effect transistor and the second group of eighth field effect transistors M n2 And the ninth field effect tube MD n2 Generate a second pair of bias voltages (V l2 and V h2 ), the third group eighth field effect tube M n3 And the ninth field effect tube MD n3 Generate the third pair of bias voltages (V l3 and V h3 ).

[0054] In some embodiments of the present application, the seventh field effect transistor M Dp The eighth field effect transistor and the ninth field effect transistor use the same width-to-length ratio, thereby reducing possible errors caused by process angle deviation and improving the accuracy of the bias voltage.

[0055] In some embodiments of the present application, the pseudo resistor unit 10 includes at least one tenth field effect transistor and at least one eleventh field effect transistor, and the number of the tenth field effect transistor and the number of the eleventh field effect transistor are equal.

[0056] In the case that there is only one tenth field effect transistor and one eleventh field effect transistor, the gates of the tenth field effect transistor and the eleventh field effect transistor are connected to the first bias voltage terminal, the drains of the tenth field effect transistor and the eleventh field effect transistor are connected to the second bias voltage terminal, the source of the tenth field effect transistor is the input terminal, and the source of the eleventh field effect transistor is the output terminal;

[0057] In the case where there are multiple tenth field effect transistors and eleventh field effect transistors, the drain of the previous tenth field effect transistor is connected to the source of the next tenth field effect transistor, the source of the previous eleventh field effect transistor is connected to the drain of the next eleventh field effect transistor, the source of the first tenth field effect transistor is the input terminal, the drain of the last tenth field effect transistor is connected to the drain of the first eleventh field effect transistor, and the source of the last eleventh field effect transistor is the output terminal, and every two adjacent field effect transistors in the pseudo-resistance unit 10 are correspondingly connected to a pair of bias voltage terminals, the gates of each field effect transistor in the pseudo-resistance unit 10 are respectively connected to the corresponding first bias voltage terminals, and the sources of each field effect transistor in the pseudo-resistance unit 10 are respectively connected to the corresponding second bias voltage terminals.

[0058] In this embodiment, the pseudo-resistance unit 10 includes at least one tenth field effect tube and at least one eleventh field effect tube, and the number of the tenth field effect tube and the eleventh field effect tube is equal, which can ensure that the pseudo-resistance unit 10 has a symmetrical resistance characteristic. In the case where the tenth field effect tube and the eleventh field effect tube are both one, the first bias voltage terminal is drawn from the gate of the tenth field effect tube and the eleventh field effect tube, and the second bias voltage terminal is drawn from the drain of the tenth field effect tube and the eleventh field effect tube. In the case where there are multiple tenth field effect tubes and eleventh field effect tubes, each two adjacent field effect tubes in the pseudo-resistance unit 10 are connected to a pair of bias voltage terminals, and each first bias voltage terminal is drawn from the gate of each field effect tube in the pseudo-resistance unit 10, and each second bias voltage terminal is drawn from the source of each field effect tube in the pseudo-resistance unit 10, thereby ensuring the reliability of the pseudo-resistance unit 10.

[0059] For example, with Figure 4 The three pairs of bias voltages (V l1 and V h1 、V l2 and V h2 、V l3 and V h3 ) corresponds to, such as Figure 2 As shown, the pseudo resistor unit 10 includes three pairs of bias voltage terminals, which are composed of two tenth field effect transistors (M p3 and M p1 ) and two eleventh field effect tubes (respectively M p2 and M p4 ) is composed of field effect tube M p3 The source of the pseudo resistor unit 10 is the input terminal, and the field effect transistor M p3 The drain of the field effect transistor M p1 The source of the field effect tube M p1 The drain of the field effect transistor M p2 The drain of the field effect transistor M p1 The gate of the field effect transistor M p2 The gate of the field effect transistor Mp2 The source of the field effect transistor M p4 The drain of the field effect transistor M p4 The source of is the output terminal of the pseudo resistor unit 10, and the field effect transistor M p3 The gate and drain lead to the second pair of bias voltage terminals (corresponding to V l2 and V h2 ), field effect tube M p1 and FET M p2 The gate and drain of the device lead out the first pair of bias voltage terminals (corresponding to V l1 and V h1 ), field effect tube M p4 The gate and drain lead to the third pair of bias voltage terminals (corresponding to V l3 and V h3 ).

[0060] In some embodiments of the present application, the first external voltage V DD06 , the second external voltage V SS06 and the third external voltage V DD The first current source I 1 The current of the second current source I 2 The current is 100nA, and the first voltage V DDPR and the second voltage V SSPR The difference between them is 450mV to ensure that all FETs in the floating power generation circuit have sufficient voltage margin. In the charging state, the output voltage V B Gradually increases until it is equal to the input voltage V A In this process, each pair of bias voltages gradually changes from negative to positive, so that the resistance value of the pseudo-resistance unit 10 gradually increases, forming a resistance adaptive change characteristic, which greatly speeds up the current charging speed. In addition, since this process is extremely fast and is not the final stable state of the circuit, the final performance of the circuit only depends on the stable state after the charging is completed. Therefore, the non-ideal characteristics of the circuit device process at this time do not affect the performance of the final circuit, that is, they will not affect the final resistance value of the pseudo-resistance unit 10.

[0061] Taking the pseudo resistor unit 10 including three pairs of bias voltage terminals as an example, once charging is completed, the output voltage V B Equal to the input voltage V A , then the resistance value of the pseudo resistance unit 10 can be expressed as:

[0062]

[0063] in, represents the thermal voltage, k is the Boltzmann constant, q is the charge of the electron, and T is the temperature. By using a PTAT (positive temperature coefficient) current source as the third current source I 0 , which can further offset the error caused by temperature. Therefore, the final resistor is highly resistant to process corner effects, temperature and random process variations, achieving strong robustness.

[0064] like Figure 6 The pseudo resistor unit 10 of the embodiment of the present application is shown in FIG. B Schematic diagram of the resistance-voltage characteristic under the condition of the pseudo-resistance. Since the structure of the pseudo-resistance is completely symmetrical, only the input voltage V is shown in the figure. A Greater than the output voltage V B When △V=V A -V B , Charging state indicates the charging state, and Settling state indicates the stable state after charging is completed. As can be seen from the figure, at V B Charge to a stable voltage V cm In the process, the resistance value R of the pseudo resistor unit 10 AB Gradually increases until it reaches the final stable state. In the stable state, its resistance value can remain constant under the voltage change from -0.3V to 0.3V, achieving high linearity and meeting the needs of most physiological electrical signal acquisition circuits.

[0065] like Figure 7 The figure shows the effect of possible mismatch in transistor manufacturing process due to process reasons on the final steady-state resistance of the pseudo-resistance unit 10 of the embodiment of the present application. Through 200 Monte Carlo simulations, the results show that the average resistance value of the pseudo-resistance unit 10 is 1.98TΩ, and the standard deviation is 3.25GΩ, which is less than 0.2%. It proves that the low sensitivity of the adaptive pseudo-resistance structure to transistor mismatch can ensure high stability in actual production and manufacturing.

[0066] The embodiment of the present application also proposes an amplifier circuit for collecting physiological electrical signals. Since the first voltage and the second voltage change with the output voltage, and the difference between the first voltage and the second voltage is a fixed value, the resistance value of the pseudo-resistance unit can gradually increase with the increase of the output voltage, thereby realizing adaptive adjustment of the pseudo-resistance, and further improving the startup speed of the operational amplifier.

[0067] like Figure 5As shown, the amplifier circuit for collecting physiological electrical signals includes an operational amplifier OTA and the above-mentioned adaptive pseudo-resistance circuit, the operational amplifier OTA has a differential input terminal and a differential output terminal, the differential input terminal receives a differential signal, and the differential output terminal outputs an amplified and inverted differential signal, and the pseudo-resistance unit 10 ( Figure 5 The physiological electrical signal may include any one of an electrocardiogram signal, an electroencephalogram signal, an electromyogram signal, an electrogastric signal, and an electroretinal signal.

[0068] In the amplifier circuit for collecting physiological electrical signals of the embodiment of the present application, the pseudo-resistance unit 10 in the adaptive pseudo-resistance circuit is set between the differential input terminal and the differential output terminal of the operational amplifier OTA. Since the resistance value of the pseudo-resistance unit 10 changes with the output voltage V B The output voltage V B After increasing to a stable value, the bias voltage generated by the bias voltage generating unit 30 no longer changes, so that the pseudo-resistance unit 10 presents a stable resistance value, while ensuring that the operational amplifier OTA generates a sufficiently low low-frequency cutoff point of the high-pass filter, and at the same time ensuring the stability of the operational amplifier OTA after completion of startup.

[0069] In some embodiments of the present application, there are two adaptive pseudo-resistance circuits, and the corresponding pseudo-resistance units 10 are respectively a first pseudo-resistance unit and a second pseudo-resistance unit. The output terminal of the first pseudo-resistance unit (corresponding to V B ) Connect the negative terminal of the differential input V in- , the input terminal of the first pseudo-resistance unit (corresponding to V A ) Connect the positive terminal V out+ , the output terminal of the second pseudo-resistance unit (corresponding to V B ) Connect the positive terminal of the differential input V in+ , the input terminal of the second pseudo-resistance unit (corresponding to V A ) Connect the negative terminal V out- .

[0070] In this embodiment, by setting the output ends of the first pseudo-resistance unit and the second pseudo-resistance unit at the differential input ends of the operational amplifier OTA, the influence of small signals (physiological electrical signals) on the linearity of the pseudo-resistance can be eliminated after the circuit is stabilized.

[0071] In some embodiments of the present application, the amplifier circuit for collecting physiological electrical signals further includes two input capacitors C in , two feedback capacitors C f and two output capacitors CL , two input capacitors C in Connect in series to the negative terminal V in- and positive terminal V in+ , two feedback capacitors C f The two output capacitors C are connected in parallel with the first pseudo resistance unit and the second pseudo resistance unit respectively. L One end of each is connected to the positive end V out+ and negative terminal V out- , two output capacitors C L The other ends are grounded.

[0072] In some embodiments of the present application, the amplifier circuit for collecting physiological electrical signals achieves a precise closed-loop gain (C) of 37.4 dB through a capacitor negative feedback structure. in / C f =19.2pF / 257.2fF). The high-pass intercept point in the transfer function of this circuit is determined by the feedback capacitor C f The capacitance and the resistance of the pseudo-resistance unit 10 are jointly determined, and are set to 0.5Hz in this design. The differential input transistors of the operational amplifier OTA are biased in the subthreshold region (gm / Id=27), and thick gate transistors are used to avoid current leakage. The common-mode feedback circuit is not shown in the figure, and can be implemented using a variety of classic structures. The power supply voltage of the operational amplifier OTA is 1.2V, and the output common-mode voltage is 0.6V. In the stable state, the voltage V A =V B =V cm =0.6V. The second field effect tube M Bn The gate-source voltage is set to 0.6V, so in the steady state the second voltage V SSPR is 0V. This ensures that the seventh field effect transistor M in the floating bias unit Dp The second field effect tube M is in the same working state as the ninth field effect tube, thereby improving the stability of the final pseudo-resistance value. Bn The body effect makes its gate-source voltage naturally less than 0.6V in the charging state, so that the second external voltage V SS06 = -0.6V during the charging process, the field effect tube has a certain voltage margin. In addition, by adding the second current source I 2 The current can reduce the second voltage V in the final stable state SSPR , so that the resistance value of the pseudo-resistance unit 10 is reduced to adjust different cut-off frequencies to meet different application requirements.

[0073] like Figure 8The figure shows a schematic diagram of the comparison of the reaction speed of the physiological electrical signal acquisition circuit entering a normal working state using the pseudo-resistance unit 10 of the embodiment of the present application and the traditional pseudo-resistance. The blue line in the figure represents the case of using the pseudo-resistance unit 10 of the embodiment of the present application, and the red line represents the case of using the traditional pseudo-resistance. It can be seen that the pseudo-resistance unit 10 of the embodiment of the application can greatly shorten the stabilization time required by the circuit, from the original 10s level to 10ms level, and the speed is increased by nearly 1000 times.

[0074] like Fig. 9 The second current source I of the embodiment of the present application is shown in FIG. 2 Schematic diagram of realizing different high-pass interception points with different second current sources I 2 The current can achieve different high-pass intercept points.

[0075] like Fig.10 FIG. 1 is a schematic diagram showing the test results of the amplifier circuit for collecting physiological electrical signals according to an embodiment of the present application after tape-out on a human body. Fig.10 In the figure, (a) represents the acquisition of ECG signals, and (b) represents the acquisition of myoelectric signals. It can be seen that the amplifier circuit for acquiring physiological electrical signals in the embodiment of the present application can realize the normal acquisition of ECG signals and myoelectric signals.

[0076] In addition, although exemplary embodiments have been described herein, the scope includes any and all embodiments based on the present disclosure with equivalent elements, modifications, omissions, combinations (e.g., various embodiments intersecting schemes), adaptations or changes. The elements in the claims will be interpreted broadly based on the language adopted in the claims, and are not limited to the examples described in this specification or during the implementation of this application, and the examples will be interpreted as non-exclusive. Therefore, this specification and examples are intended to be considered as examples only, and the true scope and spirit are indicated by the following claims and the full scope of their equivalents.

[0077] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, a person of ordinary skill in the art can use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the present disclosure. This should not be interpreted as an intention that a disclosed feature that is not required to be protected is necessary for any claim. On the contrary, the subject matter of the present disclosure may be less than all the features of a specific disclosed embodiment. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present disclosure should be determined with reference to the attached claims and the full scope of equivalent forms granted by these claims.

[0078] Multiple embodiments of the present disclosure are described in detail above, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concepts of the present disclosure, and these variations and modifications should all fall within the scope of protection required by the present disclosure.

Claims

1. An adaptive pseudo-resistance circuit, characterized in that: include: A pseudo-resistance unit, comprising an input terminal, an output terminal and at least one pair of bias voltage terminals, for presenting a resistance value corresponding to the bias voltage when the input terminal is connected to an input voltage and each of the bias voltage terminals is respectively connected to a bias voltage; a floating power supply generating unit, comprising a control terminal, a first voltage terminal and a second voltage terminal, wherein the control terminal is connected to the output terminal and is used to generate a first voltage at the first voltage terminal and a second voltage at the second voltage terminal according to an output voltage obtained from the output terminal, wherein the first voltage and the second voltage vary with the output voltage, and a difference between the first voltage and the second voltage is a fixed value; A bias voltage generating unit is connected to the first voltage terminal, the second voltage terminal and each of the bias voltage terminals, and is used to generate at least one pair of the bias voltages according to the first voltage obtained from the first voltage terminal and the second voltage obtained from the second voltage terminal, and input each of the bias voltages to the corresponding bias voltage terminal, respectively, and each pair of bias voltages corresponds to a pair of bias voltage terminals.

2. The adaptive pseudo-resistance circuit according to claim 1, characterized in that: The floating power supply generating unit comprises: a first field effect transistor, wherein the sum of a drain-source voltage of the first field effect transistor and the second voltage is the first voltage; A second field effect transistor, the output voltage minus the gate-source voltage of the second field effect transistor is the second voltage; The first current mirror and the second current mirror are used to fix the current flowing through the first field effect transistor and the second field effect transistor so that the drain-source voltage of the first field effect transistor and the gate-source voltage of the second field effect transistor are fixed values.

3. The adaptive pseudo-resistance circuit according to claim 2, characterized in that: The first current mirror includes a third field effect transistor, a fourth field effect transistor and a first current source, and the second current mirror includes a fifth field effect transistor, a sixth field effect transistor and a second current source. The source of the third field effect transistor, the source of the fourth field effect transistor, the drain of the second field effect transistor and the input end of the second current source are connected to the first external voltage, the gate and drain of the third field effect transistor and the gate of the fourth field effect transistor are commonly connected to the input end of the first current source, the drain of the fourth field effect transistor and the source of the first field effect transistor are connected to the first voltage end, the gate and drain of the first field effect transistor are connected to the drain of the fifth field effect transistor, the gate of the second field effect transistor is the control end, the source of the second field effect transistor and the drain of the first field effect transistor are connected to the second voltage end, the output end of the second current source is connected to the drain and gate of the sixth field effect transistor and the gate of the fifth field effect transistor, the output end of the first current source, the source of the fifth field effect transistor and the source of the sixth field effect transistor are connected to the second external voltage, and the substrate of the second field effect transistor is grounded.

4. The adaptive pseudo-resistance circuit according to claim 3, characterized in that: The width-to-length ratios of the third field effect tube and the fourth field effect tube are both 1:1, and the width-to-length ratios of the fifth field effect tube and the sixth field effect tube are both 2:

1.

5. The adaptive pseudo-resistance circuit according to claim 1, characterized in that: The bias voltage generating unit comprises: A reference voltage subunit, including a reference voltage terminal, for converting a bias current into a reference voltage; The bias voltage subunit is connected to the reference voltage terminal and is used to generate the bias voltage according to the first voltage and the second voltage, and the reference voltage obtained from the reference voltage subunit.

6. The adaptive pseudo-resistance circuit according to claim 5, characterized in that: The reference voltage subunit includes a third current source and a seventh field effect transistor, the bias current is provided by the third current source, the input end of the third current source is connected to a third external voltage, the output end of the third current source and the source of the seventh field effect transistor are connected to the reference voltage end, and the gate and drain of the seventh field effect transistor are grounded.

7. The adaptive pseudo-resistance circuit according to claim 5, characterized in that: Each pair of bias voltage terminals is composed of a first bias voltage terminal and a second bias voltage terminal, the bias voltage subunit includes at least one eighth field effect transistor and at least one ninth field effect transistor, the number of the eighth field effect transistor and the number of the ninth field effect transistor are equal, and each group of the eighth field effect transistor and the ninth field effect transistor corresponds to a pair of bias voltages, The drain of the eighth field effect transistor is connected to the first voltage terminal, the gate of the eighth field effect transistor is connected to the corresponding second bias voltage terminal, the source of the eighth field effect transistor is connected to the corresponding first bias voltage terminal, the source of the eighth field effect transistor is connected to the drain of the ninth field effect transistor, the gate of the ninth field effect transistor is connected to the reference voltage terminal, the source of the ninth field effect transistor is connected to the second voltage terminal, and the substrates of the eighth field effect transistor and the ninth field effect transistor are both grounded.

8. The adaptive pseudo-resistance circuit according to claim 7, characterized in that: The pseudo resistor unit includes at least one tenth field effect transistor and at least one eleventh field effect transistor, and the number of the tenth field effect transistor and the number of the eleventh field effect transistor are equal. In the case where there is only one of the tenth field effect transistor and the eleventh field effect transistor, the gates of the tenth field effect transistor and the eleventh field effect transistor are connected to the first bias voltage terminal, the drains of the tenth field effect transistor and the eleventh field effect transistor are connected to the second bias voltage terminal, the source of the tenth field effect transistor is the input terminal, and the source of the eleventh field effect transistor is the output terminal; In the case where there are multiple tenth field effect transistors and eleventh field effect transistors, the drain of the previous tenth field effect transistor is connected to the source of the next tenth field effect transistor, the source of the previous eleventh field effect transistor is connected to the drain of the next eleventh field effect transistor, the source of the first tenth field effect transistor is the input terminal, the drain of the last tenth field effect transistor is connected to the drain of the first eleventh field effect transistor, and the source of the last eleventh field effect transistor is the output terminal, and every two adjacent field effect transistors in the pseudo-resistance unit are correspondingly connected to a pair of bias voltage terminals, the gates of each field effect transistor in the pseudo-resistance unit are respectively connected to the corresponding first bias voltage terminals, and the sources of each field effect transistor in the pseudo-resistance unit are respectively connected to the corresponding second bias voltage terminals.

9. An amplifier circuit for collecting physiological electrical signals, characterized in that: It comprises an operational amplifier and an adaptive pseudo-resistance circuit as claimed in any one of claims 1 to 8, wherein the operational amplifier has a differential input terminal and a differential output terminal, and the pseudo-resistance unit in the adaptive pseudo-resistance circuit is arranged between the differential input terminal and the differential output terminal.

10. The amplifier circuit for collecting physiological electrical signals according to claim 9, characterized in that: There are two adaptive pseudo-resistance circuits, and the corresponding pseudo-resistance units are respectively a first pseudo-resistance unit and a second pseudo-resistance unit, the output end of the first pseudo-resistance unit is connected to the negative end of the differential input end, the input end of the first pseudo-resistance unit is connected to the positive end of the differential output end, the output end of the second pseudo-resistance unit is connected to the positive end of the differential input end, and the input end of the second pseudo-resistance unit is connected to the negative end of the differential output end.

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