Data filtering method based on pure lag and rate limitation
Through the data filtering method based on pure hysteresis and rate limiting, the problem that the prior art cannot adapt to all occasions is solved, and the effective filtering effect is achieved under different working conditions, and it has strong adaptability and flexibility.
Patent Information
- Application Number
- CN202411289483.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-27
AI Technical Summary
The existing data filtering methods cannot adapt to all occasions and cannot effectively deal with data noise problems under different working conditions.
The data filtering method based on pure hysteresis and rate limiting is adopted to adapt to different working conditions by adjusting the lag time, coefficient K and minimum rate RAT_MIN to achieve the expected filtering effect. The method includes transmitting real-time data to a pure lag calculation unit and a rate limiting module, performing mathematical operations and evaluation, limiting the rising and falling rates, and outputting the filtered result.
This method is highly adaptable and can flexibly adjust the lag time, coefficient and minimum rate to achieve effective filtering effects for different working conditions. It is suitable for a variety of occasions.
Smart Images
Figure CN119210400A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to instrument automation technology, and in particular to a data filtering method based on pure hysteresis and rate limitation. Background Art
[0002] In instrument automation work, it is often necessary to process a large amount of data, which is often a time series or a space series. Digital filtering technology (such as the publication (announcement) number: CN111539330B, which discloses a method for identifying digital display instruments in substations) is usually used to pre-process the data. Digital filtering refers to the use of mathematical methods to process the original data, remove the noise data mixed in the original data, and obtain the most representative data set.
[0003] There are many data filtering methods at present, including the conventional limited amplitude filtering method, median filtering method, arithmetic mean filtering method, recursive mean filtering method, etc. They have their own advantages and disadvantages, and no method can adapt to all occasions. Summary of the invention
[0004] The purpose of the present invention is to provide a data filtering method based on pure hysteresis and rate limitation, which can adapt to different working conditions by adjusting the hysteresis time, coefficient K and minimum rate RAT_MIN to achieve the expected filtering effect, so as to solve the problem that the existing filtering method cannot adapt to all occasions.
[0005] In order to achieve the above object, the present invention provides the following technical solution: a data filtering method based on pure hysteresis and rate limitation, comprising the following steps:
[0006] S01, according to a predetermined window period, input the collected real-time data to be transmitted to the pure lag calculation unit and the rate limiting module respectively;
[0007] S02, the pure hysteresis calculation unit adjusts the hysteresis time length according to the input hysteresis time, and performs mathematical operation with the real-time data through coefficients to obtain result parameters;
[0008] S03, evaluating the result parameters based on preset conditions;
[0009] S04. According to the evaluation obtained, the maximum value module combines the minimum rate to limit the minimum rate of the rate limiting module;
[0010] S05. The rate limiting module displays the limited increasing rate UP value and decreasing rate DOWN value based on the current rate.
[0011] Preferably, the preset condition is that the coefficient is inversely proportional to the strength of the filtering.
[0012] Preferably, in step S05, the rising rate UP value and the falling rate DOWN value displayed by the current rate output are filtered and then output.
[0013] Preferably, the input of the limiting increasing rate UP value and decreasing rate DOWN value in step S05 is executed by output transmission.
[0014] Preferably, the minimum rate described in step S04 is the minimum flow rate in a continuous window within a predetermined window period.
[0015] Preferably, the lag time in step S02 is a positive integer ≥ zero.
[0016] Preferably, the lag time is the difference between the actual passing time and the planned passing time in the predetermined window period.
[0017] Preferably, the coefficient is a positive real number greater than zero in the case of high-frequency oscillation under the predetermined window period.
[0018] Preferably, the rate limiting module is composed of different calculation units, and in step S05, the increase rate UP value and the decrease rate DOWN value are obtained by separate assignment.
[0019] Preferably, the pure hysteresis calculation unit comprises a link aggregation group LAG, an adder-subtractor SUB, a circuit control core ABS, and a binary number multiplication source element MUL connected in series in sequence, wherein:
[0020] The coefficients are directly transmitted to the binary number multiplication source element MUL;
[0021] The link aggregation group LAG collects input data of the input and the lag time;
[0022] The adder-subtractor SUB is used to obtain input data.
[0023] In the above technical scheme, the present invention provides a data filtering method based on pure lag and rate limitation, which has the following beneficial effects: the lag time TIME, coefficient K and minimum rate RAT_MIN in this data filtering method can be adjusted arbitrarily, and the expected filtering effect can be achieved by adjusting one or more of the above parameters for different working conditions, and it has the characteristics of strong adaptability and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0025] Figure 1 A circuit diagram provided for an embodiment of the present invention;
[0026] Figure 2 A schematic diagram of an implementation result window provided for an embodiment of the present invention.
[0027] Description of reference numerals:
[0028] Pure hysteresis calculation unit; 2. Maximum value module; 3. Rate limiting module; 4. Input; 5. Lag time TIME; 6. Coefficient K; 7. Minimum rate RAT_MIN; 8. Output OUT; 9. Current rate RAT_VA. DETAILED DESCRIPTION
[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0030] like Figure 1 As shown, the present invention relates to a data filtering method based on pure hysteresis and rate limitation, the steps of which include:
[0031] S01, according to a predetermined window period, the collected real-time data is transmitted to the pure lag calculation unit 1 and the rate limiting module 3 respectively;
[0032] S02, the pure hysteresis calculation unit 1 adjusts the hysteresis time according to the input hysteresis time 5, and performs mathematical operation with the real-time data through the coefficient 6 to obtain the result parameter;
[0033] S03. Evaluate the result parameters according to the preset conditions;
[0034] S04. According to the evaluation result, the maximum value module 2 combines with the minimum rate 7 to limit the minimum rate of the rate limiting module 3;
[0035] S05, the rate limiting module 3 displays the limited rising rate UP value and falling rate DOWN value, such as Figure 2 shown.
[0036] Furthermore, in one embodiment of the present invention, the preset condition is that the coefficient 6 is inversely proportional to the filtering strength.
[0037] In another embodiment, the rising rate UP value and the falling rate DOWN value displayed in step S05 are output after filtering.
[0038] In another embodiment, the increasing rate UP value and the decreasing rate DOWN value limited in step S05 are transmitted through output 8 for execution.
[0039] In another embodiment, the minimum rate 7 in step S04 is the minimum flow rate within a continuous window and within a predetermined window period.
[0040] In another embodiment, the lag time 8 in step S02 is taken as a positive integer ≥ zero.
[0041] In another embodiment, the lag time 5 is the difference between the actual transit time and the planned transit time, which occurs within a predetermined window period.
[0042] In another embodiment, coefficient 9 is a high frequency oscillation condition under a predetermined window period, and its value is a positive real number greater than zero.
[0043] In another embodiment, the rate limiting module 3 is composed of different calculation units, and in step S05, the increase rate UP value and the decrease rate DOWN value are obtained by separate assignment.
[0044] It should be noted that the pure hysteresis calculation unit 1 includes a link aggregation group LAG, an adder-subtractor SUB, a circuit control core ABS, and a binary number multiplication source element MUL which are connected in series in sequence, wherein:
[0045] The coefficient 6 is directly transmitted to the binary number multiplication source element MUL;
[0046] The link aggregation group LAG collects input data of input 4 and latency 5;
[0047] The adder-subtractor SUB is used to obtain input data of input 4.
[0048] In this data filtering method, the lag time TIME, the coefficient K and the minimum rate RAT_MIN can be flexibly adjusted to adapt to different working conditions and occasions, thereby achieving the expected filtering effect.
[0049] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0050] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0051] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0053] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.
[0054] The embodiments of the present application also provide a specific implementation of an electronic device capable of implementing all steps of the method in the above embodiments, and the electronic device specifically includes the following contents:
[0055] Processor, memory, communications interface and bus;
[0056] Wherein, the processor, memory, and communication interface communicate with each other via the bus;
[0057] The processor is used to call the computer program in the memory, and when the processor executes the computer program, all the steps in the method in the above embodiment are implemented.
[0058] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all the steps of the method in the above embodiments, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, all the steps of the method in the above embodiments are implemented.
[0059] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the hardware + program embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. Although the embodiment of this specification provides the method operation steps described in the embodiment or flow chart, more or less operation steps can be included based on conventional or non-creative means. The order of steps listed in the embodiment is only one way of executing the order of many steps, and does not represent the only execution order. When the device or terminal product in practice is executed, it can be executed in sequence or in parallel according to the method shown in the embodiment or the accompanying drawings (for example, a parallel processor or a multi-threaded processing environment, or even a distributed data processing environment). The term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, product or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, product or device. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or device including the elements. For the convenience of description, the above device is described by dividing it into various modules according to its functions. Of course, when implementing the embodiments of this specification, the functions of each module can be implemented in the same one or more software and / or hardware, or the module implementing the same function can be implemented by a combination of multiple sub-modules or sub-units. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The present invention is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the process and / or box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the process Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0060] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, the embodiments of this specification may be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of this specification may be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts refer to the partial description of the method embodiment. In the description of this specification, the description of the reference term "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of this specification.
[0061] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradicting each other. The above is only an embodiment of the embodiment of this specification and is not intended to limit the embodiment of this specification. For those skilled in the art, the embodiment of this specification may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiment of this specification shall be included in the scope of the claims of the embodiment of this specification.
Claims
1. A data filtering method based on pure hysteresis and rate limitation, characterized in that: The following steps are involved: S01, according to a predetermined window period, input (4) transmits the collected real-time data to the pure lag calculation unit (1) and the rate limiting module (3) respectively; S02, the pure hysteresis calculation unit (1) adjusts the length of the hysteresis time according to the input hysteresis time (5), and performs mathematical operation with the real-time data through the coefficient (6) to obtain result parameters; S03, evaluating the result parameters based on preset conditions; S04, according to the evaluation obtained, the maximum value module (2) combines with the minimum rate (7) to limit the minimum rate of the rate limiting module (3); S05. The rate limiting module (3) displays the limited increasing rate UP value and decreasing rate DOWN value by the current rate (9).
2. A data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The preset condition is that the coefficient (6) is inversely proportional to the strength of the filtering.
3. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: In step S05, the rising rate UP value and the falling rate DOWN value displayed by the current rate (9) output are filtered and then output.
4. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The input (4) of the limit-limited rising rate UP value and falling rate DOWN value in step S05 is transmitted and executed by the output (8).
5. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The minimum rate (7) described in step S04 is the minimum flow rate in a continuous window within a predetermined window period.
6. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The lag time (8) in the step S02 is a positive integer ≥ zero.
7. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The lag time (5) is the difference between the actual passing time and the planned passing time in the predetermined window period.
8. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The coefficient (9) is a positive real number greater than zero in the case of high frequency oscillation under the predetermined window period.
9. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The rate limiting module (3) is composed of different calculation units, and in step S05, obtains the rising rate UP value and the falling rate DOWN value by separate assignment.
10. The data filtering method based on pure hysteresis and rate limitation according to claim 1, characterized in that: The pure hysteresis calculation unit (1) comprises a link aggregation group LAG, an adder-subtractor SUB, a circuit control core ABS, and a binary number multiplication source element MUL which are connected in series in sequence, wherein: The coefficient (6) is directly transmitted to the binary number multiplication source element MUL; The link aggregation group LAG collects input data of the input (4) and the lag time (5); The adder-subtractor SUB is used to obtain input data of the input (4).