Rubidium atomic clock frequency source device with frequency offset adjusting function
By introducing a digital frequency offset adjustment circuit into the frequency source device, precise adjustment of the output frequency within the range of ±10Hz is achieved, which solves the problem that the existing technology cannot set frequency offset, and meets the needs of non-standard 10MHz frequency frequency standard applications. , providing higher frequency stability and accuracy.
Patent Information
- Application Number
- CN202411296004.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2024-12-27
AI Technical Summary
The existing frequency source devices cannot set the frequency offset of the frequency scale signal, and cannot meet the needs of some non-standard 10MHz frequency scale application environments.
A rubidium atomic clock frequency source device including Beidou antenna, Beidou receiving processor, rubidium clock taming synchronization circuit, digital frequency deviation adjustment circuit, frequency output processor, device management controller and power supply signal processor were designed, and the digital frequency deviation was passed. The adjustment circuit realizes accurate adjustment of the output frequency within ±10Hz range to meet non-standard frequency requirements.
It realizes fine-tuning of frequency offset in the range of ±10Hz, provides higher frequency stability and accuracy, and meets the application needs of non-standard 10MHz frequency frequency standard environments.
Smart Images
Figure CN119210436A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to a rubidium atomic clock frequency source device with a frequency deviation adjustment function. Background Art
[0002] The frequency source device provides a standard reference frequency signal with high frequency accuracy, low phase noise and other performances. The quality of its output signal directly affects the working performance of the frequency-using system (electronic communication, navigation and other equipment). The frequency source device is generally composed of clock tracing, clock synchronization, and frequency mark processing. Clock tracing is used to receive, demodulate and process the standard time information of the time and frequency reference source, mainly including Beidou, GPS, GLONASS and other satellite navigation timing signals; clock synchronization is used to receive external standard time information and maintain high-precision synchronization with it, adjust the clock frequency and phase, so that the internal frequency mark is highly consistent with the external reference, and achieve high frequency accuracy and stability; frequency mark processing is used to distribute, divide, multiply, amplify, filter and other processing of the output frequency mark signal, and output the frequency mark frequency, frequency mark amplitude, frequency mark number of paths and other frequencies that meet the needs of the frequency-using equipment. The existing frequency source device can provide accurate, stable and reliable frequency mark signals for the frequency-using system, but it cannot set the frequency offset of the frequency mark signal, does not have the frequency deviation adjustment function, and cannot meet some non-standard 10MHz frequency mark application environments. Summary of the invention
[0003] Purpose of the invention: The purpose of the present invention is to provide a rubidium atomic clock frequency source device with frequency deviation adjustment function.
[0004] Technical solution: The present invention includes a Beidou antenna, a Beidou receiving processor, a rubidium clock taming and synchronization circuit, a digital frequency deviation adjustment circuit, a frequency output processor, a device management controller and a power signal processor. The Beidou antenna receives the corresponding frequency point signal of the Beidou satellite navigation signal, which is processed by the Beidou receiving processor and input into the rubidium clock taming and synchronization circuit, and the phase and frequency of the rubidium clock are adjusted. Then, the accuracy of the output frequency of the high-stable crystal oscillator inside the frequency deviation circuit is locked to the reference frequency through the digital frequency deviation adjustment circuit. The output frequency of the frequency deviation circuit is accurately adjusted within a certain range through external parameter control, and then output after being processed by the frequency output processor.
[0005] Furthermore, the Beidou antenna adopts a microstrip laminated design and a multi-feed design.
[0006] Furthermore, the Beidou receiving processor converts the A / D signal into a digital signal after down-conversion, amplification and filtering, and then extracts the standard time information after digital signal capture, tracking and data decoding.
[0007] Furthermore, the rubidium clock taming synchronization circuit performs real-time high-precision measurement of the external reference second pulse and the internal second pulse of the rubidium clock, calculates the time difference information, and uses a comprehensive control strategy to adjust the phase and frequency of the rubidium clock to achieve high-precision synchronization with the external reference. After the rubidium clock is synchronized with the external reference, it outputs a 10MHz frequency signal and a 1PPS second pulse time signal.
[0008] Furthermore, the digital frequency deviation adjustment circuit includes a digital frequency difference multiplication amplifier, a frequency deviation controller, a voltage-controlled high-stability constant temperature crystal oscillator and a frequency isolation distributor, and outputs a frequency standard signal within the range of 10MHz±10Hz based on an atomic clock.
[0009] Furthermore, the implementation method of the digital frequency deviation adjustment circuit includes:
[0010] S1: Use dedicated digital frequency difference multiplication amplifier technology to losslessly amplify the frequency difference between the reference frequency and the output frequency, thereby improving the frequency difference measurement accuracy;
[0011] S2: The frequency deviation controller uses a dedicated algorithm to lock the accuracy of the high-stable constant temperature crystal oscillator output frequency inside the module to the reference frequency.
[0012] S3: Receive frequency deviation adjustment data from the external serial port and adjust the output frequency. The frequency adjustment range is limited by the frequency output range of the voltage-controlled crystal oscillator, and the maximum frequency deviation adjustment range is ±10Hz.
[0013] S4: The frequency difference multiplication amplifier is implemented using FPGA, F1 is the reference frequency source frequency, F2 is the frequency of the measured frequency source, Fdif is the beat frequency, Fdif = |F1-F2|, due to the down-conversion effect of mixing on the frequency, the frequency measurement resolution is increased by the beat factor times.
[0014] Furthermore, the frequency output processor outputs multiple 10 MHz frequency standard signals after being processed by a low noise amplifier, a power divider, an isolation amplifier, a filter and a back-check circuit.
[0015] Furthermore, the device management controller monitors, manages and controls all circuits in the device, displays and reports device working status information in real time, receives control instructions such as frequency deviation adjustment, and adjusts the frequency deviation and other working status parameters.
[0016] Furthermore, the power signal processor includes a power reverse connection protection circuit, a surge protection circuit, a filtering processing circuit, a main power conversion circuit and an output rectification circuit. The frequency standard signal is converted by DC / DC to generate +15V, +5V, and +3.3V voltages to power various circuits, and an automatic recovery insurance device is configured internally;
[0017] The input reverse connection protection and surge protection circuit consists of a pair of "back-to-back" N-channel MOS tubes;
[0018] The input filter circuit consists of differential mode inductors, common mode inductors, differential mode capacitors and common mode capacitors:
[0019] The main power conversion circuit is composed of an active clamp control circuit with the third-generation active clamp control chip as the core;
[0020] The output rectifier circuit is composed of a freewheeling inductor, a rectifier diode, a filter capacitor, etc.
[0021] Furthermore, the active clamp control circuit constitutes an active clamp forward circuit, the duty cycle of the active clamp forward circuit exceeds the limit of 50%, and the maximum duty cycle reaches 70%.
[0022] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: it can not only provide accurate, stable and reliable frequency standard signals for the frequency-using system, but also allow the user to set the frequency offset of the frequency standard signal within a certain frequency range, and perform on-site fine-tuning within the range of ±10Hz and 0.001Hz stepping, meeting the application of some non-standard 10MHz frequency standard environments. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 It is a structural schematic diagram of the present invention;
[0024] Figure 2 This is a schematic diagram of the Beidou antenna structure;
[0025] Figure 3 This is a schematic diagram of Beidou receiving and processing;
[0026] Figure 4 Schematic diagram of taming synchronization of rubidium clock;
[0027] Figure 5 This is a schematic diagram of digital frequency deviation adjustment;
[0028] Figure 6 This is a schematic diagram of frequency output processing;
[0029] Figure 7 It is a schematic diagram of device management control;
[0030] Figure 8 This is a schematic diagram of power signal processing. DETAILED DESCRIPTION
[0031] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.
[0032] like Figure 1As shown, the present invention includes a Beidou antenna 1, a Beidou receiving processor 2, a rubidium clock taming synchronization circuit 3, a digital frequency deviation adjustment circuit 4, a frequency output processor 5, a device management controller 6 and a power signal processor 7. The Beidou antenna 1 receives a Beidou satellite navigation signal corresponding to a frequency point signal, which is processed by the Beidou receiving processor 2 and input into the rubidium clock taming synchronization circuit 3, and the rubidium clock is adjusted in phase and frequency. Then, the accuracy of the output frequency of the high-stable crystal oscillator in the frequency deviation circuit 4 is locked to the reference frequency through the digital frequency deviation adjustment circuit 4, and the output frequency of the frequency deviation circuit 4 is accurately adjusted within a certain range through external parameter control, and then output after being processed by the frequency output processor 5.
[0033] like Figure 2 Shown is a schematic diagram of antenna composition.
[0034] Beidou antenna 1 receives the corresponding frequency signals of Beidou satellite navigation signals. It adopts microstrip stacking form to design Beidou B1 and B3 frequency antenna array elements. The mutual influence between antennas of different frequencies in this structure is small and the isolation is good. A multi-feed design is adopted to achieve the coincidence of phase center and geometric center, reducing the influence of antenna on measurement error.
[0035] The satellite signals at each frequency point received by the antenna array elements have a small signal amplitude due to the long distance, so they need to be processed by limiting, filtering and low-noise amplification to suppress out-of-band signals, enhance the useful signal amplitude and signal-to-noise ratio, and improve the satellite signal reception sensitivity, anti-burning, and anti-interference capabilities.
[0036] The received signals of different frequency bands are combined through the antenna combiner circuit, and the feed power signal is extracted and given to the amplifier and other circuits after voltage stabilization. The antenna connects the multi-frequency signals and feed power to the receiver in a one-line manner, requiring only one RF cable for interconnection, simplifying the connection relationship.
[0037] like Figure 3 Shown is a schematic diagram of Beidou reception and processing.
[0038] The signal received by the Beidou antenna is separated and filtered by the Beidou receiving processor 2, and then filtered, amplified, down-converted, etc. by the RF circuit, and then output to the baseband circuit after analog-to-digital conversion.
[0039] The baseband circuit completes the capture, tracking, demodulation and decoding of satellite signals at various Beidou frequencies, extracts original observation information such as pseudorange, carrier phase, carrier Doppler, navigation messages, etc., uses the observation quantity to complete positioning, speed measurement, timing solution, etc. of pseudorange single-point positioning, satellite-based augmented positioning SBAS and other modes, and outputs second pulse timing signals and serial port navigation information.
[0040] The power processing circuit stabilizes and filters the external input power, provides stable, low-noise operating voltage for each active chip, and feeds the external antenna active circuit.
[0041] like Figure 4 Shown is a schematic diagram of rubidium clock taming synchronization.
[0042] The rubidium clock taming synchronization circuit 3 uses 1PPS as the external time reference signal, has an intelligent self-learning function, and stores the drift characteristics of the rubidium clock such as temperature and aging. When the external reference source signal is invalid (interruption or interference failure occurs), it can still output highly accurate time synchronization information and frequency standard signals to achieve high-precision timekeeping.
[0043] By performing real-time high-precision measurement of the external reference second pulse and the internal second pulse of the rubidium clock, calculating the time difference information, and using a comprehensive control strategy to adjust the phase and frequency of the rubidium clock, high-precision synchronization with the external reference is achieved. After the rubidium clock is synchronized with the external reference, it outputs a 10MHz frequency signal and a 1PPS second pulse time signal.
[0044] The digital frequency deviation adjustment circuit 4 is a key circuit part of the invention. Figure 5 Shown is a schematic diagram of digital frequency deviation adjustment.
[0045] The digital frequency deviation adjustment circuit 4 receives an external reference frequency signal and locks the accuracy of the output frequency of the high-stable crystal oscillator inside the frequency deviation circuit to the reference frequency. The output frequency of the frequency deviation circuit can be controlled by external parameters and accurately adjusted within a certain range to output a frequency standard signal within the range of 10MHz±10Hz based on the atomic clock. At the same time, the phase noise performance of the frequency standard output signal is determined by the selected high-stable constant temperature crystal oscillator. A frequency standard signal with excellent long-term frequency stability, short-term frequency stability, and phase noise performance is achieved.
[0046] The digital frequency deviation adjustment circuit is composed of a digital frequency difference multiplication amplifier, a frequency deviation controller, a voltage-controlled high-stability constant temperature crystal oscillator, a frequency isolation distributor, etc.
[0047] The specific implementation method of the digital frequency deviation adjustment circuit is as follows:
[0048] S 1: Use dedicated digital frequency difference multiplication amplifier technology to losslessly amplify the frequency difference between the reference frequency and the output frequency, thereby improving the frequency difference measurement accuracy;
[0049] S2: The frequency deviation controller uses a dedicated algorithm to lock the accuracy of the high-stable constant temperature crystal oscillator output frequency inside the module to the reference frequency.
[0050] S3: Receive frequency deviation adjustment data from the external serial port and adjust the output frequency. The frequency adjustment range is limited by the frequency output range of the voltage-controlled crystal oscillator, and the maximum frequency deviation adjustment range that can be achieved is ±10Hz.
[0051] S4: The frequency difference multiplication amplifier is implemented using FPGA. Compared with traditional analog circuits, it has the advantages of using fewer devices, being easy to integrate and debug. The implementation principle is as follows: F1 is the reference frequency source frequency, F2 is the frequency of the measured frequency source, Fdif is the beat frequency, and Fdif = |F1-F2|. Due to the down-conversion effect of mixing on the frequency, the frequency measurement resolution can be increased by the beat factor. For example, when the nominal value of the measured frequency is 10MHz, the beat method frequency measurement is performed with the reference frequency of 9.9999MHz. The beat signal frequency after mixing is 100Hz. If the counter period measurement accuracy is 1ns, the relative error of the period measurement caused by the counter is: 1ns / 0.01s = 1×10 -7 The beat factor is the measured frequency divided by the beat frequency, which is 1×10 5 Finally, the overall measurement accuracy is 1×10 -7 / 1×10 5 =1×10 -12 .
[0052] like Figure 6 Shown is a schematic diagram of frequency output processing.
[0053] The 10MHz±10Hz frequency standard signal output by the digital frequency deviation adjustment circuit is processed and output after being processed by a low-noise amplifier, a power divider, an isolation amplifier, a filter, a check circuit, a processor, etc. The low-noise amplifier and the power divider realize the function of dividing the frequency standard signal into multiple channels and outputting it with low noise. The filter filters the amplified frequency standard signal separately and outputs it after suppressing the harmonic noise signal of the signal. The processor realizes the check function of the output frequency standard signal.
[0054] At the output port of each frequency standard signal, a signal output feedback detection circuit is designed to directly convert the sinusoidal signal into high and low level signals to indicate the presence or absence of the output signal. The detection result is displayed and reported through the processor.
[0055] like Figure 7 Shown is a schematic diagram of device management control.
[0056] The device management controller 6 monitors, manages and controls all circuits in the device, displays and reports device working status information in real time, receives control instructions such as frequency deviation adjustment, and adjusts frequency deviation and other working status parameters.
[0057] The display screen and buttons are the main local human-computer interaction interfaces of the device, through which the device can be queried and managed. The network port and serial port provide external control and management interfaces for the device. The network port or serial port can be used to monitor and query the device's working status information in real time and configure the working parameters.
[0058] like Figure 8 Shown is a schematic diagram of power supply signal processing.
[0059] The power signal processor 7 completes the external input power reverse connection protection, surge protection, filtering and other processing, and generates +15V, +5V, +3.3V voltages to power various circuits through DC / DC conversion. The internal configuration can automatically restore the insurance device and has output overvoltage, overcurrent protection and other functions.
[0060] The input reverse connection protection and surge protection circuit consists of a pair of "back-to-back" N-channel MOS tubes to prevent the DC input from damaging the power supply and the startup surge current from causing an impact on the input voltage bus.
[0061] The input filter circuit is composed of differential mode inductors, common mode inductors, differential mode capacitors and common mode capacitors. It plays a role in isolating noise and interference. It not only prevents external noise from interfering with the power supply, but also prevents power supply noise from polluting the input voltage bus.
[0062] The main power conversion circuit is composed of an active clamp control circuit with the third-generation active clamp control chip as the core. The active clamp forward circuit formed by it breaks through the limitation that the duty cycle of ordinary forward circuits does not exceed 50%, and the maximum duty cycle reaches 70%. The circuit has soft switching characteristics and has many advantages such as high efficiency and low noise.
[0063] The output rectification and filtering circuit is composed of freewheeling inductor, rectifier diode, filter capacitor, etc. Its main function is to rectify and smooth the high-frequency pulses before output.
Claims
1. A rubidium atomic clock frequency source device with frequency deviation adjustment function, characterized in that: The device comprises a Beidou antenna (1), a Beidou receiving processor (2), a rubidium clock taming synchronization circuit (3), a digital frequency deviation adjustment circuit (4), a frequency output processor (5), a device management controller (6) and a power signal processor (7). The Beidou antenna (1) receives a Beidou satellite navigation signal corresponding to a frequency point signal, which is processed by the Beidou receiving processor (2) and input into the rubidium clock taming synchronization circuit (3), and the rubidium clock is phase and frequency adjusted. Then, the accuracy of the output frequency of a high-stability crystal oscillator inside the frequency deviation circuit (4) is locked to a reference frequency through the digital frequency deviation adjustment circuit (4). The output frequency of the frequency deviation circuit (4) is accurately adjusted within a certain range through external parameter control, and then processed by the frequency output processor (5) and output.
2. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The Beidou antenna (1) adopts a microstrip stacking design and a multi-feed design.
3. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The Beidou receiving processor (2) converts the A / D signal into a digital signal through down-conversion, amplification and filtering, and then extracts the standard time information through digital signal capture, tracking and data decoding.
4. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The rubidium clock taming synchronization circuit (3) performs real-time high-precision measurement of an external reference second pulse and an internal second pulse of the rubidium clock, calculates time difference information, and uses a comprehensive control strategy to adjust the phase and frequency of the rubidium clock to achieve high-precision synchronization with the external reference. After the rubidium clock is synchronized with the external reference, it outputs a 10MHz frequency signal and a 1PPS second pulse time signal.
5. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The digital frequency deviation adjustment circuit (4) comprises a digital frequency difference multiplication amplifier, a frequency deviation controller, a voltage-controlled high-stability constant temperature crystal oscillator and a frequency isolation distributor, and outputs a frequency standard signal within the range of 10 MHz ± 10 Hz based on an atomic clock.
6. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The implementation method of the digital frequency deviation adjustment circuit (4) comprises: S1: Use dedicated digital frequency difference multiplication amplifier technology to losslessly amplify the frequency difference between the reference frequency and the output frequency, thereby improving the frequency difference measurement accuracy; S2: The frequency deviation controller uses a dedicated algorithm to lock the accuracy of the high-stable constant temperature crystal oscillator output frequency inside the module to the reference frequency. S3: Receive frequency deviation adjustment data from the external serial port and adjust the output frequency. The frequency adjustment range is limited by the frequency output range of the voltage-controlled crystal oscillator, and the maximum frequency deviation adjustment range is ±10Hz. S4: The frequency difference multiplication amplifier is implemented using FPGA, F1 is the reference frequency source frequency, F2 is the frequency of the measured frequency source, Fdif is the beat frequency, Fdif = |F1-F2|, due to the down-conversion effect of mixing on the frequency, the frequency measurement resolution is increased by the beat factor times.
7. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The frequency output processor (5) outputs multiple 10 MHz frequency standard signals after being processed by a low noise amplifier, a power divider, an isolation amplifier, a filter and a back-check circuit.
8. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The device management controller (6) monitors, manages and controls all circuits in the device, displays and reports device working status information in real time, receives control instructions such as frequency deviation adjustment, and adjusts the frequency deviation and other working status parameters.
9. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 1, characterized in that: The power signal processor (7) includes a power reverse connection protection circuit, a surge protection circuit, a filtering processing circuit, a main power conversion circuit and an output rectification circuit. The frequency standard signal is converted by DC / DC to generate +15V, +5V and +3.3V voltages to supply power to various circuits. An automatic recovery safety device is configured inside. The input reverse connection protection and surge protection circuit is composed of a pair of "back-to-back" N-channel MOS tubes; The input filter circuit is composed of differential mode inductors, common mode inductors, differential mode capacitors and common mode capacitors; The main power conversion circuit is composed of an active clamp control circuit with the third-generation active clamp control chip as the core; The output rectifier circuit is composed of a freewheeling inductor, a rectifier diode, a filter capacitor, etc.
10. The rubidium atomic clock frequency source device with frequency deviation adjustment function according to claim 9, characterized in that: The active clamp control circuit constitutes an active clamp forward circuit, the duty cycle of the active clamp forward circuit exceeds the limit of 50%, and the maximum duty cycle reaches 70%.