Resistance switching element and manufacturing method thereof

Abstract

The invention discloses a resistance switching element and a manufacturing method thereof. The resistance switching element comprises a substrate; a first dielectric layer disposed on the substrate; a via hole disposed in the first dielectric layer; the bottom electrode is positioned on the via hole and the first dielectric layer; the resistance switching layer is arranged on the bottom electrode; the gap wall covers the side wall of the resistance switching layer and the side wall of the bottom electrode; and a top electrode covering the spacer and the resistance switching layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a resistance switching element and a manufacturing method thereof. Background Art

[0002] Resistive random access memory (RRAM) is a memory structure that includes an array of RRAM cells, each of which uses resistance value rather than charge to store a bit of data. In particular, each RRAM cell includes a layer of resistance-switching material whose resistance can be adjusted to represent a logical "0" or a logical "1".

[0003] At advanced technology nodes, feature sizes are scaled down, and the size of memory elements is scaled accordingly. However, the scaling of RRAM elements is limited due to the "forming" operation, in which high voltage is applied to the RRAM element to generate a conductive path in the resistance-switching material layer. Summary of the invention

[0004] The main purpose of the present invention is to provide an improved resistance switching element and a manufacturing method thereof to solve the deficiencies or shortcomings of the prior art.

[0005] On one hand, the present invention provides a resistance switching element, comprising: a substrate; a first dielectric layer disposed on the substrate; a conductive hole disposed in the first dielectric layer; a bottom electrode located on the conductive hole and the first dielectric layer; a resistance switching layer disposed on the bottom electrode; a spacer covering the sidewalls of the resistance switching layer and the sidewalls of the bottom electrode; and a top electrode covering the spacer and the resistance switching layer.

[0006] According to an embodiment of the present invention, the via comprises tungsten.

[0007] According to an embodiment of the present invention, the bottom electrode includes TaN, TiN, Pt, Ir, Ru or W.

[0008] According to an embodiment of the present invention, the top electrode includes TiN, TaN, Pt, Ir or W.

[0009] According to an embodiment of the present invention, the resistance switching layer includes a hafnium oxide layer and a titanium layer.

[0010] According to an embodiment of the present invention, the top electrode has an inverted U-shaped cross-sectional profile and covers the entire sidewall of the spacer.

[0011] According to an embodiment of the present invention, the spacer has an L-shaped cross-sectional profile.

[0012] According to an embodiment of the present invention, the spacer comprises silicon nitride.

[0013] According to an embodiment of the present invention, the resistance switching element further includes: a second dielectric layer disposed on the top electrode; and a contact penetrating the second dielectric layer and electrically connected to the top electrode.

[0014] According to an embodiment of the present invention, the contact does not directly contact the spacer.

[0015] Another aspect of the present invention provides a method for forming a resistance switching element. First, a substrate is provided; a first dielectric layer is formed on the substrate; a conductive hole is formed in the first dielectric layer; a bottom electrode is formed on the conductive hole and the first dielectric layer; a resistance switching layer is formed on the bottom electrode; a spacer is formed to cover the sidewalls of the resistance switching layer and the sidewalls of the bottom electrode; and a top electrode is formed to cover the spacer and the resistance switching layer.

[0016] According to an embodiment of the present invention, the via comprises tungsten.

[0017] According to an embodiment of the present invention, the bottom electrode includes TaN, TiN, Pt, Ir, Ru or W.

[0018] According to an embodiment of the present invention, the top electrode includes TiN, TaN, Pt, Ir or W.

[0019] According to an embodiment of the present invention, the resistance switching layer includes a hafnium oxide layer and a titanium layer.

[0020] According to an embodiment of the present invention, the top electrode has an inverted U-shaped cross-sectional profile and covers the entire sidewall of the spacer.

[0021] According to an embodiment of the present invention, the spacer has an L-shaped cross-sectional profile.

[0022] According to an embodiment of the present invention, the spacer comprises silicon nitride.

[0023] According to an embodiment of the present invention, the method further includes: forming a second dielectric layer on the top electrode; and forming a contact penetrating the second dielectric layer and electrically connecting the top electrode.

[0024] According to an embodiment of the present invention, the contact does not directly contact the spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A cross-sectional schematic diagram of a resistance switching element according to an embodiment of the present invention;

[0026] Figures 2 to 7 is a schematic diagram of a method for forming a resistance switching element;

[0027] Figure 8 The diagram is a schematic diagram of an internal connection structure in a logic circuit area and a resistance switching element in a memory area.

[0028] Explanation of symbols

[0029] 1Resistor switching element

[0030] 100 base

[0031] 110 first dielectric layer

[0032] 112 vias

[0033] 120 second dielectric layer

[0034] 210 bottom electrode

[0035] 220 resistor switching layer

[0036] 221Hafnium oxide layer

[0037] 222 Titanium layer

[0038] 230 spacer layer

[0039] 240 gap wall

[0040] 240a horizontal section

[0041] 250 top electrode layer

[0042] 260 Top Electrode

[0043] 260a horizontal section

[0044] 280 Contacts

[0045] 300 internal connection structure

[0046] LR logic circuit area

[0047] MR memory area

[0048] M3 third metal layer

[0049] V2 via

[0050] PR photoresist pattern DETAILED DESCRIPTION

[0051] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0052] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0053] See also Figure 1 , which is a cross-sectional schematic diagram of a resistance switching element according to an embodiment of the present invention. Figure 1 As shown, the resistance switching element 1, for example, a resistance random access memory element, includes a substrate 100 and a first dielectric layer 110 and a second dielectric layer 120 formed on the substrate 100. According to an embodiment of the present invention, the substrate 100 may be a silicon substrate, but is not limited thereto. In order to simplify the description, various circuit structures formed in the substrate 100, such as transistors, insulation structures, metal interconnects, etc., are not shown. Figure 1 According to an embodiment of the present invention, the first dielectric layer 110 may include a silicon oxide layer, such as a TEOS silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, for example, the second dielectric layer 120 may include a low dielectric constant material, but is not limited thereto.

[0054] According to an embodiment of the present invention, a via hole 112 is formed in the first dielectric layer 110. According to an embodiment of the present invention, the via hole 112 may contain tungsten, but is not limited thereto. According to an embodiment of the present invention, the via hole 112 may be a tungsten via. A bottom electrode 210 and a resistance switching layer 220 are formed on the via hole 112 and the first dielectric layer 110. According to an embodiment of the present invention, the bottom electrode 210 may contain TaN, TiN, Pt, Ir, Ru or W. According to an embodiment of the present invention, for example, the resistance switching layer 220 may include a hafnium oxide (HfO2) layer 221 and a titanium (Ti) layer 222, but is not limited thereto.

[0055] According to an embodiment of the present invention, the resistance switching element 1 further includes a spacer 240, covering the sidewalls of the resistance switching layer 220 and the sidewalls of the bottom electrode 210. According to an embodiment of the present invention, the sidewalls of the resistance switching layer 220 and the sidewalls of the bottom electrode 210 may be continuously inclined sidewalls. According to an embodiment of the present invention, the spacer 240 includes silicon nitride, but is not limited thereto. According to an embodiment of the present invention, the spacer 240 does not extend to the top surface of the resistance switching layer 220. According to an embodiment of the present invention, the spacer 240 may have a horizontal section 240a extending to the top surface of the first dielectric layer 110. According to an embodiment of the present invention, the spacer 240 has an L-shaped cross-sectional profile.

[0056] According to an embodiment of the present invention, the resistance switching element 1 further includes a top electrode 260, covering the spacer 240 and the resistance switching layer 220. According to an embodiment of the present invention, the top electrode 260 directly contacts the resistance switching layer 220. According to an embodiment of the present invention, the top electrode 260 may include TiN, TaN, Pt, Ir or W, but is not limited thereto. For example, the top electrode 260 may be TiN. According to an embodiment of the present invention, the top electrode 260 has an inverted U-shaped cross-sectional profile and covers the entire sidewall of the spacer 240. According to an embodiment of the present invention, the top electrode 260 may have a horizontal section 260a disposed on the horizontal section 240a of the spacer 240. According to an embodiment of the present invention, the second dielectric layer 120 surrounds and covers the top electrode 260.

[0057] According to an embodiment of the present invention, the resistance switching element 1 further includes a contact 280, for example, a copper contact, penetrating the second dielectric layer 120 and electrically connected to the top electrode 260. According to an embodiment of the present invention, the contact 280 is not in direct contact with the spacer 240. According to an embodiment of the present invention, the contact 280 may have an inverted U-shaped cross-sectional profile and cover the top surface and a portion of the sidewall of the top electrode 260.

[0058] See also Figures 2 to 7 Another aspect of the present invention provides a method for forming a resistance switching element. Figure 2 As shown, a substrate 100 is first provided, for example, a silicon substrate. A first dielectric layer 110, for example, a silicon oxide layer, is formed on the substrate 100 by a chemical vapor deposition (CVD) process. A via hole 112 is then formed in the first dielectric layer 110. According to an embodiment of the present invention, the via hole 112 may include tungsten, but is not limited thereto. According to an embodiment of the present invention, the via hole 112 may be a tungsten via. A planarization process, for example, a chemical mechanical polishing (CMP) process, may be used to make the top surface of the via hole 112 flush with the top surface of the first dielectric layer 110.

[0059] Next, a deposition process, a photolithography process, and an etching process are performed to form a patterned bottom electrode 210 and a resistance switching layer 220 on the conductive hole 112 and the first dielectric layer 110. According to an embodiment of the present invention, the bottom electrode 210 may include TaN, TiN, Pt, Ir, Ru, or W. According to an embodiment of the present invention, for example, the resistance switching layer 220 may include a hafnium oxide (HfO2) layer 221 and a titanium (Ti) layer 222, but is not limited thereto.

[0060] like Figure 3 As shown, a deposition process is performed to form a spacer layer 230 by deposition on the substrate 100. According to an embodiment of the present invention, the spacer 240 may include a silicon nitride layer, but is not limited thereto.

[0061] like Figure 4As shown, an etching process, for example, a plasma dry etching process, is performed to remove the spacer layer 230 above the resistance switching layer 220, and form a spacer 240 covering the sidewalls of the resistance switching layer 220 and the sidewalls of the bottom electrode 210. According to an embodiment of the present invention, the spacer 240 has an L-shaped cross-sectional profile. At this time, the titanium layer 222 of the resistance switching layer 220 is exposed.

[0062] like Figure 5 As shown, a deposition process is then performed to form a top electrode layer 250 on the spacer 240 and the resistance switching layer 220. According to an embodiment of the present invention, the top electrode layer 250 may include TiN, TaN, Pt, Ir or W, but is not limited thereto. For example, the top electrode layer 250 may be TiN.

[0063] like Figure 6 As shown, a photolithography and etching process is performed, a top electrode pattern is defined using a photoresist pattern PR, and a plasma dry etching process is used to etch away the top electrode layer 250 not covered by the photoresist pattern PR, thereby forming a top electrode 260. According to an embodiment of the present invention, the top electrode 260 has an inverted U-shaped cross-sectional profile and covers the entire sidewall of the spacer 240. Subsequently, the photoresist pattern PR is removed.

[0064] like Figure 7 As shown, a second dielectric layer 120 is formed on the top electrode 260 and the first dielectric layer 110. According to an embodiment of the present invention, for example, the second dielectric layer 120 may include a low dielectric constant material, but is not limited thereto. A photolithography process, an etching process, and a metallization process are then performed to form a contact 280 in the second dielectric layer 120, so that the contact 280 is electrically connected to the top electrode 260. According to an embodiment of the present invention, the contact 280 does not directly contact the spacer 240.

[0065] Since the resistance switching layer 220 and the spacer 240 are covered by the top electrode 260 during the process of forming the contact 280 , the resistance switching layer 220 can be protected from being affected by the etching process, thereby improving the process margin for forming the contact 280 and the reliability of the resistance switching element 1 .

[0066] Figure 8 The example shows the interconnect structure in the logic circuit area and the resistance switching element 1 in the memory area. Figure 8 As shown, the substrate 100 includes a logic circuit region LR and a memory region MR, wherein the logic circuit region LR shows an internal connection structure 300, for example, a copper dual damascene structure. For example, the internal connection structure 300 includes a third metal layer M3 and a via V2 connecting the lower metal layer. The contact 280 of the resistance switching element 1 and the third metal layer M3 are both trench structures and are formed at the same time.

[0067] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A resistance switching element, comprising: substrate; A first dielectric layer is disposed on the substrate; A via hole is provided in the first dielectric layer; A bottom electrode, located on the via hole and the first dielectric layer; a resistance switching layer, disposed on the bottom electrode; A spacer covering a sidewall of the resistance switching layer and a sidewall of the bottom electrode; as well as A top electrode covers the spacer and the resistance switching layer.

2. The resistance switching element according to claim 1, wherein: The via contains tungsten.

3. The resistance switching element according to claim 1, wherein: The bottom electrode includes TaN, TiN, Pt, Ir, Ru or W.

4. The resistance switching element according to claim 1, wherein: The top electrode includes TiN, TaN, Pt, Ir or W.

5. The resistance switching element according to claim 1, wherein: The resistance switching layer includes a hafnium oxide layer and a titanium layer.

6. The resistance switching element according to claim 1, wherein: The top electrode has an inverted U-shaped cross-sectional profile and covers the entire sidewall of the spacer.

7. The resistance switching element according to claim 1, wherein: The spacer has an L-shaped cross-sectional profile.

8. The resistance switching element according to claim 1, wherein: The spacer comprises silicon nitride.

9. The resistance switching element according to claim 1, wherein: Also includes: A second dielectric layer is disposed on the top electrode; and A contact penetrates the second dielectric layer and is electrically connected to the top electrode.

10. The resistance switching element according to claim 9, wherein: The contact is not in direct contact with the spacer.

11. A method for forming a resistance switching element, comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a via hole in the first dielectric layer; forming a bottom electrode on the conductive hole and the first dielectric layer; forming a resistance switching layer on the bottom electrode; forming a spacer to cover the sidewall of the resistance switching layer and the sidewall of the bottom electrode; as well as A top electrode is formed to cover the spacer and the resistance switching layer.

12. The forming method according to claim 11, wherein: The via contains tungsten.

13. The forming method according to claim 11, wherein: The bottom electrode includes TaN, TiN, Pt, Ir, Ru or W.

14. The forming method according to claim 11, wherein: The top electrode includes TiN, TaN, Pt, Ir or W.

15. The forming method according to claim 11, wherein: The resistance switching layer includes a hafnium oxide layer and a titanium layer.

16. The forming method according to claim 11, wherein: The top electrode has an inverted U-shaped cross-sectional profile and covers the entire sidewall of the spacer.

17. The forming method according to claim 11, wherein: The spacer has an L-shaped cross-sectional profile.

18. The forming method according to claim 11, wherein: The spacer comprises silicon nitride.

19. The forming method according to claim 11, wherein: Also includes: forming a second dielectric layer on the top electrode; and A contact is formed through the second dielectric layer and electrically connected to the top electrode.

20. The forming method according to claim 19, wherein: The contact is not in direct contact with the spacer.

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