Display substrate, display panel and display device

Abstract

The invention provides a display substrate, a display panel and a display device. The display substrate is provided with a display area and a peripheral area. The display substrate comprises a test structure, a transmission wire and a driving circuit. The testing structure comprises an electrical testing structure and a first connecting part; the electrical test structure is arranged on one side, far away from the display area, of the transmission wire; the electrical test structure is used for transmitting an electrical test signal to the drive circuit; the driving circuit is used for providing a driving signal; the transmission wire is a signal transmission wire between a driving integrated circuit and the driving circuit; the electrical test structure is electrically connected with the transmission wire through the first connecting part; and the transmission wire and the first connecting part are located in different conductive layers. The driving circuit in the display panel can be protected.

Description

Display substrate, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a display panel, and a display device. Background Art

[0002] In the related art, the preparation of a display panel includes an array substrate process, a color film substrate process, and an array substrate and color film substrate alignment process. After the array substrate and the color film substrate are aligned, a whole film substrate is cut into individual panels. The cut individual panels enter the electrical test (ET) process. The ET test process loads the test electrical signal into the individual panels through the test pads on the array substrate to perform defect detection on the individual panels. After the ET test process, defective products are eliminated and good products are processed to form a display panel. In the display panel, one end of the test pad is connected to the driver integrated circuit in the FPC (flexible circuit board), and the other end is connected to the GOA (Gate On Array, array substrate row drive) circuit inside the display panel, which plays the role of transmitting the drive signal.

[0003] Because the GOA circuit is manufactured on a substrate using an array process, in actual layout, long metal traces are inevitably present in the transmission path of the drive signal. Furthermore, the test pads are large in area and easily accumulate charge. When static electricity occurs, it can directly enter the display panel through the test pads, burning components of the drive circuit inside the display panel and causing abnormal display on the display panel.

[0004] Summary of the Invention

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate having a display area and a peripheral area, wherein the display substrate includes a test structure, a transmission line, and a driving circuit; the test structure includes an electrical test structure and a first connection portion;

[0006] The electrical test structure is arranged on a side of the transmission line away from the display area; the electrical test structure is used to transmit an electrical test signal to the driving circuit; the driving circuit is used to provide a driving signal;

[0007] The transmission line is a signal transmission line between the driver integrated circuit and the driver circuit; the electrical test structure is electrically connected to the transmission line through the first connection portion;

[0008] The transmission line and the first connection portion are located in different conductive layers.

[0009] Optionally, the resistivity of the first connection portion is greater than the resistivity of the transmission line.

[0010] Optionally, the electrical test structure includes a test transistor; the test transistor includes a gate, a first electrode and a second electrode; the gate is electrically connected to the first electrode, and the second electrode is electrically connected to the transmission line through the first connecting portion.

[0011] Optionally, the transmission line is a single-layer line, and the first connection portion is a single-layer connection portion. Optionally, the electrical test structure includes a test pad;

[0012] The test pad is electrically connected to the first connection portion. Optionally, the test structure further includes a first electrostatic release structure;

[0013] The first connecting portion is electrically connected to the test pad via the first electrostatic release structure;

[0014] The first electrostatic discharge structure includes a plurality of first via holes.

[0015] Optionally, the test structure further includes a second electrostatic release structure;

[0016] The first connection portion is electrically connected to the transmission line through the second electrostatic release structure;

[0017] The second electrostatic discharge structure includes a plurality of second via holes.

[0018] Optionally, the first connection portion is electrically connected to the test pad through a first via hole, and the first connection portion is electrically connected to the transmission trace through a second via hole;

[0019] The aperture of the first via hole is smaller than the aperture of the second via hole.

[0020] Optionally, a ratio of the aperture of the first via hole to the aperture of the second via hole is greater than or equal to 1 / 1.8 and less than or equal to 1 / 1.2.

[0021] Optionally, the electrical test structure further includes a test pad; the gate of the test transistor and the test pad are an integrated structure; and the test transistor is used to transmit an electrical test signal to the transmission line.

[0022] Optionally, the electrical test structure further includes a test pad; the test pad is used to transmit an electrical test signal to the test transistor; the gate of the test transistor and the test pad are separate structures;

[0023] The first electrode is electrically connected to the test pad.

[0024] Optionally, the resistivity of the first connection portion is greater than the resistivity of the transmission line; the test structure further includes a third electrostatic release structure;

[0025] The first connecting portion is electrically connected to the second electrode via the third electrostatic release structure;

[0026] The third electrostatic discharge structure includes a plurality of third via holes.

[0027] Optionally, the test structure further includes a fourth electrostatic release structure;

[0028] The first connection portion is electrically connected to the transmission line through the fourth electrostatic release structure;

[0029] The fourth electrostatic discharge structure includes a plurality of fourth via holes.

[0030] Optionally, the resistivity of the first connection portion is greater than the resistivity of the transmission line, the first connection portion is electrically connected to the second electrode through a third via hole, and the first connection portion is electrically connected to the transmission line through a fourth via hole;

[0031] The aperture of the third via hole is smaller than the aperture of the fourth via hole.

[0032] Optionally, a ratio of the aperture of the third via hole to the aperture of the fourth via hole is greater than or equal to 1 / 1.8 and less than or equal to 1 / 1.2.

[0033] Optionally, the thickness of the first connecting portion is smaller than the thickness of the transmission line.

[0034] Optionally, the first connecting portion is located in a first conductive layer, and the first conductive layer is made of ITO.

[0035] Optionally, the test transistor is an oxide transistor, and a width-to-length ratio of the test transistor is less than or equal to 2.

[0036] Optionally, the test transistor is an amorphous silicon transistor, and a width-to-length ratio of the test transistor is less than or equal to 100 / 3.6.

[0037] Optionally, the test pad and the transmission line are located in the same conductive layer, and the transmission line and the first connecting portion are located in different conductive layers.

[0038] Optionally, the first connecting portion, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, and the first connecting portion and the transmission line are located in different conductive layers.

[0039] Optionally, the first electrode and the second electrode are located in the same conductive layer;

[0040] The first electrode includes a first main portion and at least one first extension portion electrically connected to each other, and the second electrode includes a second main portion and at least one second extension portion;

[0041] The first main body portion and the second main body portion both extend along a first direction, and the first extension portion and the second extension portion both extend along a second direction;

[0042] The first direction intersects the second direction.

[0043] Optionally, the first electrode includes at least two first extension portions, and the at least two first extension portions are arranged along a first direction;

[0044] The second electrode includes at least two second extensions, and the at least two second extensions are arranged along the first direction;

[0045] At least a portion of at least one of the second extension portions is disposed between two adjacent first extension portions.

[0046] Optionally, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, the first connecting portion and the first electrode are located in different conductive layers, and the first connecting portion and the transmission line are located in different conductive layers.

[0047] Optionally, the test pad, the first electrode, the second electrode and the first connecting portion are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, and the first connecting portion and the transmission line are located in different conductive layers.

[0048] Optionally, the test pad, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, the first connecting portion and the test pad are located in different conductive layers, and the first connecting portion and the transmission line are located in different conductive layers.

[0049] In a second aspect, an embodiment of the present disclosure provides a display panel, comprising a driver integrated circuit and the above-mentioned display substrate;

[0050] The driving integrated circuit is used to provide a signal to the driving circuit.

[0051] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] 1A and 1B are structural diagrams of a display substrate according to at least one embodiment of the present disclosure;

[0053] FIG2 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0054] FIG3 is a layout diagram of the first metal layer in FIG1A ;

[0055] FIG4 is a layout diagram of the first conductive layer in FIG1A ;

[0056] FIG5 is a cross-sectional view of AA' in FIG1A;

[0057] FIG6 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0058] FIG7 is a layout diagram of the first metal layer in FIG6;

[0059] 8A and 8B are layout diagrams of the second metal layer in FIG. 6 ;

[0060] FIG9 is a layout diagram of the semiconductor layer in FIG6;

[0061] FIG10 is a layout diagram of the first conductive layer in FIG6;

[0062] FIG11 is a waveform diagram of a first noise reduction voltage signal VDDO and a second noise reduction voltage signal VDDE;

[0063] FIG12 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0064] FIG13 is a layout diagram of the first metal layer in FIG12;

[0065] FIG14 is a layout diagram of the source-drain electrode layer in FIG12;

[0066] FIG15 is a layout diagram of the semiconductor layer in FIG12;

[0067] FIG16 is a layout diagram of the first conductive layer in FIG12;

[0068] 17A and 17B are structural diagrams of a display substrate according to at least one embodiment of the present disclosure;

[0069] FIG18 is a layout diagram of the first metal layer in FIG17A;

[0070] FIG19 is a layout diagram of the source-drain electrode layer in FIG17A;

[0071] FIG20 is a layout diagram of the semiconductor layer in FIG17A;

[0072] FIG21 is a layout diagram of the first conductive layer in FIG17A;

[0073] FIG22 is a BB' cross-sectional view in FIG17A;

[0074] FIG23 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure;

[0075] FIG24 is a layout diagram of the first metal layer in FIG23;

[0076] 25A and 25B are layout diagrams of the second metal layer in FIG. 23 ;

[0077] FIG26 is a layout diagram of the semiconductor layer in FIG23;

[0078] FIG27 is a layout diagram of the first conductive layer in FIG23;

[0079] FIG. 28 is a schematic diagram of a test structure included in a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0081] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0082] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0083] The display substrate of the embodiment of the present disclosure has a display area and a peripheral area; the display substrate includes a test structure, a transmission line and a driving circuit; the test structure includes an electrical test structure and a first connection portion;

[0084] The electrical test structure is arranged on a side of the transmission line away from the display area; the electrical test structure is used to transmit an electrical test signal to the driving circuit; the driving circuit is used to provide a driving signal;

[0085] The transmission line is a signal transmission line between the driver integrated circuit and the driver circuit; the electrical test structure is electrically connected to the transmission line through the first connection portion;

[0086] The transmission line and the first connection portion are located in different conductive layers.

[0087] The embodiments of the present disclosure provide a test structure that can prevent ESD (Electro-Static discharge). Without adding additional development costs and processes, the electrical test structure can be set on the side of the transmission line away from the display area, which can ensure normal electrical testing and realize electrostatic protection function.

[0088] Optionally, the resistivity of the first connection portion may be greater than the resistivity of the transmission trace. In at least one embodiment of the present disclosure, the electrical test structure may be electrically connected to the transmission trace via the first connection portion, and the resistivity of the first connection portion may be greater than the resistivity of the transmission trace, so that when ESD (electro-static discharge) passes through, the first connection portion is burned out, thereby protecting the driving circuit inside the display panel.

[0089] Optionally, the electrical test structure may include a test transistor; the test transistor includes a gate, a first electrode, and a second electrode; the gate is electrically connected to the first electrode, and the second electrode is electrically connected to the transmission line through the first connecting portion.

[0090] In a specific implementation, the electrical test structure may include a diode-connected test transistor, and the second electrode of the test transistor is electrically connected to the transmission line through the first connection part. The characteristic that the diode-connected test transistor is easily burned during ESD impact can be utilized to protect the driving circuit inside the display panel.

[0091] In at least one embodiment of the present disclosure, the driving circuit may be a GOA (Gate On Array, a gate driving circuit provided on an array substrate) circuit, configured to provide a driving signal for a pixel circuit included in a display substrate.

[0092] In at least one embodiment of the present disclosure, the transmission line may be a single-layer line, and the first connection portion may be a single-layer connection portion.

[0093] In a specific implementation, all parts of the transmission line may be located in the same conductive layer, and all parts of the first connection portion may be located in the same conductive layer, so as to simplify the structure.

[0094] In at least one embodiment of the present disclosure, the electrical test structure includes a test pad;

[0095] The resistivity of the first connection portion is greater than the resistivity of the transmission line, and the test pad is electrically connected to the first connection portion.

[0096] In a specific implementation, the electrical test structure may include a test pad, the resistivity of the first connection portion is greater than the resistivity of the transmission line, and the test pad is electrically connected to the first connection portion.

[0097] In at least one embodiment of the present disclosure, the test structure may further include a first electrostatic release structure;

[0098] The first connecting portion is electrically connected to the test pad via the first electrostatic release structure;

[0099] The first electrostatic discharge structure may include a plurality of first via holes.

[0100] In a specific implementation, the first connection portion can be electrically connected to the test pad through a plurality of first vias included in the first electrostatic release structure. By using a plurality of first vias, electrostatic protection can be better performed compared to using a single first via.

[0101] Optionally, the test structure may further include a second electrostatic release structure;

[0102] The first connection portion is electrically connected to the transmission line through the second electrostatic release structure;

[0103] The second electrostatic discharge structure includes a plurality of second via holes.

[0104] In a specific implementation, the first connection portion can be electrically connected to the transmission line through a plurality of second vias included in the second electrostatic release structure. By using a plurality of second vias, electrostatic protection can be better performed compared to using a single second via.

[0105] In at least one embodiment of the present disclosure, the first connection portion is electrically connected to the test pad through a first via hole, and the first connection portion is electrically connected to the transmission trace through a second via hole;

[0106] The aperture of the first via hole is smaller than the aperture of the second via hole.

[0107] In a specific implementation, the aperture of the first via hole close to the test pad can be set to be smaller than the aperture of the second via hole. The smaller the aperture, the greater the resistance. When a large current passes through, the first via hole will burn out first, thereby preventing ESD from entering the display panel when ESD occurs, thereby playing an ESD protection role.

[0108] Optionally, a ratio of the aperture of the first via hole to the aperture of the second via hole is greater than or equal to 1 / 1.8 and less than or equal to 1 / 1.2.

[0109] Optionally, the first via hole may be greater than or equal to 5 μm and less than or equal to 15 μm, and the second via hole may be greater than or equal to 15 μm and less than or equal to 40 μm, but the present invention is not limited thereto.

[0110] Optionally, the first connecting portion is located in a first conductive layer, and the first conductive layer is made of ITO.

[0111] In at least one embodiment of the present disclosure, the thickness of the first connection portion is smaller than the thickness of the transmission line, so that when ESD occurs, the first connection portion is burned first.

[0112] As shown in FIG1A , in the display substrate according to at least one embodiment of the present disclosure, the test structure includes an electrical test structure and a first first connection portion L11 and a second first connection portion L21 ; the electrical test structure includes a first test pad 101 and a second test pad 102 ;

[0113] In FIG1A , the first transmission line is labeled X1, and the second transmission line is labeled X2;

[0114] The first test pad 101 is arranged on a side of the first transmission line X1 and the second transmission line X2 away from the display area; the second test pad 102 is arranged on a side of the first transmission line X1 and the second transmission line X2 away from the display area; the first test pad 101 and the second test pad 102 are used to transmit electrical test signals to the driving circuit;

[0115] The first test pad 101 is electrically connected to the first first connection portion L11 through the first first via H11, and the first first connection portion L11 is electrically connected to the first transmission line X1 through the first second via H12;

[0116] The second test pad 102 is electrically connected to the second first connection portion L21 through the second first via H21, and the second first connection portion L21 is electrically connected to the second transmission line X2 through the second second via H22;

[0117] The resistivity of the first first connection portion L11 is greater than the resistivity of the first transmission line X1; the resistivity of the second first connection portion L21 is greater than the resistivity of the second transmission line X2;

[0118] The first transmission line X1 and the second transmission line X2 are signal transmission lines between the driver integrated circuit and the driver circuit.

[0119] In at least one embodiment of the present disclosure, the resistance of L11 may be greater than the resistance of X1 , and the resistance of L21 may be greater than the resistance of X2 .

[0120] In FIG1B , the first electrostatic release structure is labeled JS11 , the second electrostatic release structure is labeled JS21 , the first electrostatic release structure is labeled JS12 , and the second electrostatic release structure is labeled JS22 .

[0121] The first first electrostatic release structure JS11 includes six first via holes, and the second first electrostatic release structure JS21 includes six first via holes;

[0122] The first second electrostatic discharge structure JS12 includes six second via holes, and the second second electrostatic discharge structure JS22 includes six second via holes.

[0123] In at least one embodiment shown in FIG. 1A to FIG. 5 , each first electrostatic discharge structure includes six first vias, and each second electrostatic discharge structure includes six second vias, so that electrostatic protection can be improved by increasing the number of vias.

[0124] In at least one embodiment shown in FIG. 1A to FIG. 5 , the first transmission trace X1, the second transmission trace X2, the first test pad 101, and the second test pad 102 are all located in the first metal layer, and the first first connection portion L11 and the second first connection portion L21 are both located in the first conductive layer. The first metal layer and the first conductive layer are separated by a first insulating layer, and the first insulating layer has holes so that the first conductive layer overlaps the first metal layer to achieve electrical connection between the test pad and the transmission trace.

[0125] The first conductive layer may be an ITO (indium tin oxide) layer, and the first metal layer may be a gate electrode layer, but is not limited thereto.

[0126] In at least one embodiment shown in FIG. 1A to FIG. 5 , the thickness of the first first connection portion L11 is smaller than the thickness of the first transmission trace X1 , and the thickness of the second first connection portion L21 is smaller than the thickness of the second transmission trace X2 .

[0127] In at least one embodiment of the present disclosure, the thickness of the ITO layer may be greater than or equal to 600 angstroms and less than or equal to 1500 angstroms, and the thickness of the gate electrode layer may be greater than or equal to 2500 angstroms and less than or equal to 4000 angstroms, but are not limited thereto.

[0128] As shown in FIG1A , the aperture of the first via hole H11 is smaller than the aperture of the first second via hole H12 , and the aperture of the second first via hole H21 is smaller than the aperture of the second second via hole H22 .

[0129] In at least one embodiment shown in FIG. 1A to FIG. 5 , the first test pad 101 is electrically connected to the first first conductive structure J11 located in the first conductive layer through a first first connection via H011, and the second test pad 102 is electrically connected to the second first conductive structure J21 located in the first conductive layer through a second first connection via H021;

[0130] When performing electrical testing, the electrical test signal can be transmitted to the first test pad 101 through the first first conductive structure J11 and the first first connection via H011 by a probe, and then transmitted to the driving circuit, and the electrical test signal can be transmitted to the second test pad 102 through the second first conductive structure J21 and the second first connection via H021 by a probe, and then transmitted to the driving circuit.

[0131] Optionally, the aperture of the first first connection via H01 may be greater than or equal to 30 μm and less than or equal to 80 μm, and the aperture of the second first connection via H021 may be greater than or equal to 30 μm and less than or equal to 80 μm. For example, the aperture of the first first connection via H011 may be 40 μm, and the aperture of the second first connection via H021 may be 40 μm.

[0132] In at least one embodiment shown in Figures 1A to 5, when ESD occurs, ESD first passes through the first first via H11 and the second first via H21. The first first via H11, the second first via H21, the first first connection portion L11 and the second first connection portion L21 are burned first, preventing ESD from entering the interior of the display panel, thereby playing a role in electrostatic protection.

[0133] As shown in FIG2 , based on at least one embodiment shown in FIG1A , a driving circuit 21 and a driving integrated circuit 22 are additionally provided;

[0134] The first transmission line X1 and the second transmission line X2 are signal transmission lines between the driver integrated circuit 22 and the driver circuit 21 .

[0135] 3 is a layout diagram of the first metal layer in FIG. 1A , FIG. 4 is a layout diagram of the first conductive layer in FIG. 1A , and FIG. 5 is a cross-sectional view taken along line AA′ in FIG. 1A .

[0136] In FIG5 , the reference numeral 50 is a substrate, the reference numeral 51 is a first metal layer, the reference numeral 52 is a first conductive layer, and the reference numeral 501 is a first insulating layer.

[0137] In at least one embodiment of the present disclosure, the electrical test structure includes a test transistor; the electrical test structure further includes a test pad;

[0138] The gate of the test transistor and the test pad are an integrated structure;

[0139] The test transistor is used to transmit an electrical test signal to the transmission line.

[0140] Optionally, when the electrical test structure includes a test transistor,

[0141] The test transistor is an oxide transistor, and the width-to-length ratio of the test transistor is less than or equal to 2; or

[0142] The test transistor is an amorphous silicon transistor, and a width-to-length ratio of the test transistor is less than or equal to 100 / 3.6.

[0143] In a specific implementation, the aspect ratio of the test transistor may be comparable to or smaller than the aspect ratio of the TFT (thin film transistor) with the smallest aspect ratio in the GOA circuit, and the specific size is set according to the design of the GOA circuit.

[0144] As shown in Figures 6 to 10, in the display substrate according to at least one embodiment of the present disclosure, the test structure includes a first transmission trace X1, a second transmission trace X2, an electrical test structure, a first first connection portion L11, and a second first connection portion L21; the electrical test structure includes a first test transistor M1 and a second test transistor M2; the first test transistor M1 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area, and the second test transistor M2 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area;

[0145] The first transmission line X1 and the second transmission line X2 are signal transmission lines between the driver integrated circuit and the driver circuit;

[0146] The first test transistor M1 includes a gate, a first electrode, and a second electrode; the gate of the first test transistor M1 is electrically connected to the first electrode S1 of the first test transistor M1, and the second electrode D1 of the first test transistor M1 is electrically connected to the first transmission line X1 through the first first connection portion L11;

[0147] The second test transistor M2 includes a gate, a first electrode, and a second electrode; the gate of the second test transistor M2 is electrically connected to the first electrode S2 of the second test transistor M2, and the second electrode D2 of the second test transistor M2 is electrically connected to the second transmission line X2 through the second first connection portion L21;

[0148] As shown in FIG7 , the gate of the first test transistor M1 and the first test pad 101 are an integrated structure, and the gate of the second test transistor M2 and the second test pad 102 are an integrated structure;

[0149] The first test transistor M1 is used to transmit an electrical test signal to the first transmission line X1 , and the second test transistor M2 is used to transmit an electrical test signal to the second transmission line X2 .

[0150] In FIG8A , S1 is the first electrode of M1 , and D1 is the second electrode of M1 ; S2 is the first electrode of M2 , and D2 is the second electrode of M2 .

[0151] In at least one embodiment shown in FIG6-FIG10 , the first transmission trace X1, the second transmission trace X2, the first test pad 101, and the second test pad 102 are all located in the first metal layer, the first electrode S1 of the first test transistor M1, the second electrode D1 of the first test transistor M1, the first electrode S2 of the second test transistor M2, and the second electrode D2 of the second test transistor M2 are all located in the second metal layer, and the first first connection portion L11 and the second first connection portion L21 are located in the second metal layer;

[0152] The first metal layer may be a gate electrode layer, and the second metal layer may be a source / drain electrode layer, but the present invention is not limited thereto.

[0153] 7 is a layout diagram of the first metal layer in FIG. 6 , FIG. 8A and FIG. 8B are layout diagrams of the second metal layer in FIG. 6 , FIG. 9 is a layout diagram of the semiconductor layer in FIG. 6 , and FIG. 10 is a layout diagram of the first conductive layer in FIG. 6 .

[0154] In FIG. 9 , the active pattern labeled A1 is M1 , and the active pattern labeled A2 is M2 .

[0155] As shown in FIG6-FIG10, the first first connection portion L11 is electrically connected to the first transmission trace X1 through the first fifth via H15; the second first connection portion L21 is electrically connected to the second transmission trace X2 through the second fifth via H25;

[0156] The first test pad 101 is electrically connected to the first electrode S1 of the first test transistor M1 and the first first conductive structure J11 located in the first conductive layer through a first second connection via H012; the second test pad 102 is electrically connected to the first electrode S2 of the second test transistor M2 and the second first conductive structure J21 located in the first conductive layer through a second second connection via H022.

[0157] The aperture of the first second connection via H012 may be greater than or equal to 30 μm and less than or equal to 80 μm, and the aperture of the second second connection via H022 may be greater than or equal to 30 μm and less than or equal to 80 μm. For example, the aperture of the first second connection via H012 may be 40 μm, and the aperture of the second second connection via H022 may be 40 μm.

[0158] In at least one embodiment shown in FIG. 6 , the first test transistor M1 and the second test transistor M2 may be n-type transistors, but the present invention is not limited thereto.

[0159] In at least one embodiment shown in FIG. 6 , the electrical test structure includes a diode-connected first test transistor M1 and a diode-connected second test transistor M2. The gate of the first test transistor M1 is reused as a first test pad 101, and the gate of the second test transistor M2 is reused as a second test pad 102. When ESD passes through, the first test transistor M1 and the second test transistor M2 burn out first, forming a short circuit, thereby protecting the GOA circuit.

[0160] In at least one embodiment shown in FIG. 6 , the first test pad 101 may be a test pad for transmitting a first noise reduction voltage signal VDDO, and the second test pad 102 may be a test pad for transmitting a second noise reduction voltage signal VDDE;

[0161] As shown in Figure 11, the first noise reduction voltage signal VDDO can be in antiphase with the second noise reduction voltage signal VDDE. When the potential of VDDO is a high voltage, the potential of VDDE can be a low voltage. When the potential of VDDO is a low voltage, the potential of VDDE is a high voltage. For example, every 2 seconds, the potential of VDDO jumps from the first voltage to the second voltage, and the potential of VDDE jumps from the second voltage to the first voltage. The first voltage is a high voltage or a low voltage, and the second voltage is a low voltage or a high voltage.

[0162] In a specific implementation, when the potential of VDDO is a high voltage, the first test transistor M1 is turned on and transmits VDDO to the interior of the display panel. At this time, the potential of VDDE is a low voltage, the second test transistor M2 is turned off, and the GOA circuit works normally; when the potential of VDDO is a low voltage, the first test transistor M1 is turned off. At this time, the potential of VDDE is a voltage, the second test transistor M2 is turned on and transmits VDDE to the interior of the display panel, and the GOA circuit works normally;

[0163] When ESD occurs, ESD first passes through the first test transistor M1 and the second test transistor M2, and the first test transistor M1 and the second test transistor M2 are burned, thereby protecting the GOA circuit. This can prevent problems such as the conductorization of the transistor included in the noise reduction unit caused by ESD impact, optimize the display product design, and improve the life of the display product.

[0164] In at least one embodiment of the present disclosure, the noise reduction unit may include a first noise reduction transistor and a second noise reduction transistor;

[0165] The gate of the first noise reduction transistor and the first electrode of the first noise reduction transistor may both be connected to VDDO, and the second electrode of the first noise reduction transistor may be electrically connected to a pull-down node;

[0166] A gate of the second noise reduction transistor and a first electrode of the second noise reduction transistor may both be connected to VDDE, and a second electrode of the second noise reduction transistor may be electrically connected to a pull-down node.

[0167] At least one embodiment of the present disclosure not only protects the signal connected to the noise reduction unit, but also protects other signals.

[0168] In at least one embodiment of the present disclosure, the first electrode and the second electrode are located in the same conductive layer;

[0169] The first electrode includes a first main portion and at least one first extension portion electrically connected to each other, and the second electrode includes a second main portion and at least one second extension portion;

[0170] The first main body portion and the second main body portion both extend along a first direction, and the first extension portion and the second extension portion both extend along a second direction;

[0171] The first direction intersects the second direction.

[0172] Optionally, the first electrode includes at least two first extension portions, and the at least two first extension portions are arranged along a first direction;

[0173] The second electrode includes at least two second extensions, and the at least two second extensions are arranged along the first direction;

[0174] At least a portion of at least one of the second extension portions is disposed between two adjacent first extension portions.

[0175] In at least one embodiment of the present disclosure, the first direction may be a horizontal direction, and the second direction may be a vertical direction, but the present invention is not limited thereto.

[0176] As shown in FIG6 to FIG10 , the first electrode of the first test transistor M1 is in an E shape, and the second electrode of the first test transistor M1 is in a π shape; the first electrode of the second test transistor M2 is in an E shape, and the second electrode of the second test transistor M2 is in a π shape;

[0177] As shown in FIG8A and FIG8B , the first electrode S1 of the first test transistor M1 includes a first main portion Z1 extending in the horizontal direction, a first first extension portion Y11 extending in the vertical direction, a second first extension portion Y21 extending in the vertical direction, and a third first extension portion Y31 extending in the vertical direction, which are electrically connected to each other;

[0178] Y11, Y21 and Y31 are arranged in the horizontal direction;

[0179] The second electrode D1 of the first test transistor M1 includes a second main portion Z2 extending in the horizontal direction, a first second extension portion Y12 extending in the vertical direction, and a second second extension portion Y22 extending in the vertical direction, which are electrically connected to each other;

[0180] Y12 and Y22 extend in the horizontal direction;

[0181] Y12 is set between Y11 and Y21, and Y12 is set between Y21 and Y31;

[0182] The second electrode S2 of the second test transistor M1 includes a third main portion Z3 extending in the horizontal direction, a fourth first extension portion Y41 extending in the vertical direction, a fifth first extension portion Y51 extending in the vertical direction, and a sixth first extension portion Y61 extending in the vertical direction, which are electrically connected to each other;

[0183] Y41, Y51 and Y61 are arranged in the horizontal direction;

[0184] The second electrode D2 of the second test transistor M2 includes a fourth main portion Z4 extending in the horizontal direction, a third second extension portion Y32 extending in the vertical direction, and a fourth second extension portion Y42 extending in the vertical direction, which are electrically connected to each other;

[0185] Y32 and Y42 extend in the horizontal direction;

[0186] Y32 is set between Y41 and Y51, and Y42 is set between Y51 and Y61.

[0187] In at least one embodiment of the present disclosure, when the electrical test structure includes a test transistor, the electrical test structure further includes a test pad; the test pad is used to transmit an electrical test signal to the test transistor; the gate of the test transistor and the test pad are separate structures;

[0188] The first electrode is electrically connected to the test pad.

[0189] In a specific implementation, the electrical test structure may include a test transistor, and the test transistor may be disposed between the test pad and the first connection structure.

[0190] Optionally, when the electrical test structure includes a test transistor,

[0191] The test transistor is an oxide transistor, and the width-to-length ratio of the test transistor is less than or equal to 2; or

[0192] The test transistor is an amorphous silicon transistor, and a width-to-length ratio of the test transistor is less than or equal to 100 / 3.6.

[0193] In a specific implementation, the aspect ratio of the test transistor may be comparable to or smaller than the aspect ratio of the TFT (thin film transistor) with the smallest aspect ratio in the GOA circuit, and the specific size is set according to the design of the GOA circuit.

[0194] In at least one embodiment of the display substrate shown in FIG. 6 to FIG. 10 , the first test transistor M1 and the second test transistor M2 may be oxide transistors, and both the aspect ratio of M1 and the aspect ratio of M2 are smaller than 2.

[0195] As shown in Figures 12 to 16, in the display substrate according to at least one embodiment of the present disclosure, the test structure includes an electrical test structure, a first first connection portion L11, and a second first connection portion L21; the electrical test structure includes a first test transistor M1, a second test transistor M2, a first test pad 101, and a test pad 102; the first test transistor M1 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area; the second test transistor M2 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area;

[0196] The first transmission line X1 and the second transmission line X2 are signal transmission lines between the driver integrated circuit and the driver circuit;

[0197] The first test transistor M1 includes a gate, a first electrode, and a second electrode; the gate G1 of the first test transistor M1 is electrically connected to the first electrode S1 of the first test transistor M1, and the second electrode D1 of the first test transistor M1 is electrically connected to the first transmission line X1 through a first first connection portion L11;

[0198] The second test transistor M2 includes a gate, a first electrode, and a second electrode; the gate G2 of the second test transistor M2 is electrically connected to the first electrode S2 of the second test transistor M2, and the second electrode D2 of the second test transistor M2 is electrically connected to the second transmission line X2 through the second first connection portion L21.

[0199] In at least one embodiment of the display substrate shown in Figures 12 to 16, the first transmission trace X1, the second transmission trace X2, the gate G1 of the first test transistor M1, and the gate G2 of the second test transistor M2 may be located in a first metal layer, and the first test pad 101, the second test pad 102, the first electrode S1 of the first test transistor M1, the second electrode D1 of the first test transistor M1, the first electrode S2 of the second test transistor M2, the second electrode D2 of the second test transistor M2, the first first connection portion L11, and the second first connection portion L21 are all located in a second metal layer;

[0200] The first metal layer may be an electrode metal layer, and the second metal layer may be a source-drain electrode layer.

[0201] Figure 13 is a layout diagram of the first metal layer in Figure 12, Figure 14 is a layout diagram of the source-drain electrode layer in Figure 12, Figure 15 is a layout diagram of the semiconductor layer in Figure 12, and Figure 16 is a layout diagram of the first conductive layer in Figure 12. The first conductive layer may be an ITO layer.

[0202] In FIG. 15 , the active pattern labeled A1 is M1 , and the active pattern labeled A2 is M2 .

[0203] As shown in FIG. 12 to FIG. 16 , the first test pad 101 is electrically connected to the first electrode S1 of the first test transistor M1 ; the second test pad 102 is electrically connected to the first electrode S2 of the second test transistor M2 ;

[0204] The gate G1 of the first test transistor M1 is electrically connected to the first electrode S1 of the first test transistor M1 through the first sixth via H16; the gate G2 of the second test transistor M2 is electrically connected to the first electrode S2 of the second test transistor M2 through the second sixth via H26;

[0205] The second electrode D1 of the first test transistor M1 is electrically connected to the first first connection portion L11; the first first connection portion L11 is electrically connected to the first transmission trace X1 through the first seventh via H17; the second electrode D2 of the second test transistor M2 is electrically connected to the second first connection portion L21; the second first connection portion L21 is electrically connected to the second transmission trace X2 through the second seventh via H27.

[0206] In at least one embodiment of the present disclosure, the pore diameters of H16, H17, H26, and H27 may be greater than or equal to 5 μm and less than or equal to 15 μm, but are not limited thereto.

[0207] As shown in Figures 12 to 16, the first test pad 101 is electrically connected to the first first conductive structure J11 located in the first conductive layer through the first third connection via H013. When performing electrical testing, the electrical test signal can be transmitted to the first test pad 101 through the first first conductive structure J11 and the first third connection via H013 through a probe, and then transmitted to the drive circuit. The electrical test signal can be transmitted to the second test pad 102 through the second first conductive structure J21 and the second third connection via H023 through a probe, and then transmitted to the drive circuit.

[0208] In at least one embodiment of the display substrate shown in FIG. 12 to FIG. 16 , when ESD occurs, the first test transistor M1 and the second test transistor M2 are burned out first, thereby protecting the internal units of the GOA from being affected.

[0209] Optionally, the aperture of the first third connecting via H03 may be greater than or equal to 30 μm and less than or equal to 80 μm, and the aperture of the second third connecting via H023 may be greater than or equal to 30 μm and less than or equal to 80 μm. For example, the aperture of the first third connecting via H013 may be 40 μm, and the aperture of the second third connecting via H023 may be 40 μm.

[0210] In at least one embodiment of the present disclosure, the resistivity of the first connection portion is greater than the resistivity of the transmission line; the test structure further includes a third electrostatic release structure;

[0211] The first connecting portion is electrically connected to the second electrode via the third electrostatic release structure;

[0212] The third electrostatic discharge structure includes a plurality of third via holes.

[0213] In a specific implementation, the first connection portion is electrically connected to the second electrode through a plurality of third vias included in the third electrostatic release structure. By using a plurality of third vias, electrostatic protection can be better performed compared to using a single third via.

[0214] In at least one embodiment of the present disclosure, the test structure further includes a fourth electrostatic release structure;

[0215] The first connection portion is electrically connected to the transmission line through the fourth electrostatic release structure;

[0216] The fourth electrostatic discharge structure includes a plurality of fourth via holes.

[0217] In a specific implementation, the first via is electrically connected to the transmission line through a plurality of fourth vias included in the fourth electrostatic release structure. By using a plurality of fourth vias, electrostatic protection can be better performed compared to using a single fourth via.

[0218] Optionally, the resistivity of the first connection portion is greater than the resistivity of the transmission trace, the first connection portion is electrically connected to the second electrode of the test transistor through a third via hole, and the first connection portion is electrically connected to the transmission trace through a fourth via hole;

[0219] The aperture of the third via hole is smaller than the aperture of the fourth via hole.

[0220] Optionally, a ratio of the aperture of the third via hole to the aperture of the fourth via hole is greater than or equal to 1 / 1.8 and less than or equal to 1 / 1.2.

[0221] As shown in Figures 17A to 21, in the display substrate according to at least one embodiment of the present disclosure, the test structure includes an electrical test structure and a first connection portion L1; the electrical test structure includes a first test transistor M1, a second test transistor M2, a first test pad 101, and a second test pad 102; the first test transistor M1 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area; the second test transistor M2 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area;

[0222] The first transmission line X1 and the second transmission line X2 are signal transmission lines between the driver integrated circuit and the driver circuit;

[0223] The first test transistor M1 includes a gate, a first electrode, and a second electrode; the gate G1 of the first test transistor M1 is electrically connected to the first electrode S1 of the first test transistor M1, and the second electrode D1 of the first test transistor M1 is electrically connected to the first transmission line X1 through a first first connection portion L11;

[0224] The second test transistor M2 includes a gate, a first electrode, and a second electrode; the gate G2 of the second test transistor M2 is electrically connected to the first electrode S2 of the second test transistor M2, and the second electrode D2 of the second test transistor M2 is electrically connected to the second transmission line X2 through the second first connection portion L21.

[0225] In at least one embodiment of the display substrate shown in Figures 17A to 21, the first transmission trace X1, the second transmission trace X2, the gate G1 of the first test transistor M1, and the gate G2 of the second test transistor M2 may be located in a first metal layer; the first test pad 101, the second test pad 102, the first electrode S1 of the first test transistor M1, the second electrode D1 of the first test transistor M1, the first electrode S2 of the second test transistor M1, and the second electrode D2 of the second test transistor M2 are located in a second metal layer; the first first connection portion L11 and the second first connection portion L21 are located in a first conductive layer;

[0226] The first metal layer may be a gate electrode layer, the second metal layer may be a source / drain electrode layer, and the first conductive layer may be an ITO layer.

[0227] 18 is a layout diagram of the first metal layer in FIG17A , FIG19 is a layout diagram of the source / drain electrode layer in FIG17A , FIG20 is a layout diagram of the semiconductor layer in FIG17A , and FIG21 is a layout diagram of the first conductive layer in FIG17A .

[0228] In FIG20 , the active pattern labeled A1 is M1, and the active pattern labeled A2 is M2.

[0229] As shown in FIG. 17A to FIG. 21 , the first test pad 101 is electrically connected to the first electrode S1 of the first test transistor M1 ;

[0230] The gate G1 of the first test transistor M1 is electrically connected to the first electrode S1 of the first test transistor M1 through the first sixth via hole H16;

[0231] The second electrode D1 of the first test transistor M1 is electrically connected to the first first connection portion L11 through the first third via H13; the first first connection portion L11 is electrically connected to the first transmission trace X1 through the first fourth via H14;

[0232] The gate G2 of the second test transistor M2 is electrically connected to the first electrode S2 of the second test transistor M2 through the second sixth via H26;

[0233] The second electrode D2 of the second test transistor M2 is electrically connected to the second first connection portion L21 through the second third via H23 ; the second first connection portion L21 is electrically connected to the second transmission trace X2 through the second fourth via H24 .

[0234] As shown in Figures 17A to 21, the first test pad 101 is electrically connected to the first first conductive structure J11 located in the first conductive layer through the first third connection via H013, and the second test pad 102 is electrically connected to the second first conductive structure J21 located in the first conductive layer through the second third connection via H023. When performing electrical testing, the electrical test signal can be transmitted to the first test pad 101 through the first first conductive structure J11 and the first third connection via H013 through a probe, and then transmitted to the driving circuit. The electrical test signal can be transmitted to the second test pad 102 through the second first conductive structure J21 and the second third connection via H023 through a probe, and then transmitted to the driving circuit.

[0235] In at least one embodiment of the display substrate shown in FIG. 17A to FIG. 21 , the resistivity of the first first connection portion L11 is greater than the resistivity of the first transmission trace X1 ; the resistivity of the second first connection portion L21 is greater than the resistivity of the second transmission trace X2 ;

[0236] The thickness of the first first connection portion L11 is smaller than the thickness of the first transmission line X1 , and the thickness of the second first connection portion L21 is smaller than the thickness of the second transmission line X2 .

[0237] In at least one embodiment of the display substrate shown in FIG. 17A to FIG. 21 , the resistance of L11 may be greater than the resistance of X1 , and the resistance of L21 may be greater than the resistance of X2 .

[0238] In at least one embodiment of the display substrate shown in Figures 17A to 21, the aperture of the first third via hole H13 is smaller than the aperture of the first fourth via hole H14, and the aperture of the second third via hole H23 is smaller than the aperture of the second fourth via hole H24.

[0239] In at least one embodiment of the display substrate shown in Figures 17A to 21, the pore size of H13 can be greater than or equal to 5μm and less than or equal to 15μm, the pore size of H23 can be greater than or equal to 5μm and less than or equal to 15μm, the pore size of H14 can be greater than or equal to 15μm and less than or equal to 40μm, and the pore size of H24 can be greater than or equal to 15μm and less than or equal to 40μm, but are not limited to this.

[0240] In at least one embodiment of the display substrate shown in FIG. 17A to FIG. 21 , when ESD occurs, the first test transistor M1 , the second test transistor M2 , the first third via H13 and the second third via H23 are preferentially burned out, thereby protecting the internal units of the GOA from being affected.

[0241] In at least one embodiment of the display substrate shown in FIG. 17A to FIG. 21 , the apertures of H013 and H023 may be greater than or equal to 30 μm and less than or equal to 80 μm. For example, the apertures of H013 and H023 may be 40 μm, but are not limited thereto.

[0242] In FIG17B , the structure labeled JS13 is the first third electrostatic release structure, and the structure labeled JS23 is the second third electrostatic release structure;

[0243] The first third electrostatic discharge structure JS13 includes six third via holes, and the second third electrostatic discharge structure JS23 includes six third via holes;

[0244] The first fourth electrostatic discharge structure JS14 includes six fourth via holes, and the second fourth electrostatic discharge structure JS24 includes six fourth via holes.

[0245] In at least one embodiment shown in FIG. 17A to FIG. 21 , each third electrostatic discharge structure includes six third via holes, so that electrostatic protection can be well performed by increasing the number of via holes.

[0246] In at least one embodiment shown in Figures 17A to 21, the first test pad 101 can be used to transmit the first noise reduction voltage signal VDDO, and the second test pad 102 can be used to transmit the second noise reduction voltage signal VDDE; the first test transistor M1 and the second test transistor M2 can be oxide transistors, and the width-to-length ratio of M1 and the width-to-length ratio of M2 can be less than or equal to 2, but are not limited to this.

[0247] FIG. 22 is a cross-sectional view taken along line BB′ in FIG. 17A .

[0248] In FIG22 , reference numeral 50 denotes a substrate, reference numeral 51 denotes a first metal layer, reference numeral 52 denotes a first conductive layer, reference numeral 53 denotes a semiconductor layer, and reference numeral 54 denotes a second metal layer.

[0249] The number 502 is the second insulating layer, the number 503 is the third insulating layer, and the number 504 is the fourth insulating layer.

[0250] As shown in Figures 23 to 27, in the display substrate according to at least one embodiment of the present disclosure, the test structure includes an electrical test structure, a first first connection portion L11, and a second first connection portion L21; the electrical test structure includes a first test transistor M1 and a second test transistor M2; the first test transistor M1 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area, and the second test transistor M2 is disposed on a side of the first transmission trace X1 and the second transmission trace X2 away from the display area;

[0251] The first transmission line X1 and the second transmission line X2 are signal transmission lines between the driver integrated circuit and the driver circuit;

[0252] The first test transistor M1 includes a gate, a first electrode, and a second electrode; the gate of the first test transistor M1 is electrically connected to the first electrode S1 of the first test transistor M1, and the second electrode D1 of the first test transistor M1 is electrically connected to the first transmission line X1 through a first first connection portion L11;

[0253] The second test transistor M2 includes a gate, a first electrode, and a second electrode; the gate of the second test transistor M2 is electrically connected to the first electrode S2 of the second test transistor M2, and the second electrode D2 of the second test transistor M2 is electrically connected to the second transmission line X2 through the second first connection portion L21;

[0254] As shown in FIG24 , the gate of the first test transistor M1 and the first test pad 101 are an integrated structure, and the gate of the second test transistor M2 and the second test pad 102 are an integrated structure;

[0255] The first test transistor M1 is used to transmit an electrical test signal to the first transmission line X1 , and the second test transistor M2 is used to transmit an electrical test signal to the second transmission line X2 .

[0256] In FIG25A , S1 is the first electrode of M1 and D1 is the second electrode of M1 ; S2 is the first electrode of M2 and D2 is the second electrode of M2 .

[0257] In at least one embodiment shown in FIG. 23 to FIG. 27 , the first transmission trace X1, the second transmission trace X2, the first test pad 101, and the second test pad 102 are all located in the first metal layer; the first electrode S1 of the first test transistor M1, the second electrode D1 of the first test transistor M1, the first electrode S2 of the second test transistor M2, and the second electrode D2 of the second test transistor M2 are all located in the second metal layer; and the first first connection portion L11 and the second first connection portion L21 are located in the first conductive layer;

[0258] The first metal layer may be a gate electrode layer, and the second metal layer may be a source / drain electrode layer, but the present invention is not limited thereto.

[0259] 24 is a layout diagram of the first metal layer in FIG. 23 , FIG. 25A and FIG. 25B are layout diagrams of the second metal layer in FIG. 23 , FIG. 26 is a layout diagram of the semiconductor layer in FIG. 23 , and FIG. 27 is a layout diagram of the first conductive layer in FIG. 23 .

[0260] In FIG26 , the active pattern labeled A1 is M1, and the active pattern labeled A2 is M2.

[0261] As shown in FIG23 to FIG27 , the second electrode D1 of the first test transistor M1 is electrically connected to the first first connection portion L11 through the first third via H13, and the second electrode D2 of the second test transistor M2 is electrically connected to the second first connection portion L21 through the second third via H23;

[0262] The first first connection portion L11 is electrically connected to the first transmission line X1 through the first fourth via H14; the second first connection portion L21 is electrically connected to the second transmission line X2 through the second fourth via H24;

[0263] The first test pad 101 is electrically connected to the first electrode S1 of the first test transistor M1 and the first first conductive structure J11 located in the first conductive layer through a first second connection via H012; the second test pad 102 is electrically connected to the first electrode S2 of the second test transistor M2 and the second first conductive structure J21 located in the first conductive layer through a second second connection via H022.

[0264] The aperture of the first second connection via H012 may be greater than or equal to 30 μm and less than or equal to 80 μm, and the aperture of the second second connection via H022 may be greater than or equal to 30 μm and less than or equal to 80 μm. For example, the aperture of the first second connection via H012 may be 40 μm, and the aperture of the second second connection via H022 may be 40 μm.

[0265] In at least one embodiment shown in FIG. 23 to FIG. 27 , the first test transistor M1 and the second test transistor M2 may be n-type transistors, but the present invention is not limited thereto.

[0266] In at least one embodiment of the display substrate shown in FIG. 23 to FIG. 27 , the resistivity of the first first connection portion L11 is greater than the resistivity of the first transmission trace X1 ; the resistivity of the second first connection portion L21 is greater than the resistivity of the second transmission trace X2 ;

[0267] The thickness of the first first connection portion L11 is smaller than the thickness of the first transmission line X1 , and the thickness of the second first connection portion L21 is smaller than the thickness of the second transmission line X2 .

[0268] In at least one embodiment of the display substrate shown in FIG. 23 to FIG. 27 , the resistance of L11 may be greater than the resistance of X1 , and the resistance of L21 may be greater than the resistance of X2 .

[0269] In at least one embodiment of the display substrate shown in Figures 23 to 27, the aperture of the first third via hole H13 is smaller than the aperture of the first fourth via hole H14, and the aperture of the second third via hole H23 is smaller than the aperture of the second fourth via hole H24.

[0270] In at least one embodiment of the display substrate shown in Figures 23 to 27, the pore size of H13 can be greater than or equal to 5μm and less than or equal to 15μm, the pore size of H23 can be greater than or equal to 5μm and less than or equal to 15μm, the pore size of H14 can be greater than or equal to 15μm and less than or equal to 40μm, and the pore size of H24 can be greater than or equal to 15μm and less than or equal to 40μm, but are not limited to this.

[0271] In at least one embodiment shown in Figures 23 to 27, the electrical test structure includes a first test transistor M1 connected to a diode and a second test transistor M2 connected to a diode. The gate of the first test transistor M1 is reused as a first test pad 101, and the gate of the second test transistor M2 is reused as a second test pad 102. When ESD passes through, the first test transistor M1, the second test transistor M2, the first third via H13, and the second third via H23 are preferentially burned to form a short circuit, thereby protecting the GOA circuit.

[0272] In at least one embodiment shown in FIG. 23 to FIG. 27 , the first test pad 101 may be a test pad for transmitting a first noise reduction voltage signal VDDO, and the second test pad 102 may be a test pad for transmitting a second noise reduction voltage signal VDDE;

[0273] In a specific implementation, when the potential of VDDO is a high voltage, the first test transistor M1 is turned on and transmits VDDO to the interior of the display panel. At this time, the potential of VDDE is a low voltage, the second test transistor M2 is turned off, and the GOA circuit works normally; when the potential of VDDO is a low voltage, the first test transistor M1 is turned off. At this time, the potential of VDDE is a voltage, the second test transistor M2 is turned on and transmits VDDE to the interior of the display panel, and the GOA circuit works normally;

[0274] When ESD occurs, ESD first passes through the first test transistor M1 and the second test transistor M2, and the first test transistor M1 and the second test transistor M2 are burned, thereby protecting the GOA circuit. This can prevent problems such as the conductorization of the transistor included in the noise reduction unit caused by ESD impact, optimize the display product design, and improve the life of the display product.

[0275] As shown in FIG25A and FIG25B , the first electrode S1 of the first test transistor M1 includes a first main portion Z1 extending in the horizontal direction, a first first extension portion Y11 extending in the vertical direction, a second first extension portion Y21 extending in the vertical direction, and a third first extension portion Y31 extending in the vertical direction, which are electrically connected to each other;

[0276] Y11, Y21 and Y31 are arranged in the horizontal direction;

[0277] The second electrode D1 of the first test transistor M1 includes a second main portion Z2 extending in the horizontal direction, a first second extension portion Y12 extending in the vertical direction, and a second second extension portion Y22 extending in the vertical direction, which are electrically connected to each other;

[0278] Y12 and Y22 extend in the horizontal direction;

[0279] Y12 is set between Y11 and Y21, and Y12 is set between Y21 and Y31;

[0280] The second electrode S2 of the second test transistor M1 includes a third main portion Z3 extending in the horizontal direction, a fourth first extension portion Y41 extending in the vertical direction, a fifth first extension portion Y51 extending in the vertical direction, and a sixth first extension portion Y61 extending in the vertical direction, which are electrically connected to each other;

[0281] Y41, Y51 and Y61 are arranged in the horizontal direction;

[0282] The second electrode D2 of the second test transistor M2 includes a fourth main portion Z4 extending in the horizontal direction, a third second extension portion Y32 extending in the vertical direction, and a fourth second extension portion Y42 extending in the vertical direction, which are electrically connected to each other;

[0283] Y32 and Y42 extend in the horizontal direction;

[0284] Y32 is set between Y41 and Y51, and Y42 is set between Y51 and Y61.

[0285] In at least one embodiment of the present disclosure, the test pad and the transmission trace may be located in the same conductive layer, and the transmission trace and the first connecting portion may be located in different conductive layers.

[0286] For example, the test pad and the transmission trace may both be located in a first metal layer, and the first connection portion may be located in a first conductive layer.

[0287] Optionally, the first connecting portion, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, and the first connecting portion and the transmission line are located in different conductive layers.

[0288] For example, the first connection portion, the first electrode, and the second electrode may all be located in the second metal layer, the gate and the transmission line may all be located in the first metal layer, and the first connection portion may be located in the first conductive layer.

[0289] In at least one embodiment of the present disclosure, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, the first connecting portion and the first electrode are located in different conductive layers, and the first connecting portion and the transmission line are located in different conductive layers.

[0290] For example, the first electrode and the second electrode may both be located in the second metal layer, the gate and the transmission line may both be located in the first metal layer, and the first connection portion may be located in the first conductive layer.

[0291] Optionally, the test pad, the first electrode, the second electrode and the first connecting portion are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, and the first connecting portion and the transmission line are located in different conductive layers.

[0292] For example, the test pad, the first electrode, the second electrode and the first connection portion may all be located in the second metal layer, the gate and the transmission line may all be located in the first metal layer, and the first connection portion may be located in the first conductive layer.

[0293] Optionally, the test pad, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, the first connecting portion and the test pad are located in different conductive layers, and the first connecting portion and the transmission line are located in different conductive layers.

[0294] For example, the test pad, the first electrode, and the second electrode may all be located in the second metal layer, the gate and the transmission line may all be located in the first metal layer, and the first connection portion may be located in the first conductive layer.

[0295] The display substrate described in at least one embodiment of the present disclosure can, without increasing additional development costs and the number of masks, burn out the test transistor and / or the first connection portion when ESD occurs, thereby ensuring that the GOA circuit inside the display panel is not affected by ESD and improving the life of the display product.

[0296] The disclosed embodiments can effectively improve the anti-static capability of display products without taking up additional space, affecting the wiring of display products, increasing the border design, or increasing the number of masks, thereby enhancing the competitiveness of display products.

[0297] The display panel according to the embodiment of the present disclosure includes a driver integrated circuit and the above-mentioned test structure;

[0298] The driving integrated circuit is used to provide a signal to the driving circuit.

[0299] FIG. 28 is a schematic diagram of a test structure included in a display panel according to at least one embodiment of the present disclosure.

[0300] In FIG28 , X1 is a first transmission trace, X2 is a second transmission trace, X3 is a third transmission trace, X4 is a fourth transmission trace, X5 is a fifth transmission trace, and X6 is a sixth transmission trace. 101 is a first test pad, 102 is a second test pad, and 103 is a third test pad. L11 is a first first connection portion, L21 is a second first connection portion, L31 is a third first connection portion, L41 is a fourth first connection portion, L51 is a fifth first connection portion, and L61 is a sixth first connection portion.

[0301] L11 is electrically connected to X1, L21 is electrically connected to X2, L31 is electrically connected to X3, L41 is electrically connected to X4, L51 is electrically connected to X5, and L61 is electrically connected to X6;

[0302] The first test pad 101 is electrically connected to L11 , the second test pad 102 is electrically connected to L31 , and the third test pad 103 is electrically connected to L51 .

[0303] In the schematic diagram of the test structure shown in FIG28 , the left side of each transmission line is the driving circuit inside the display panel.

[0304] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0305] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A display substrate having a display area and a peripheral area, the display substrate comprising a test structure, a transmission line and a driving circuit; the test structure comprising an electrical test structure and a first connection portion; The electrical test structure is arranged on a side of the transmission line away from the display area; the electrical test structure is used to transmit an electrical test signal to the drive circuit; the drive circuit is used to provide a drive signal; The transmission line is a signal transmission line between the driver integrated circuit and the driver circuit; the electrical test structure is electrically connected to the transmission line through the first connection portion; The transmission line and the first connection portion are located in different conductive layers.

2. The display substrate according to claim 1, wherein: The resistivity of the first connection portion is greater than the resistivity of the transmission line.

3. The display substrate according to claim 1, wherein: The electrical test structure includes a test transistor; the test transistor includes a gate, a first electrode, and a second electrode; the gate is electrically connected to the first electrode, and the second electrode is electrically connected to the transmission line through the first connection portion.

4. The display substrate according to claim 1, wherein: The transmission line is a single-layer line, and the first connection portion is a single-layer connection portion.

5. The display substrate according to claim 2, wherein: The electrical test structure includes a test pad; The test pad is electrically connected to the first connection portion.

6. The display substrate according to claim 5, wherein: The test structure also includes a first electrostatic release structure; The first connection portion is electrically connected to the test pad via the first electrostatic release structure; The first electrostatic release structure includes a plurality of first via holes.

7. The display substrate according to claim 5, wherein: The test structure also includes a second electrostatic release structure; The first connection portion is electrically connected to the transmission line through the second electrostatic release structure; The second electrostatic release structure includes a plurality of second via holes.

8. The display substrate according to claim 5, wherein: The first connection portion is electrically connected to the test pad through a first via hole, and the first connection portion is electrically connected to the transmission trace through a second via hole; The aperture of the first via hole is smaller than the aperture of the second via hole.

9. The display substrate according to claim 8, wherein: The ratio of the aperture of the first via hole to the aperture of the second via hole is greater than or equal to 1 / 1.8 and less than or equal to 1 / 1.

2.

10. The display substrate according to claim 3, wherein: The electrical test structure further includes a test pad; the gate of the test transistor and the test pad are an integrated structure; the test transistor is used to transmit an electrical test signal to the transmission line.

11. The display substrate according to claim 3, wherein: The electrical test structure further comprises a test pad; the test pad is used to transmit an electrical test signal to the test transistor; the gate of the test transistor and the test pad are separate structures; The first electrode is electrically connected to the test pad.

12. The display substrate according to claim 10 or 11, wherein: The resistivity of the first connection portion is greater than the resistivity of the transmission line; the test structure further includes a third electrostatic release structure; The first connecting portion is electrically connected to the second electrode through the third electrostatic release structure; The third electrostatic release structure includes a plurality of third via holes.

13. The display substrate according to claim 10 or 11, wherein: The test structure also includes a fourth electrostatic release structure; The first connection portion is electrically connected to the transmission line through the fourth electrostatic release structure; The fourth electrostatic release structure includes a plurality of fourth via holes.

14. The display substrate according to claim 10 or 11, wherein: The resistivity of the first connection portion is greater than the resistivity of the transmission line, the first connection portion is electrically connected to the second electrode through a third via hole, and the first connection portion is electrically connected to the transmission line through a fourth via hole; The aperture of the third via hole is smaller than the aperture of the fourth via hole.

15. The display substrate according to claim 14, wherein: A ratio of a diameter of the third via hole to a diameter of the fourth via hole is greater than or equal to 1 / 1.8 and less than or equal to 1 / 1.

2.

16. The display substrate according to any one of claims 1 to 11, wherein: The thickness of the first connection portion is smaller than the thickness of the transmission line.

17. The display substrate according to any one of claims 1 to 11, wherein: The first connection portion is located in a first conductive layer, and the first conductive layer is made of ITO.

18. The display substrate according to claim 3, wherein: The test transistor is an oxide transistor, and a width-to-length ratio of the test transistor is less than or equal to 2.

19. The test structure of claim 3, wherein: The test transistor is an amorphous silicon transistor, and a width-to-length ratio of the test transistor is less than or equal to 100 / 3.

6.

20. The display substrate according to any one of claims 5 to 9, wherein: The test pad and the transmission line are both located in the same conductive layer, and the transmission line and the first connecting portion are located in different conductive layers.

21. The display substrate according to claim 10, wherein: The first connection portion, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, and the first connection portion and the transmission line are located in different conductive layers.

22. The display substrate according to claim 10, wherein: The first electrode and the second electrode are located in the same conductive layer; The first electrode includes a first main body portion and at least one first extension portion electrically connected to each other, and the second electrode includes a second main body portion and at least one second extension portion; The first main body portion and the second main body portion both extend along a first direction, and the first extension portion and the second extension portion both extend along a second direction; The first direction intersects the second direction.

23. The display substrate according to claim 22, wherein: The first electrode comprises at least two first extension portions, and the at least two first extension portions are arranged along a first direction; The second electrode comprises at least two second extension portions, and the at least two second extension portions are arranged along the first direction; At least a portion of at least one of the second extension portions is disposed between two adjacent first extension portions.

24. The display substrate according to claim 10, wherein: The first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, the first connecting portion and the first electrode are located in different conductive layers, and the first connecting portion and the transmission line are located in different conductive layers.

25. The display substrate according to claim 11, wherein: The test pad, the first electrode, the second electrode and the first connection portion are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, and the first connection portion and the transmission line are located in different conductive layers.

26. The display substrate according to claim 11, wherein: The test pad, the first electrode and the second electrode are located in the same conductive layer, the gate and the transmission line are located in the same conductive layer, the first connecting portion and the test pad are located in different conductive layers, and the first connecting portion and the transmission line are located in different conductive layers.

27. A display panel comprising a driver integrated circuit and a display substrate according to any one of claims 1 to 26; The driving integrated circuit is used for providing a signal to the driving circuit.

28. A display device comprising the display panel according to claim 27.

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