Electrical improvements for 3D NAND

Abstract

An exemplary semiconductor processing method may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within a processing region of a semiconductor processing chamber. Alternating layers of material may be formed on a substrate. One or more recesses may be formed in the alternating layers of material. A method may include forming a first silicon-containing material. The first silicon-containing material may extend into one or more recesses formed in the alternating layers of material. A method may include providing a halogen-containing precursor to a processing region of a semiconductor processing chamber. A method may include forming a silicon and halogen containing material. A silicon-and halogen-containing material may overlie the first silicon-containing material. The method may include forming a second silicon-containing material. A second silicon-containing material may overlie the silicon-and halogen-containing material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Patent Application No. 17 / 705,135, filed on March 25, 2022, entitled “ELECTRICAL IMPROVEMENTS FOR 3D NAND,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present technology relates to semiconductor processes and materials and more particularly to forming and processing memory holes in a hierarchical memory structure. Background Art

[0004] Integrated circuits are made possible by processes that produce intricately patterned material layers on a substrate surface. Producing patterned materials on a substrate requires controlled methods of forming and removing exposed materials. Stacked memories (such as vertical or 3D NAND) may include a series of alternating layers forming dielectric materials, through which multiple memory holes or holes may be etched. Subsequent deposition and processing of material layers in the memory holes may be performed to form polysilicon channels. The material properties of the material layers may affect device performance, which may result in defects or performance degradation in the final device. As the number of alternating layers increases, continued innovation in 3D NAND technology is necessary to meet the requirements for high string currents and reduced device variations.

[0005] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology addresses these and other needs. Summary of the invention

[0006] An exemplary semiconductor processing method may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. Alternating material layers may be formed on the substrate. One or more recesses may be formed in the alternating material layers. The method may include forming a first silicon-containing material. The first silicon-containing material may extend into one or more recesses formed in the alternating material layers. The method may include providing a halogen-containing precursor to a processing region of the semiconductor processing chamber. The method may include forming a silicon-containing and halogen material. The silicon-containing and halogen material may overlie the first silicon-containing material. The method may include forming a second silicon-containing material. The second silicon-containing material may overlie the silicon-containing and halogen material.

[0007] In some embodiments, the temperature within the semiconductor processing chamber may be maintained at less than or about 700° C. The pressure within the semiconductor processing chamber may be maintained at less than or about 300 Torr. The silicon-containing precursor may be or include monosilane, disilane, dichlorosilane, or trisilane. The halogen-containing precursor may include fluorine. The silicon-containing and halogen-containing material may include a silicon-containing and fluorine-containing material. The halogen-containing precursor may be or include nitrogen trifluoride or silicon tetrafluoride. The method may include forming a first silicon-containing material before forming the silicon-containing and halogen-containing material. The first silicon-containing material may extend into one or more recesses formed in the alternating material layers. The method may include forming a second silicon-containing material. The second silicon-containing material may overlie the silicon-containing and halogen-containing material. The method may include forming both the first silicon-containing material and the second silicon-containing material. The silicon-containing and halogen-containing material may be characterized by a thickness of less than or about 60 nm. The method may include annealing the substrate after forming the second silicon-containing material. During the annealing, the halogen material within the silicon-containing and halogen-containing material may diffuse into the first silicon-containing material, the second silicon-containing material, or both.

[0008] Some embodiments of the present technology may encompass semiconductor processing methods. The method may include forming a first material layer in one or more grooves defined in alternating material layers on a substrate in a processing region of a semiconductor processing chamber. The first material layer may be a first silicon-containing material. The method may include forming a second material layer on the first material layer. The second material layer may be a silicon- and fluorine-containing material. The method may include forming a third material layer on the second material layer. The third material layer may be a second silicon-containing material.

[0009] In some embodiments, the temperature within the semiconductor processing chamber may be maintained at less than or about 700° C. The pressure within the semiconductor processing chamber may be maintained at less than or about 300 Torr. The alternating material layers may include alternating oxide material layers and nitride material layers. The substrate may include more than 16 alternating material layers. The second material layer may be characterized by a thickness greater than the thickness of the first material layer and the third material layer. The second material layer may be characterized by a thickness between about 2 nm and about 30 nm. The method may include annealing the substrate after forming the first material layer, the second material layer, and the third material layer. The first material layer, the third material layer, or both may include amorphous silicon. Annealing may convert at least a portion of the amorphous silicon into polycrystalline silicon. The method may include removing a portion of the first silicon-containing material, the silicon-containing and halogen-containing material, and the second silicon-containing material after annealing the substrate.

[0010] Some embodiments of the present technology include semiconductor structures. The structures may include a substrate having alternating material layers formed on the substrate. One or more grooves may be formed in the alternating material layers. These structures may include polycrystalline silicon material, which extends into the one or more grooves. A second surface of the polycrystalline material opposite to the first surface of the polycrystalline silicon material may overlie the alternating material layers. The polycrystalline silicon material may include halogens. A portion of the polycrystalline silicon material disposed between the first surface and the second surface may have a higher concentration of halogen atoms than the first surface and the second surface.

[0011] In some embodiments, the polysilicon material is characterized by a thickness of less than or about 30 nm.

[0012] This technology can provide many benefits over conventional systems and techniques. For example, these processes and structures can improve polysilicon channel formation. In addition, the operation of embodiments of the present technology can improve the electrical performance of the final device or structure. These and other embodiments and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] A further understanding of the nature and advantages of the disclosed technology may be obtained by reference to the remaining portions of the specification and the accompanying drawings.

[0014] Figure 1 A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown.

[0015] Figure 2 Selected operations in a method of forming according to some embodiments of the present technology are shown.

[0016] FIG. 3A to FIG. 3D Exemplary schematic cross-sectional structures are shown in which material layers are included and created according to some embodiments of the present technology.

[0017] Several drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically noted to be to scale. In addition, as schematic diagrams, the drawings are provided to aid understanding, and the drawings may not include all aspects or information compared to a true representation, and may include superfluous or exaggerated material for illustrative purposes.

[0018] In the accompanying drawings, similar components and / or features may have the same reference numeral. In addition, various components of the same type may be distinguished by adding a letter that distinguishes the similar components after the reference numeral. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0019] In the transition from 2D NAND to 3D NAND, the processing options can be modified from vertical application to horizontal application. During 3D NAND processing, the stack of placeholder layers and dielectric materials can form inter-electrode dielectrics or inter-polysilicon dielectrics ("IPD") layers. These placeholder layers can have various operations performed to place the structure before completely removing the material and replacing it with metal. When forming a memory hole, the hole can extend through all the alternating material layers before entering the underlying substrate. Subsequent processing can form a stepped structure of contacts, and can also laterally discharge the placeholder material and form a conductive material in the groove.

[0020] As 3D NAND structures grow in the number of cells formed, the aspect ratio of the memory hole to the other structures sometimes increases significantly. The growth in the number of cells formed may result in a decay of the string current. In addition, small threshold voltage changes may require a reduction in the thickness of the polysilicon channel formed in the memory hole. When forming the polysilicon channel, the reduction in the thickness of the deposited silicon material may result in a reduction in the string current. In addition, as the number of inter-electrode dielectrics and IPD layers increases, the string current may be further sacrificed.

[0021] Conventional techniques may have difficulty balancing the properties associated with the thickness of the polysilicon channel. As the thickness decreases, the defect variability decreases, resulting in a decrease in threshold voltage variation. However, as previously discussed, the reduction in thickness also results in a decrease in string current. The present technology overcomes these problems by adjusting the material used to form the polysilicon channel, which can reduce the tradeoff in electrical performance when reducing the thickness of the polysilicon channel. For example, when forming the polysilicon channel, the present technology can use a three-part material layer. The present technology can deposit an intermediate layer of halogen-doped material between two layers of amorphous material, rather than using only amorphous material. By using halogen-doped materials, the halogens can improve electrical properties by passivating trap states and increasing carrier mobility, thereby increasing the string current compared to conventional techniques.

[0022] While the remainder of the disclosure will routinely identify specific materials and semiconductor structures that utilize the disclosed techniques, it will be readily appreciated that these systems, methods, and materials are equally applicable to many other structures that may benefit from aspects of the present techniques. Thus, the techniques should not be considered limited to use with 3D NAND processes or individual materials. Furthermore, while an exemplary chamber is described to provide a basis for the present techniques, it should be understood that the present techniques are applicable to virtually any semiconductor processing chamber that may allow for the described operations.

[0023] Figure 1A cross-sectional view of an exemplary semiconductor processing chamber system 100 according to some embodiments of the present technology is shown. Although it should be understood that these methods can be similarly performed in any chamber in which film formation can occur, according to some embodiments of the present technology, a semiconductor processing chamber 100 can be used to form a film layer. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and encapsulating the substrate support 104 in a processing volume 120. A substrate 103 can be provided to the processing volume 120 through an opening 126, which can be conventionally sealed for processing using a slit valve or door. During processing, the substrate 103 can be placed on a surface 105 of the substrate support. As shown by arrow 145, the substrate support 104 can be rotated along an axis 147, and the shaft 144 of the substrate support 104 can be located at the axis. Alternatively, during the deposition process, the substrate support 104 can be lifted as needed for rotation.

[0024] The plasma profile modulator 111 may be disposed in the semiconductor processing chamber 100 to control the plasma distribution on the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be disposed near the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be a ring or annular member and may be a ring electrode. The first electrode 108 may be a continuous ring around the circumference of the semiconductor processing chamber 100, which surrounds the processing volume 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode (such as a perforated ring or mesh electrode) or may be a plate electrode (such as, for example, a second gas distributor).

[0025] The one or more insulators 110a, 110b may be a dielectric material such as a ceramic or a metal oxide (e.g., aluminum oxide and / or aluminum nitride), may contact the first electrode 108, and electrically and thermally separate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define apertures 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled to a first electrical power source 142 such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to the processing chamber. In some embodiments, the first electrical power source 142 may be an RF power source.

[0026] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive components and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the panel of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first electrical power source 142, such as Figure 1 As shown in , or in some embodiments, the gas distributor 112 may also be grounded.

[0027] The first electrode 108 may be coupled to a first tuning circuit 128, which may control a ground path for the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit that achieves a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some of the illustrated embodiments, the first tuning circuit 128 may include a first circuit branch and a second circuit branch coupled in parallel between ground and the first electronic sensor 130. The first circuit branch may include a first inductor 132A. The second circuit branch may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and an anode connecting both the first circuit branch and the second circuit branch to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to a first electronic controller 134 , which may provide a degree of closed-loop control of plasma conditions within the processing volume 120 .

[0028] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire mesh, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 via a conduit 146, such as a cable having a selected resistance (such as 50 ohms) disposed in the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control of the plasma conditions in the processing volume 120.

[0029] A third electrode 124, which may serve as a bias electrode and / or an electrostatic clamping electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second electrical power source 150 via a filter 148, which may be an impedance matching circuit. The second electrical power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second electrical power source 150 may be RF bias power.

[0030] Figure 1 The lid assembly 106 and substrate support 104 of the semiconductor processing chamber 100 can be used with any processing chamber for plasma or thermal processing. In operation, the semiconductor processing chamber 100 can provide real-time control of plasma conditions in the processing volume 120. The substrate 103 can be disposed on the substrate support 104, and the process gas can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the semiconductor processing chamber 100 through the outlet 152. Electrical power can be coupled to the gas distributor 112 to establish a plasma in the processing volume 120. In some embodiments, the substrate can be subjected to an electrical bias using the third electrode 124.

[0031] When the plasma in the processing volume 120 is energized, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground path represented by the two tuning circuits 128 and 136. Set points may be delivered to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and plasma density uniformity from center to edge. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0032] Each of the tuning circuits 128, 136 may have a variable impedance that can be adjusted using the corresponding electronic controller 134, 140. When the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. The range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value in the capacitance range of each of the variable capacitors. Therefore, when the capacitance of the first electronic controller 134 is at a minimum or maximum value, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape having a minimum space or coverage on the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the spatial coverage of the plasma may grow to a maximum value, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber wall and the spatial coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, as the capacitance of the second electronic controller 140 may be varied to increase and decrease the spatial coverage of the plasma on the substrate support.

[0033] The electronic sensors 130, 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be installed in each sensor, and the sensor may be equipped with control software that determines adjustments to each respective electronic controller 134, 140 to minimize deviations from the set point. Thus, the plasma shape may be selected and dynamically controlled during processing. It should be understood that while the foregoing discussion is based on electronic controllers 134, 140 that may act as variable capacitors, any electronic component with an adjustable characteristic may be used to provide a tuned circuit 128 and 136 with an adjustable impedance.

[0034] Figure 2 Operations of an exemplary semiconductor processing method 200 according to some embodiments of the present technology are shown. The method may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other processing chamber in which plasma deposition may be performed. The method 200 may include a number of optional operations prior to mimicking the method 200, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the operations. For example, the method may begin after multiple pairs of layers have been deposited to produce a 3D NAND memory.

[0035] Method 200 may include a number of optional operations as depicted, which may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many operations are described to provide a greater range of structure formation, but are not critical to the technology, or many operations may be performed by alternative methods, which will be discussed further below. Method 200 describes FIG. 3A to FIG. 3D The operations schematically shown in FIG. 2 will be described in conjunction with the operations of method 200. It should be understood that FIG. 3A to FIG. 3D Only partial schematic diagrams are depicted, and the substrate may include any number of structural portions having the aspects depicted in the figures, as well as alternative structural aspects that may still benefit from operation of the present technology.

[0036] The method 200 may or may not involve designing the semiconductor structure as an optional operation of a particular manufacturing operation. It should be understood that the method 200 may be performed on any number of semiconductor structures or substrates 305, such as Figure 3A As shown, an exemplary structure including an exemplary structure on which a selectively deposited material may be formed. Figure 3A As shown, substrate 305 may have multiple material layers deposited overlying the substrate. In embodiments, substrate 305 may have a substantially planar surface or an uneven surface. Substrate 305 may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon on insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, sapphire, or other substrate materials. Substrate 305 may have various sizes, such as 200 mm or 300 mm diameter wafers, and rectangular or square panels.

[0037] Structure 300 may depict a partial view of a stack of alternating material layers that may be used in 3D NAND memory formation in some embodiments. The alternating material layers may be produced by any number of methods, including plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermal enhanced chemical vapor deposition, or any other formation technique. In some embodiments, plasma enhanced chemical vapor deposition may be performed in a processing chamber, such as processing chamber 100 described above. Although the remainder of the disclosure will generally discuss stacks of alternating oxide layers and nitride layers, embodiments of the present technology may use different combinations of materials, such as silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials. Additionally, according to embodiments of the present technology, any number of material layers may be produced in a stack or any portion of any stack, and different portions of a stack may include more, less, or a similar number of layers as any other portion of the stack.

[0038] like Figure 3AAs shown, structure 300 may include a substrate 305 having a stack of alternating material layers. The illustrated stack may include a plurality of portions 310, each of which may include at least one oxide material layer 317 and at least one nitride material layer 319. Each portion may also include multiple pairs of layers, including greater than or about 2 pairs, greater than or about 10 pairs, greater than or about 50 pairs, greater than or about 100 pairs, or more pairs of layers. In general, structure 300 may include at least 16 layers of alternating oxide material layers 317 and nitride material layers 319 and may include at least 32 layers, at least 64 layers, at least 128 layers, or more layers. Any specific number of correspondences encompassed by any of these stated ranges is understood as if specifically stated herein. Although three portions 310A, 310B, and 310C are shown, some embodiments according to the present technology may include more or fewer portions.

[0039] In some embodiments, multiple portions 310, including all portions 310, may be formed during a single deposition sequence. Additionally, in some embodiments, the portions may be produced in multiple operations. Prior to forming a portion of a memory hole or other feature through the structure, a masking material 315 may be formed on any of the stacked portions. Figure 3B As shown, once these layers are formed and a mask material 315 is deposited on the structure, a memory hole can be etched through the structure. The etching process can be any type of etching, and in some embodiments, the etching process can be or include a reactive ion etching process. The etching operation can extend through the third portion 310C of the stack, the second portion 310B of the stack, and at least partially through the first portion 310A of the stack. Although in some embodiments, the characteristics of the material can be characterized by a larger aspect ratio, the structure according to the present technology can be characterized by any aspect ratio or height-to-width ratio of the structure. For example, in some embodiments, the aspect ratio of the exemplary structure (such as the depth of the hole or memory hole relative to the cross-sectional diameter) can be greater than or about 10:1, greater than or about 20:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater.

[0040] refer to Figure 3C, method 200 may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber at operation 205. Silicon-containing precursors that may be used may include, but are not limited to, monosilane (SiH4), disilane (Si2H6), trisilane (Si3H8), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethoxysilane (TEOS), and any other silicon-containing precursor that may be used for silicon-containing film formation. In an embodiment, method 200 may further include forming a plasma of the silicon-containing precursor in the processing region. In an embodiment, the plasma of the silicon-containing precursor may be formed by providing RF power to a faceplate to generate a plasma in the processing region, although any other processing chamber capable of generating a plasma may be similarly used.

[0041] The method 200 may include forming a first silicon-containing material 320 on the substrate in an optional operation 210. The first silicon-containing material 320 may be referred to as a first material layer. The first material layer may include a silicon-containing material, such as amorphous silicon. The first material layer may include other components and may not be a pure silicon material. The first material layer may extend into one or more grooves in the alternating material layers formed on the substrate 305. The first silicon-containing material 320 may reduce or prevent materials (such as halogen materials in the silicon-containing and halogen materials discussed below) from entering the alternating layers (such as dielectric materials) of the portion 310. If a large amount of halogen material enters the alternating layers of the portion 310, the device may be damaged or destroyed due to high leakage and / or instability.

[0042] After depositing the first silicon-containing material 320 to a sufficient thickness, the method may include providing a halogen-containing precursor to a processing region of a semiconductor processing chamber at operation 215. The halogen-containing precursor may include fluorine, chlorine, bromine, or any other halogen or combination of halogens. The halogen-containing precursors that may be used may include, but are not limited to, nitrogen trifluoride (NF3) and silicon tetrafluoride (SiF4), as well as any other halogen-containing precursors that may be used for silicon-containing and halogen film formation. In an embodiment, the method 200 may also include forming a plasma of a halogen-containing precursor in the processing region. As previously discussed, although any other processing chamber capable of generating a plasma may be similarly used, the plasma of the halogen-containing precursor may be similarly formed by providing RF power to a faceplate to generate a plasma in the processing region. The halogen-containing precursor may be provided together with the silicon-containing precursor. It is contemplated that the silicon-containing precursor provided together with the halogen-containing precursor may be the same precursor or a different precursor provided at operation 205. It is also contemplated that the halogen-containing precursor may include sufficient silicon content, thereby avoiding the need to provide both a silicon-containing precursor and a halogen-containing precursor.

[0043] The method 200 may include forming a silicon-containing and halogen material 325 on the substrate at operation 220. The silicon-containing and halogen material 325 may be simply referred to as a second material layer. The second material layer may include a silicon-containing and halogen material. In an embodiment, the silicon-containing and halogen material may include a silicon-containing and fluorine material, a silicon-containing and chlorine material, a silicon-containing and bromine material, or any other halogen material. The silicon-containing and halogen material 325 may extend into one or more grooves formed in the alternating material layers. The silicon-containing and halogen material 325 may overlie the first silicon-containing material 320.

[0044] In an embodiment, the method 200 may include reducing or stopping the flow of the halogen-containing precursor after forming the silicon-containing and halogen-containing material 325 at operation 225. If reduced or stopped during operations 215 and 220, the flow of the silicon-containing precursor from operation 205 may be maintained, increased, or restored. The silicon-containing precursor used to form the first silicon-containing material 320 may be the same as the precursor used to form the second silicon-containing material 330, which will be discussed further below. However, it is contemplated that different silicon-containing precursors may be used to form the first silicon-containing material 320 and the second silicon-containing material 330.

[0045] The method 200 may include forming a second silicon-containing material 330 at optional operation 230. The second silicon-containing material 330 may be simply referred to as a third material layer. The third material layer may include a silicon-containing material, such as amorphous silicon. The second material layer may include other components and may not be a pure silicon material. The second silicon material 330 may extend into one or more grooves formed in the alternating material layers. The second silicon-containing material 330 may overlie the silicon-containing and halogen material 325. The second silicon-containing material 330 may protect the first silicon-containing material 320, the silicon-containing and halogen material 325, or both from moisture and oxygen. The second silicon-containing material 330 may be used as a protective layer to improve process stability.

[0046] The first silicon-containing material 320 and the second silicon-containing material 330 may have substantially similar thicknesses. For example, the first silicon-containing material 320 and the second silicon-containing material 330 may be characterized by a thickness within about 5 nm of each other, and may have a thickness within about 4 nm of each other, within about 3 nm of each other, within about 2 nm of each other, within about 1 nm of each other, or less. In an embodiment, the first material layer, the second material layer, or both may be characterized by a thickness of less than or about 10 nm, such as less than or about 8 nm, less than or about 6 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, or less.

[0047] The silicon-containing and halogen material 325 may be characterized by a thickness greater than the thickness of the first silicon-containing material 320 and the second silicon-containing material 330. In an embodiment, the silicon-containing and halogen material 325 may be characterized by a thickness less than or about 60 nm. The thickness of the silicon-containing and halogen material 325 may depend on the desired amount of halogen material between the first silicon-containing material 320 and the second silicon-containing material 330. Therefore, in an embodiment, the silicon-containing and halogen material 325 may be characterized by a thickness less than or about 55 nm, such as less than or about 50 nm, less than or about 45 nm, less than or about 40 nm, less than or about 37 nm, less than or about 35 nm, less than or about 32 nm, less than or about 30 nm, less than or about 25 nm, less than or about 20 nm, less than or about 15 nm, less than or about 10 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, or less.

[0048] The deposition at operations 210, 220, and 230 may be performed at a chamber, substrate, or pedestal temperature of less than or about 700° C. Thus, in some embodiments, deposition may occur at a temperature of less than or about 675° C., less than or about 650° C., less than or about 625° C., less than or about 600° C., less than or about 575° C., less than or about 550° C., less than or about 525° C., less than or about 500° C., less than or about 475° C., less than or about 450° C., less than or about 425° C., less than or about 400° C., less than or about 375° C., less than or about 350° C., less than or about 325° C., less than or about 300° C., less than or about 275° C., less than or about 250° C., less than or about 225° C., less than or about 200° C., or less.

[0049] Additionally, the deposition at operations 210, 220, and 230 may be performed at a pressure of less than or about 300 Torr, such as less than or about 280 Torr, less than or about 260 Torr, less than or about 240 Torr, less than or about 220 Torr, less than or about 200 Torr, less than or about 180 Torr, less than or about 160 Torr, less than or about 140 Torr, less than or about 120 Torr, less than or about 100 Torr, less than or about 80 Torr, less than or about 60 Torr, less than or about 40 Torr, less than or about 20 Torr, less than or about 15 Torr, less than or about 10 Torr, less than or about 7 Torr, less than or about 5 Torr, less than or about 3 Torr, or lower.

[0050] Operations 210, 220, and 230 may be formed under the same or similar process conditions. For example, the temperature and / or pressure for each of the formation of the first silicon-containing material 320, the silicon-containing and halogen material 325, and the second silicon-containing material 330 may be maintained. Conversely, the temperature and / or pressure may be modified or adjusted between the formation of the first silicon-containing material 320, the silicon-containing and halogen material 325, and the second silicon-containing material 330.

[0051] refer to Figure 3D, an optional anneal may be performed on the substrate 305 and the formed film at operation 235, which may increase the temperature of the formed film. The annealing may be performed after forming the second silicon-containing material 330. The annealing may include increasing the temperature of the structure 300 to greater than or about 500° C., and this may increase the temperature of the structure 300 to greater than or about 550° C., greater than or about 600° C., greater than or about 650° C., greater than or about 700° C., greater than or about 750° C., greater than or about 800° C., greater than or about 850° C., greater than or about 900° C., or more. During the annealing, at least a portion of the first silicon-containing material 320 and the second silicon-containing material 330 may be transformed from, for example, amorphous silicon to polycrystalline silicon. During the annealing, greater than or about 95.0 volume % of the amorphous silicon may be transformed into polycrystalline silicon, such as greater than or about 97.0%, greater than or about 99.0%, greater than or about 99.9%, or more. The polysilicon may include grains of crystalline silicon separated by regions of amorphous silicon, or grain boundaries. Depending on the depth of the channel, the polysilicon may include between one and about five grain boundaries. However, depending on the size, it is contemplated that the polysilicon may include more than five grain boundaries. The grain boundaries may act as scattering centers that may reduce channel conductance and string current. In addition, the halogen material within the silicon-containing and halogen material 325 may diffuse into the first silicon-containing material 320 and the second silicon-containing material 330. The first silicon-containing material 320, the silicon-containing and halogen material 325, and the second silicon-containing material 330 may be collectively referred to as annealing materials.

[0052] By incorporating the silicon-containing and halogen material 325 between the first silicon-containing material 320 and the second silicon-containing material 330, the halogen material may diffuse into the first silicon-containing material 320, the second silicon-containing material 330, or both during the annealing at operation 235. Depending on the conditions of the annealing at operation 235, the halogen material may be uniformly distributed into the first silicon-containing material 320, the second silicon-containing material 330, or both. However, it is contemplated that the halogen material may not be completely uniformly distributed, and there may be a concentration gradient between the silicon-containing and halogen material 325 and the first silicon-containing material 320, the second silicon-containing material 330, or both. When there is a concentration gradient, there may be a higher concentration in the case where the silicon-containing and halogen-containing material 325 is present before the annealing relative to the case where the first silicon-containing material 320, the second silicon-containing material 330, or both are present before the annealing. As the halogen material diffuses into the polysilicon, the thin film transistor characteristics of the polysilicon may be improved. Halogens can bind to silicon and passivate trap states in the silicon bandgap, resulting in a polysilicon channel with stronger bonding than conventional technology. In conventional technology, more silicon in the polysilicon channel can bind to hydrogen, which has a lower bonding energy than halogen-bound silicon. The increased bonding energy between silicon and halogens can reduce the density of trap states via passivation, thereby breaking the tradeoff between string current and threshold voltage change in a polysilicon channel with reduced thickness. In addition, the increased bonding energy between silicon and halogens can extend the useful life of the device because the bond is less likely to be broken by passing electrons during operation.

[0053] After annealing the substrate, the method 200 may include removing a portion of the annealed material 335 at operation 240, and the annealed material may include a polysilicon material. As previously discussed, the annealed material 335 may include a first silicon-containing material 320, a silicon-containing and halogen-containing material 325, and a second silicon-containing material 330. The process for removing a portion of the annealed material 335 may be any type of etching process, and in some embodiments, the process may be or include wet etching. In the case of annealing a thicker material, the grain size within the annealed material 335 (such as polysilicon) may be larger and the grain boundaries may be reduced. In the case of a larger grain size, and therefore a reduced grain boundary, the string current in the final device may increase. If a thinner material is annealed, and an etching process for removing a portion of the annealed material is not required, the grain size within the annealed material may be smaller, thereby sacrificing the conductive path and reducing the string current. In addition, the threshold voltage variation may be improved by removing a portion of the annealed material 335 to thin the channel, because there may be less defect variability in the thinner channel.

[0054] Still reference Figure 3D, some embodiments of the present technology relate to semiconductor structures. As previously discussed, these structures may include a substrate 305 having alternating layers of materials (such as oxide materials 317 and nitride materials 319) formed on the substrate 305. One or more grooves may be formed in the alternating material layers. The polysilicon material 335 may extend into the one or more grooves. The polysilicon material 335 may include a first surface 337. A second surface 339 of the polycrystalline material opposite to the first surface 337 of the polysilicon material 335 may overlie and contact the alternating material layers. The polysilicon material 335 may include halogens. A portion of the polysilicon material 335 disposed between the first surface 337 and the second surface 339 may have a higher concentration of halogen atoms than the first surface 337 and the second surface 339. For example, a portion of the polysilicon material 335 disposed between the first surface 337 and the second surface 339 may have a halogen concentration between about 1 atomic percent and about 5 atomic percent compared to the halogen concentration at the first surface 337 and / or the second surface 339. However, it is contemplated that the difference in halogen concentration between the first surface 337 and / or the second surface 339 and the portion of the polysilicon material 335 intermediate the first surface 337 and the second surface 339 may be greater than or about 5 atomic percent. The polysilicon material 335 may be characterized by a thickness of less than or about 30 nm, such as less than or about 28 nm, less than or about 26 nm, less than or about 24 nm, less than or about 22 nm, less than or about 20 nm, less than or about 18 nm, less than or about 16 nm, less than or about 14 nm, less than or about 12 nm, less than or about 10 nm, less than or about 8 nm, less than or about 6 nm, less than or about 4 nm, less than or about 2 nm, or less.

[0055] By utilizing one or more of the described processes, improved electrical performance in 3D NAND can be provided, which can limit the difficulties associated with scaling and increased layers in the 3D NAND stack. Thus, the present technology can provide improved manufacturing that can produce devices that perform better than conventional technologies.

[0056] In the foregoing description, for the purpose of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0057] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessarily obscuring the present technology, many well-known processes and elements are not described. Therefore, the above description should not be considered to limit the scope of the present technology. In addition, methods or processes may be described as sequential or step-by-step, but it should be understood that operations may be performed concurrently or in an order different from the order listed.

[0058] In the case of providing a numerical range, it is understood that unless the context clearly indicates otherwise, each intermediate value between the upper and lower limits of the range is also specifically disclosed, reaching the minimum fraction of the lower limit unit. Any narrower range between any stated value or unstated intermediate value and any other stated value or intermediate value in the stated range is included in the stated range. The upper and lower limits of those smaller ranges can be independently included or excluded from the range, and each range in which any limit, no limit, or two limits are included in the smaller range is also included in the present technology, depending on any specifically excluded limit in the stated range. In the case where the stated range includes one or both of the limits, the scope of excluding any or both of those included limits is also included.

[0059] As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to a "silicon-containing precursor" includes a plurality of such precursors and reference to "a first material layer" includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0060] Furthermore, when used in this specification and the appended claims, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)” and “including” are intended to specify the presence of stated features, integers, components or operations, but they do not exclude the presence or addition of one or more other features, integers, components, operations, acts or groups.

Claims

1. A semiconductor processing method, the semiconductor processing method comprising: providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber, wherein alternating material layers are formed on the substrate; and wherein one or more recesses are formed in the alternating material layers; providing a halogen-containing precursor to the processing region of the semiconductor processing chamber; A silicon-and-halogen containing material is formed, wherein the silicon-and-halogen containing material extends into the one or more recesses formed in the alternating material layers and overlies the alternating material layers.

2. The semiconductor processing method of claim 1, wherein the temperature within the semiconductor processing chamber is maintained at less than or about 700°C.

3. The semiconductor processing method of claim 1, wherein the pressure within the semiconductor processing chamber is maintained at less than or about 300 Torr. 4 . The semiconductor processing method of claim 1 , wherein the silicon-containing precursor comprises monosilane, disilane, dichlorosilane or trisilane.

5. The semiconductor processing method according to claim 1, wherein: The halogen-containing precursor includes fluorine; and The silicon-and-halogen-containing material includes a silicon-and-fluorine-containing material.

6. The semiconductor processing method of claim 1, wherein the halogen-containing precursor comprises nitrogen trifluoride or silicon tetrafluoride.

7. The semiconductor processing method according to claim 1, further comprising: forming a first silicon-containing material before forming the silicon-and-halogen-containing material, wherein the first silicon-containing material extends into the one or more recesses formed in the alternating material layers; forming a second silicon-containing material, wherein the second silicon-containing material overlies the silicon-and-halogen containing material; or Both the first silicon-containing material and the second silicon-containing material are formed.

8. The semiconductor processing method of claim 1, wherein the silicon and halogen containing material is characterized by a thickness of less than or about 60 nm.

9. The semiconductor processing method according to claim 7, further comprising: The substrate is annealed after forming the second silicon-containing material.

10. The semiconductor processing method according to claim 9, wherein: During the annealing, a halogen material within the silicon-and-halogen containing material diffuses into the first silicon-containing material, the second silicon-containing material, or both.

11. A semiconductor processing method, the semiconductor processing method comprising: forming a first material layer in one or more recesses defined in alternating material layers on a substrate in a processing region of a semiconductor processing chamber, wherein the first material layer is a first silicon-containing material, forming a second material layer on the first material layer, wherein the second material layer is a material containing silicon and fluorine; as well as A third material layer is formed on the second material layer, wherein the third material layer is a second silicon-containing material.

12. The semiconductor processing method of claim 11, wherein: The temperature within the semiconductor processing chamber is maintained at less than or about 700° C.; and The pressure within the semiconductor processing chamber is maintained at less than or about 300 Torr.

13. The semiconductor processing method of claim 11, wherein: The alternating material layers include alternating oxide material layers and nitride material layers; and The substrate includes greater than 16 alternating layers of material.

14. The semiconductor processing method of claim 11, wherein the second material layer is characterized by a thickness greater than a thickness of the first material layer and the third material layer.

15. The semiconductor processing method of claim 11, wherein the second material layer is characterized by a thickness between about 2 nm and about 30 nm.

16. The semiconductor processing method according to claim 11, further comprising: The substrate is annealed after forming the first material layer, the second material layer, and the third material layer.

17. The semiconductor processing method of claim 16, wherein: The first material layer, the third material layer, or both include amorphous silicon; and The annealing converts at least a portion of the amorphous silicon into polycrystalline silicon.

18. The semiconductor processing method according to claim 16, further comprising: After annealing the substrate, a portion of the first silicon-containing material, the silicon-and-halogen-containing material, and the second silicon-containing material are removed.

19. A semiconductor structure, comprising: a substrate having alternating layers of material formed on the substrate; and wherein one or more grooves are formed in said alternating layers of material; as well as A polysilicon material extending into the one or more grooves, wherein a second surface of the polysilicon material opposite the first surface of the polysilicon material overlies the alternating material layers, wherein the polysilicon material includes a halogen, and wherein a portion of the polysilicon material disposed intermediate the first surface and the second surface has a higher concentration of halogen atoms than the first surface and the second surface.

20. The semiconductor structure of claim 19, wherein: The polysilicon material is characterized by a thickness of less than or about 30 nm.

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