IGBT defect location method and system based on gate voltage during turn-off process

Abstract

The present application provides an IGBT defect location method and system based on the gate voltage of the shutdown process, the method comprising: obtaining the total number of chips and detection data of the target IGBT, the detection data comprising: the normal gate voltage, the actual gate voltage, the first normal duration, the first actual duration, the second normal duration and the second actual duration in the Miller platform phase of the shutdown process during the gate voltage drop phase of the shutdown process; according to the total number of chips and the detection data of the target IGBT, the internal defect location of the target IGBT is completed. The present application can realize the location of the internal defects of the IGBT, which is convenient for the subsequent maintenance of the IGBT.

Description

Technical Field

[0001] The present application relates to the technical field of IGBT defect detection, and in particular to an IGBT defect locating method and system based on gate voltage during a turn-off process. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor and an insulated gate field effect transistor. With the development of electronic technology, the application of insulated gate bipolar transistors is becoming more and more extensive, such as in new energy converters, flexible DC transmission equipment, and dynamic reactive power compensation equipment. Therefore, it is very meaningful to detect defects in IGBTs.

[0003] At present, the main focus is on detecting whether defects have occurred inside the IGBT. The detection method is single and cannot locate the internal defects of the IGBT. For example, analyzing the defect situation through the gate discharge charge can partially reflect whether defects have occurred inside the IGBT, but it cannot determine the internal defects of the IGBT. Summary of the invention

[0004] In response to at least one problem in the prior art, the present application proposes an IGBT defect locating method and system based on the gate voltage during the shutdown process, which can locate the internal defects of the IGBT and facilitate the subsequent maintenance of the IGBT.

[0005] In order to solve the above technical problems, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides an IGBT defect location method based on gate voltage during a turn-off process, comprising:

[0007] Obtaining the total number of chips and detection data of the target IGBT, wherein the detection data includes: a normal gate voltage in a gate voltage drop phase of the shutdown process, an actual gate voltage, a first normal duration, a first actual duration, a second normal duration and a second actual duration in a Miller platform phase of the shutdown process;

[0008] According to the total number of chips and detection data of the target IGBT, complete the internal defect location of the target IGBT;

[0009] The method of completing the internal defect location of the target IGBT according to the total number of chips of the target IGBT and the detection data includes:

[0010] Detecting whether the actual gate voltage is greater than the normal gate voltage, and if so, locating the internal defect of the target IGBT as a first gate-emitter loop defect;

[0011] Detecting whether the first actual duration is less than the first normal duration, and if so, locating the internal defect of the target IGBT as a second gate-emitter loop defect;

[0012] Detecting whether the second actual duration is less than the second normal duration, and if so, locating the internal defect of the target IGBT as a collector gate loop defect;

[0013] The IGBT defect location method based on the gate voltage during the turn-off process further includes:

[0014] If the internal defect includes a first gate-emitter loop defect, a second gate-emitter loop defect, and a collector-gate loop defect, then determining that the target IGBT is a gate defect;

[0015] If the internal defect includes a first gate-emitter loop defect and a second gate-emitter loop defect, but does not include a collector-gate loop defect, then the target IGBT is determined to be an emitter defect;

[0016] If the internal defect includes a collector-gate loop defect but does not include a first gate-emitter loop defect and a second gate-emitter loop defect, then the target IGBT is determined to be a collector defect;

[0017] After locating the internal defect of the target IGBT as a first gate-emitter loop defect, the method further includes:

[0018] Determine the number of chips of the target IGBT having a first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage;

[0019] After locating the internal defect of the target IGBT as a second gate-emitter loop defect, the method further includes:

[0020] Determine the number of chips of the target IGBT having a second gate-emitter loop defect according to the first normal duration, the first actual duration and the total number of chips;

[0021] After locating the internal defect of the target IGBT as a collector gate loop defect, the method further includes:

[0022] Determine the number of chips of the target IGBT having collector-gate loop defects according to the second normal duration and the second actual duration and the total number of chips;

[0023] The obtaining of the total number of target IGBT chips and detection data includes:

[0024] Obtain the total number of target IGBT chips, actual gate voltage and collector-emitter voltage waveforms, and gate voltage and collector-emitter voltage waveforms in a normal state;

[0025] If there is a stage in which the gate voltage changes and the collector-emitter voltage does not change in the actual gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the gate voltage falling stage, and the corresponding duration is the first actual duration of the gate voltage falling stage, and the corresponding gate voltage is the actual gate voltage in the gate voltage falling stage; if there is a stage in which the gate voltage does not change and the collector-emitter voltage changes in the actual gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the Miller platform stage, and the corresponding duration is the second actual duration of the Miller platform stage;

[0026] If, in the gate voltage and collector-emitter voltage waveforms in the normal state, there is a stage in which the gate voltage changes but the collector-emitter voltage does not change, then this stage is determined to be the gate voltage falling stage, the corresponding duration is the first normal duration of the gate voltage falling stage, and the corresponding gate voltage is the normal gate voltage in the gate voltage falling stage; if, in the gate voltage and collector-emitter voltage waveforms in the normal state, there is a stage in which the gate voltage does not change but the collector-emitter voltage changes, then this stage is determined to be the Miller platform stage, and the corresponding duration is the second normal duration of the Miller platform stage.

[0027] In one embodiment, determining the number of chips of the target IGBT having the first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage includes:

[0028] The number of chips with the first gate-emitter loop defect is determined by the following formula: m 1:

[0029]

[0030] Where n represents the total number of chips. u miller represents the normal gate voltage, u miller，fault represents the actual gate voltage, U T Represents the gate threshold voltage.

[0031] In one embodiment, determining the number of chips of the target IGBT having the second gate-emitter loop defect according to the first normal duration, the first actual duration and the total number of chips includes:

[0032] Determine the number of chips with the second gate-emitter loop defect in the target IGBT according to the following formula: m 2:

[0033]

[0034] Where n represents the total number of chips, ΔtA = t A,fault - t A , t A,fault Indicates the first actual duration, t A Indicates the first normal duration.

[0035] In one embodiment, determining the number of chips of the target IGBT having collector-gate loop defects according to the second normal duration, the second actual duration and the total number of chips includes:

[0036] The number of chips with collector gate loop defects is determined according to the following formula: m 3:

[0037]

[0038] Where n represents the total number of chips. t B,faul Indicates the second actual duration, t B Indicates the second normal duration.

[0039] In a second aspect, the present application provides an IGBT defect location system based on gate voltage during a turn-off process, comprising:

[0040] An acquisition device is used to acquire the total number of chips and detection data of the target IGBT, wherein the detection data includes: a normal gate voltage, an actual gate voltage, a first normal duration, a first actual duration, a second normal duration and a second actual duration in a Miller platform phase of the shutdown process during a gate voltage drop phase of the shutdown process;

[0041] A detection device, used for completing the internal defect location of the target IGBT according to the total number of chips of the target IGBT and the detection data;

[0042] The detection device comprises:

[0043] A first detection module is used to detect whether the actual gate voltage is greater than the normal gate voltage, and if so, locate the internal defect of the target IGBT as a first gate-emitter loop defect;

[0044] A second detection module is used to detect whether the first actual duration is less than a first normal duration, and if so, the internal defect of the target IGBT is located as a second gate-emitter loop defect;

[0045] A third detection module is used to detect whether the second actual duration is less than the second normal duration, and if so, the internal defect of the target IGBT is located as a collector gate loop defect;

[0046] The IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0047] A first positioning device, used for determining that the target IGBT is a gate defect if the internal defect includes a first gate-emitter loop defect, a second gate-emitter loop defect and a collector-gate loop defect;

[0048] A second positioning device, for determining that the target IGBT is an emitter defect if the internal defect includes a first gate-emitter loop defect and a second gate-emitter loop defect, but does not include a collector-gate loop defect;

[0049] A third positioning device, for determining that the target IGBT is a collector defect if the internal defect includes a collector gate loop defect but does not include a first gate emitter loop defect and a second gate emitter loop defect;

[0050] The IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0051] A first quantity determining device, for determining the number of chips of the target IGBT having a first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage;

[0052] The IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0053] A second quantity determining device, used for determining the number of chips of the target IGBT having a second gate-emitter loop defect according to the first normal duration, the first actual duration and the total number of chips;

[0054] The IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0055] A third quantity determining device, used for determining the number of chips of the target IGBT having collector gate loop defects according to the second normal duration and the second actual duration and the total number of chips;

[0056] The acquisition device comprises:

[0057] An acquisition module is used to acquire the total number of target IGBT chips, actual gate voltage and collector-emitter voltage waveforms, and gate voltage and collector-emitter voltage waveforms in a normal state;

[0058] The first determination module is used to determine that if there is a stage in which the gate voltage changes and the collector-emitter voltage does not change in the actual gate voltage and collector-emitter voltage waveforms, the stage is determined to be a gate voltage falling stage, and the corresponding duration is the first actual duration of the gate voltage falling stage, and the corresponding gate voltage is the actual gate voltage in the gate voltage falling stage; if there is a stage in which the gate voltage does not change and the collector-emitter voltage changes in the actual gate voltage and collector-emitter voltage waveforms, the stage is determined to be a Miller platform stage, and the corresponding duration is the second actual duration of the Miller platform stage;

[0059] The second determination module is used to determine that if there is a stage in which the gate voltage changes and the collector-emitter voltage does not change in the gate voltage and collector-emitter voltage waveforms in the normal state, then the stage is determined to be the gate voltage falling stage, and the corresponding duration is the first normal duration of the gate voltage falling stage, and the corresponding gate voltage is the normal gate voltage in the gate voltage falling stage; if there is a stage in which the gate voltage does not change and the collector-emitter voltage changes in the gate voltage and collector-emitter voltage waveforms in the normal state, then the stage is determined to be the Miller platform stage, and the corresponding duration is the second normal duration of the Miller platform stage.

[0060] In one embodiment, the first quantity determining device is used to:

[0061] The number of chips with the first gate-emitter loop defect is determined by the following formula: m 1:

[0062]

[0063] Where n represents the total number of chips. u miller represents the normal gate voltage, u miller，fault represents the actual gate voltage, U T Represents the gate threshold voltage.

[0064] In one embodiment, the second quantity determining device is used to:

[0065] Determine the number of chips with the second gate-emitter loop defect in the target IGBT according to the following formula: m 2:

[0066]

[0067] Where n represents the total number of chips, Δt A = t A,fault - t A , t A,fault Indicates the first actual duration, tA Indicates the first normal duration.

[0068] In one embodiment, the third quantity determining device is used to:

[0069] The number of chips with collector gate loop defects is determined according to the following formula: m 3:

[0070]

[0071] Where n represents the total number of chips. t B,faul Indicates the second actual duration, t B Indicates the second normal duration.

[0072] In a third aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the IGBT defect location method based on the gate voltage during the shutdown process is implemented.

[0073] In a fourth aspect, the present application provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the IGBT defect locating method based on the gate voltage during the turn-off process.

[0074] It can be seen from the above technical solution that the present application provides an IGBT defect positioning method and system based on the gate voltage during the shutdown process, which can realize the positioning of internal defects of the IGBT and facilitate the subsequent maintenance of the IGBT. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0076] Figure 1 It is a first flow chart of the IGBT defect location method based on the gate voltage during the turn-off process in the embodiment of the present application;

[0077] Figure 2 is a schematic diagram of the commutation circuit structure of the half-bridge circuit model in the embodiment of the present application;

[0078] Figure 3 is a schematic diagram of the internal structure of the IGBT in the embodiment of the present application;

[0079] Figure 4is a schematic diagram of the IGBT shutdown process in an embodiment of the present application;

[0080] Figure 5 It is a second flow chart of the IGBT defect location method based on the gate voltage during the turn-off process in the embodiment of the present application;

[0081] Figure 6 It is a first structural schematic diagram of an IGBT defect location system based on gate voltage during a turn-off process in an embodiment of the present application;

[0082] Figure 7 is a second structural schematic diagram of the IGBT defect location system based on the gate voltage during the turn-off process in an embodiment of the present application;

[0083] Figure 8 A schematic block diagram of the system structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0084] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0085] In order to solve the problems existing in the above-mentioned prior art, the embodiment of the present application provides an IGBT defect location method and system based on the gate voltage during the shutdown process, which can be used to locate the gate voltage of the IGBT device during the shutdown process. u GE Waveform analysis can be used to determine whether a device has defects and the location of the defects, which has a certain guiding significance for IGBT status detection. By analyzing the gate voltage waveform during the shutdown process, the shutdown process can be divided into the gate voltage drop stage and the Miller platform stage, and the response of the gate voltage waveform to the collector, emitter, and gate defects in each stage can be studied separately. The gate voltage characteristics of the two stages of the shutdown process can be combined to locate defects at different locations inside the IGBT, which can enhance the depth of understanding of the internal defects of the IGBT and has a certain value for the performance detection of IGBT devices.

[0086] The details are described through the following embodiments.

[0087] In order to locate the internal defects of the IGBT and facilitate the subsequent maintenance of the IGBT, this embodiment provides an IGBT defect location method based on the gate voltage of the shutdown process, which is an IGBT defect location system based on the gate voltage of the shutdown process. The IGBT defect location system based on the gate voltage of the shutdown process includes but is not limited to a server, such as Figure 1 As shown, the method specifically includes the following contents:

[0088] Step 100: Obtain the total number of chips and detection data of the target IGBT, the detection data including: normal gate voltage in the gate voltage drop phase of the shutdown process, actual gate voltage, first normal duration, first actual duration, second normal duration and second actual duration in the Miller platform phase of the shutdown process.

[0089] Specifically, the normal gate voltage may represent the Miller platform value of the gate voltage of the insulated gate bipolar transistor in the gate voltage falling stage under normal conditions; the actual gate voltage may represent the Miller platform value of the gate voltage of the insulated gate bipolar transistor in the gate voltage falling stage. The first normal duration may be the duration of the insulated gate bipolar transistor in the gate voltage falling stage under normal conditions; the first actual duration may be the actual duration of the insulated gate bipolar transistor in the gate voltage falling stage. The second normal duration may be the duration of the insulated gate bipolar transistor in the Miller platform stage under normal conditions; the second actual duration may be the actual duration of the insulated gate bipolar transistor in the Miller platform stage. The shutdown process may include: a shutdown delay process, the gate voltage falling stage may be the gate voltage falling stage of the shutdown delay process, and the Miller platform stage may be the Miller platform stage of the shutdown delay process.

[0090] Specifically, the actual gate voltage and collector-emitter voltage of the target IGBT can be obtained u CEThe gate voltage and collector-emitter voltage waveforms of the target IGBT in a normal state can be obtained and the normal duration of the gate voltage falling phase and the normal duration of the Miller platform phase can be determined based on them. If the gate voltage changes and the collector-emitter voltage does not change in the actual gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the gate voltage falling stage, and the corresponding duration is the actual duration of the gate voltage falling stage; if the gate voltage does not change and the collector-emitter voltage changes in the actual gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the Miller platform stage, and the corresponding duration is the actual duration of the Miller platform stage; if the gate voltage changes and the collector-emitter voltage does not change in the normal state gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the gate voltage falling stage, and the corresponding duration is the normal duration of the gate voltage falling stage; if the gate voltage does not change and the collector-emitter voltage changes in the normal state gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the Miller platform stage, and the corresponding duration is the normal duration of the Miller platform stage. The gate voltage falling stage and the Miller platform stage can also be determined based on the gate voltage waveform, and the stage where the gate voltage changes for the first time is determined as the gate voltage falling stage, and the stage where the gate voltage remains unchanged after the initial change is determined as the Miller platform stage.

[0091] Specifically, Figure 2 The commutation circuit structure of the half-bridge circuit model including IGBT, u GE is the gate voltage, u CE is the collector-emitter voltage, u chip,CE is the chip collector-emitter voltage, turn-off delay process u chip,CE = u CE , u CG is the collector gate voltage. i C is the collector current, L s,1 is the parasitic inductance of the IGBT circuit, u GE is the device gate voltage. The half-bridge circuit model should include the gate voltage u GE , collector gate voltage u CG and collector-emitter voltage u CE Measurement points of key parameters such as Figure 2 The dotted line box 1 in the figure represents the IGBT, the dotted line 2 represents the collector gate loop, and the dotted line 3 represents the gate emitter loop. The reference direction of voltage and current is Figure 2 Winning bid. L s,F and L s,CE They represent the parasitic parameters of the main circuit inside the FWD device and the IGBT device respectively. L s,F Including parasitic inductance on the FWD anode and cathode sides, L s,CE include L s,C 、L s,E2 part.

[0092] Figure 3 is the internal circuit structure of IGBT, and n is the total number of chips. IGBT device packaging defects can be divided into three categories: gate defects, collector defects, and emitter defects; Figure 3 The mark ① indicates a gate defect. Figure 3 The mark ② indicates a collector defect. Figure 3 The mark ③ indicates an emitter defect. Figure 4 The t0~t2 stage is the turn-off delay process, which includes two stages: ① the gate voltage drop stage (t0~t1), and ② the gate voltage Miller platform stage (t1~t2). Figure 4 The gate voltage is included u GE Waveform and Collector-Emitter Voltage u CE waveform, the collector-emitter voltage u CE The waveform is approximately the collector-gate voltage u CG Waveform.

[0093] Step 200: According to the total number of chips and detection data of the target IGBT, complete the internal defect location of the target IGBT.

[0094] In order to improve the efficiency and convenience of internal defect positioning, Figure 5 As shown, in one embodiment, step 200 includes:

[0095] Step 201: Detect whether the actual gate voltage is greater than the normal gate voltage. If so, locate the internal defect of the target IGBT as a first gate-emitter loop defect.

[0096] Specifically, when the gate voltage Miller platform height u miller Increase (Δ u miller >0), indicating that the IGBT has a gate-emitter loop defect. ,in, umiller represents the normal gate voltage, u miller,fault represents the actual gate voltage. The first gate-emitter loop defect may be a gate-emitter loop defect determined according to the actual gate voltage and the normal gate voltage.

[0097] Step 202: Detect whether the first actual duration is less than the first normal duration. If so, locate the internal defect of the target IGBT as a second gate-emitter loop defect.

[0098] Specifically, when the time t of the process t0~t1 A Shorten (Δt A <0), indicating that the IGBT has a gate-emitter loop defect. Δt A = t A,fault - t A ,in, t A,fault Indicates the first actual duration, t A The second gate-emitter loop defect is a gate-emitter loop defect determined according to the first actual duration and the first normal duration.

[0099] Step 203: Detect whether the second actual duration is less than the second normal duration. If so, locate the internal defect of the target IGBT as a collector-gate loop defect.

[0100] Specifically, when the gate voltage uGE Miller platform process (t1~t2 process) duration t B Shortened, indicating that the collector-gate loop defect occurs in the IGBT. t B = t B - t B,fault >0, where t B,faul Indicates the second actual duration, t B Indicates the second normal duration.

[0101] In order to improve the accuracy of locating internal defects of the IGBT, in one embodiment, the IGBT defect locating method based on the gate voltage during the turn-off process further includes:

[0102] Step 300: If the internal defect includes a first gate-emitter loop defect, a second gate-emitter loop defect, and a collector-gate loop defect, then determining that the target IGBT is a gate defect.

[0103] Step 400: If the internal defect includes a first gate-emitter loop defect and a second gate-emitter loop defect, but does not include a collector-gate loop defect, then it is determined that the target IGBT is an emitter defect.

[0104] Step 500: If the internal defect includes a collector-gate loop defect but does not include a first gate-emitter loop defect and a second gate-emitter loop defect, then it is determined that the target IGBT is a collector defect.

[0105] In order to improve the reliability of determining the number of chips with the first gate-emitter loop defect, in one embodiment, after step 201, it also includes: determining the number of chips with the first gate-emitter loop defect of the target IGBT based on the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage.

[0106] Specifically, the number of chips with the first gate-emitter loop defect can be determined according to the following formula: m 1:

[0107]

[0108] Where n represents the total number of chips. u miller represents the normal gate voltage, u miller，fault represents the actual gate voltage, U T represents the gate threshold voltage, U T It can be preset according to actual needs, and this application does not impose any restrictions on this.

[0109] In order to improve the reliability of determining the number of chips with the second gate-emitter loop defect, in one embodiment, after step 202, it also includes: determining the number of chips with the second gate-emitter loop defect of the target IGBT based on the first normal duration, the first actual duration and the total number of chips.

[0110] Specifically, the number of chips with the second gate-emitter loop defect can be determined according to the following formula: m 2:

[0111]

[0112] Where n represents the total number of chips, Δt A = t A,fault - t A , t A,fault Indicates the first actual duration, t A Indicates the first normal duration.

[0113] In order to improve the reliability of determining the number of chips with collector gate loop defects, in one embodiment, after step 203, it also includes: determining the number of chips with collector gate loop defects in the target IGBT based on the second normal duration, the second actual duration and the total number of chips.

[0114] Specifically, the number of chips with collector gate loop defects can be determined according to the following formula: m 3:

[0115]

[0116] Where n represents the total number of chips. t B,faul Indicates the second actual duration, t B Indicates the second normal duration.

[0117] In order to further improve the reliability of the number of chips, in one embodiment, the IGBT defect locating method based on the gate voltage during the shutdown process may also include: if the target IGBT is a gate defect, then it can be determined whether the number of chips with the first gate-emitter loop defect, the number of chips with the second gate-emitter loop defect and the number of chips with the collector gate loop defect are the same. If so, the number of chips with gate defects can be determined as the number of chips with the collector gate loop defect, otherwise an abnormal warning prompt is output; if the target IGBT is an emitter defect, then it can be determined whether the number of chips with the first gate-emitter loop defect and the number of chips with the second gate-emitter loop defect are the same. If so, the number of chips with emitter defects can be determined as the number of chips with the first gate-emitter loop defect, otherwise an abnormal warning prompt is output; if the target IGBT is a collector defect, then the number of chips with collector defects can be determined as the number of chips with the collector gate loop defect.

[0118] In order to further illustrate the present solution, the present application provides an application example of an IGBT defect location method based on the gate voltage during the turn-off process, which is specifically described as follows:

[0119] During the IGBT turn-off transient process, the gate-emitter capacitance ( C GE ) and Miller capacitance ( C CG ) The current direction is Figure 2 shown.

[0120] 1) For C GE , if the voltage reference direction is G→E, then the process C GE Discharge, gate voltageu GE reduce.

[0121] 2) For C CG , if the voltage reference direction is C→G, then the process C CG Charge, u CG and u CE Increase.

[0122] Gate current i G There is the following relationship with voltage ( Q G Discharge amount for gate of a single chip):

[0123] (1)

[0124] in, n is the total number of chips, C GE is the gate-emitter capacitance, u GE is the gate voltage, C CG is the Miller capacitance, u CG is the collector gate voltage.

[0125] If the collector-gate voltage is taken into account u CG ≈ Collector-Emitter Voltage u CE ,exist:

[0126] (2)

[0127] 1) Gate voltage falling stage ( t 0~ t 1), u GE changes, and u CG No change.

[0128] 2) Miller platform stage ( t 1~ t 2), u CG changes, and u GE No change.

[0129] C GE is a constant (not changing with u GE changes with changes), andC CG is a variable (as u CG or u CE changes with changes).

[0130] The changes in voltage and capacitance at each stage of the shutdown delay process are shown in Table 1:

[0131] Table 1

[0132]

[0133] Considering the changes in voltage and capacitance at different stages, equation (2) can be organized as:

[0134] (3)

[0135] 1. Gate voltage falling stage ( t 0~ t 1):

[0136] The gate voltage at this stage u GE The waveform can be used to analyze gate-emitter (GE) loop defects, which include gate defects and emitter defects.

[0137] Define the gate-emitter loop time constant for a single chip τ 0 is:

[0138] τ 0 =R G,off C ies (4)

[0139] Overall gate loop time constant τ for:

[0140] τ = n × τ 0 =R G,off × nC ies (5)

[0141] In formula (4) R G,off is the gate turn-on resistance, C ies For a single IGBT chip gate input capacitance ( C ies = C GE + C CG ).

[0142] During the gate voltage drop phase ( t 0~ t 1) Due to u CE Maintaining the on-state saturation voltage drop (approximately 3V), the process C CG It can be approximately considered as a constant C CG,sat .

[0143] t 0~ t 1. During the gate discharge process, the following relationship is satisfied:

[0144] (6)

[0145] in, n is the total number of chips, U G,on is the gate supply voltage during the turn-on process, U G,off For the gate supply voltage during the shutdown process, both parameters are fixed and do not change with time.

[0146] Gate voltage u GE Collector current i C The control relationship is:

[0147] (7)

[0148] in, μ n is the electron mobility, α pnp is the transistor transport coefficient, w is the gate channel width, l is the gate channel length, c ox is the gate channel capacitance per unit area, U T is the gate threshold voltage.

[0149] Miller platform height is determined by the load current I L The gate voltage Miller platform value u miller can be equivalent to the normal gate voltage mentioned above, u miller for:

[0150] (8)

[0151] Combining equations (6) and (8), we get the gate voltage uGE from U G,on Reduce to u miller The process time (i.e. t 0~ t 1 time) t A It can be equivalent to the first normal duration mentioned above. t A for:

[0152] (9)

[0153] If the gate (G) or emitter (E) contact defect occurs in the gate-emitter loop, the gate loop discharge time constant will become smaller.

[0154] Referring to equations (3) and (4), when we have m The gate or emitter contact of the IGBT chip package structure is abnormal, and the gate loop time constant changes to:

[0155] τ = ( nm )× τ 0 =R G,off ×( nm ) C ies (10)

[0156] In the above case, the gate voltage Miller platform value u miller,fault can be equivalent to the actual gate voltage mentioned above, u miller,faul for:

[0157] (11)

[0158] Change of gate Miller platform height Δ u miller for:

[0159] (12)

[0160] The following conclusions can be obtained through formula 12:

[0161] Case 1: When the gate voltage Miller platform height u miller Increase (Δ u miller >0), indicating that the IGBT has a gate-emitter (GE) loop defect. Correspondingly, the change in the gate Miller platform height Δ u miller The number of chips with defectsm for:

[0162] (13)

[0163] Gate voltage U G,on From reduced to u miller,fault The process time (i.e. t 0~ t 1 time) t A,fault It can be equivalent to the first actual duration mentioned above. t A,fault for:

[0164] (14)

[0165] Combining equations (9) and (14), we can get: t 0~ t 1The change in time is Δ t A for:

[0166] (15)

[0167] If the change in the height of the Miller platform caused by the defect is not considered, Δ u miller (That is, approximately u miller ≈ u miller,fault ), formula (15) is rearranged to obtain:

[0168] (16)

[0169] The following conclusions can be obtained through formula (16):

[0170] Case 2: When t 0~ t 1. Process time t A Shorten (Δ t A <0), indicating that the IGBT has a gate-emitter (GE) circuit defect.

[0171] Correspondingly, the gate voltage U G,on From reduced to u miller,fault The process ( t 0~ t 1. Process) Time change, the number of defective chips is solved m for:

[0172] (17)

[0173] 2. Miller Platform Stage ( t 1~ t 2):

[0174] The gate current in this stage i G The waveform can be used to analyze collector-gate (GC) loop defects, which include gate defects and collector defects.

[0175] Gate voltage u GE Miller platform continuous process ( t 1~ t 2), Collector-emitter voltage u CE From close to 0 to U DC .

[0176] u CG (or u CE ) is larger, C CG The smaller. C CG and u CE The functional relationship between them is:

[0177] (18)

[0178] in, q is the electron charge, N D is the drift region doping concentration, p SC is the hole concentration across the depletion layer, n SC The electron concentration that crosses the depletion layer is n is the number of chips in parallel, ε is the dielectric constant of silicon material.

[0179] The gate charge during the Miller platform process is:

[0180] (19)

[0181] Miller plateau process gate current i G for:

[0182] (20)

[0183] Gate current flowing through a single chipi G,chip for:

[0184] i G,chip = i G / n (twenty one)

[0185] Considering the Miller platform process u miller Basically no change, so i G is approximately constant.

[0186] when m When a defect occurs in the collector-gate loop (collector or gate) of a chip package structure, the gate current of the Miller platform process i G,fault for:

[0187] (twenty two)

[0188] Gate current flowing through a single chip i G,fault,chip for:

[0189] i G,fault,chip = i G,fault / ( nm ) (twenty three)

[0190] Combining equations (19) to (23), we obtain:

[0191] (twenty four)

[0192] Further rearrangement of formula (24) yields:

[0193] (25)

[0194] If the change in the height of the Miller platform caused by the defect is not considered, Δ u miller (That is, approximately u miller ≈ u miller,fault ), formula (25) is rearranged to obtain:

[0195] (26)

[0196] The following conclusions can be obtained through formula (23):

[0197] Case 3: When the gate voltage uGE Miller platform process ( t 1~ t 2. Duration of the process t B shortened, indicating that the collector-gate (CG) loop defect occurred in the IGBT. The duration of this process t B Change Δ t B for:

[0198] Δ t B =( t B — t B,fault )>0

[0199] Combined with equation (26), the number of defective chips is obtained: m for:

[0200]

[0201] 3. IGBT defect location method:

[0202] Combining Case 1, Case 2, and Case 3, the defect location method of IGBT device is obtained as follows:

[0203] 1) Gate defect: Situations 1, 2, and 3 all exist;

[0204] 2) Collector defect: Cases 1 and 2 do not exist, but case 3 does.

[0205] 3) Emitter defect: Situations 1 and 2 exist, but 3 does not;

[0206] The correspondence between IGBT defect types and corresponding conditions is shown in Table 2, where "√" indicates that the corresponding situation exists and "×" indicates that the corresponding situation does not exist.

[0207] Table 2

[0208]

[0209] From the software level, in order to realize the location of the internal defects of the IGBT and facilitate the subsequent maintenance of the IGBT, the present application provides an embodiment of an IGBT defect location system based on the gate voltage during the shutdown process for realizing all or part of the contents of the IGBT defect location method based on the gate voltage during the shutdown process, see Figure 6 The IGBT defect location system based on the gate voltage during the shutdown process specifically includes the following contents:

[0210] The acquisition device 01 is used to acquire the total number of chips and detection data of the target IGBT, wherein the detection data includes: the normal gate voltage, the actual gate voltage, the first normal duration, the first actual duration, the second normal duration and the second actual duration in the Miller platform phase of the shutdown process during the gate voltage drop phase of the shutdown process;

[0211] The detection device 02 is used to complete the internal defect positioning of the target IGBT according to the total number of chips of the target IGBT and the detection data.

[0212] like Figure 7 As shown, in one embodiment, the detection device comprises:

[0213] A first detection module 021 is used to detect whether the actual gate voltage is greater than the normal gate voltage. If so, the internal defect of the target IGBT is located as a first gate-emitter loop defect;

[0214] A second detection module 022 is used to detect whether the first actual duration is less than a first normal duration, and if so, the internal defect of the target IGBT is located as a second gate-emitter loop defect;

[0215] The third detection module 023 is used to detect whether the second actual duration is less than the second normal duration. If so, the internal defect of the target IGBT is located as a collector gate loop defect.

[0216] In one embodiment, the IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0217] A first positioning device, used for determining that the target IGBT is a gate defect if the internal defect includes a first gate-emitter loop defect, a second gate-emitter loop defect and a collector-gate loop defect;

[0218] A second positioning device, for determining that the target IGBT is an emitter defect if the internal defect includes a first gate-emitter loop defect and a second gate-emitter loop defect, but does not include a collector-gate loop defect;

[0219] The third positioning device is used to determine that the target IGBT is a collector defect if the internal defect includes a collector gate loop defect but does not include a first gate emitter loop defect and a second gate emitter loop defect.

[0220] In one embodiment, the IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0221] The first quantity determining device is used to determine the number of chips of the target IGBT having the first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage.

[0222] In one embodiment, the IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0223] The second quantity determining device is used to determine the number of chips of the target IGBT having the second gate-emitter loop defect according to the first normal duration, the first actual duration and the total number of chips.

[0224] In one embodiment, the IGBT defect location system based on the gate voltage during the turn-off process further includes:

[0225] The third quantity determining device is used to determine the number of chips of the target IGBT having collector-gate loop defects according to the second normal duration, the second actual duration and the total number of chips.

[0226] The embodiment of the IGBT defect location system based on the gate voltage during the shutdown process provided in this specification can be specifically used to execute the processing flow of the embodiment of the IGBT defect location method based on the gate voltage during the shutdown process. Its functions will not be repeated here, and reference can be made to the detailed description of the embodiment of the IGBT defect location method based on the gate voltage during the shutdown process.

[0227] Figure 8 A schematic diagram of the physical structure of an electronic device provided in an embodiment of the present invention, such as Figure 8 As shown, the electronic device includes: a memory 801, a processor 802, and a computer program stored in the memory 801 and executable on the processor 802. When the processor 802 executes the computer program, the following method is implemented:

[0228] Step 100: Obtain the total number of chips and detection data of the target IGBT, the detection data including: normal gate voltage in the gate voltage drop phase of the shutdown process, actual gate voltage, first normal duration, first actual duration, second normal duration and second actual duration in the Miller platform phase of the shutdown process.

[0229] Step 200: According to the total number of chips and detection data of the target IGBT, complete the internal defect location of the target IGBT.

[0230] This embodiment provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following method is implemented:

[0231] Step 100: Obtain the total number of chips and detection data of the target IGBT, the detection data including: normal gate voltage in the gate voltage drop phase of the shutdown process, actual gate voltage, first normal duration, first actual duration, second normal duration and second actual duration in the Miller platform phase of the shutdown process.

[0232] Step 200: According to the total number of chips and detection data of the target IGBT, complete the internal defect location of the target IGBT.

[0233] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0234] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0235] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0236] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0237] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0238] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for locating IGBT defects based on gate voltage during turn-off, characterized in that: include: Obtaining the total number of chips and detection data of the target IGBT, wherein the detection data includes: a normal gate voltage in a gate voltage drop phase of the shutdown process, an actual gate voltage, a first normal duration, a first actual duration, a second normal duration and a second actual duration in a Miller platform phase of the shutdown process; According to the total number of chips and the detection data of the target IGBT, the internal defect location of the target IGBT is completed; The method of completing the internal defect location of the target IGBT according to the total number of chips and the detection data of the target IGBT includes: Detecting whether the actual gate voltage is greater than the normal gate voltage, and if so, locating the internal defect of the target IGBT as a first gate-emitter loop defect; Detecting whether the first actual duration is less than the first normal duration, and if so, locating the internal defect of the target IGBT as a second gate-emitter loop defect; Detecting whether the second actual duration is less than the second normal duration, and if so, locating the internal defect of the target IGBT as a collector gate loop defect; The IGBT defect location method based on the gate voltage during the turn-off process further includes: If the internal defect includes a first gate-emitter loop defect, a second gate-emitter loop defect, and a collector-gate loop defect, then determining that the target IGBT is a gate defect; If the internal defect includes a first gate-emitter loop defect and a second gate-emitter loop defect, but does not include a collector-gate loop defect, then the target IGBT is determined to be an emitter defect; If the internal defect includes a collector-gate loop defect but does not include a first gate-emitter loop defect and a second gate-emitter loop defect, then the target IGBT is determined to be a collector defect; After locating the internal defect of the target IGBT as a first gate-emitter loop defect, the method further includes: Determine the number of chips of the target IGBT having a first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips, and the pre-acquired gate threshold voltage; After locating the internal defect of the target IGBT as a second gate-emitter loop defect, the method further includes: Determine the number of chips of the target IGBT having a second gate-emitter loop defect according to the first normal duration, the first actual duration and the total number of chips; After locating the internal defect of the target IGBT as a collector gate loop defect, the method further includes: Determine the number of chips of the target IGBT having collector-gate loop defects according to the second normal duration and the second actual duration and the total number of chips; The obtaining of the total number of target IGBT chips and detection data includes: Obtain the total number of target IGBT chips, actual gate voltage and collector-emitter voltage waveforms, and gate voltage and collector-emitter voltage waveforms in a normal state; If there is a stage in which the gate voltage changes and the collector-emitter voltage does not change in the actual gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the gate voltage falling stage, and the corresponding duration is the first actual duration of the gate voltage falling stage, and the corresponding gate voltage is the actual gate voltage in the gate voltage falling stage; if there is a stage in which the gate voltage does not change and the collector-emitter voltage changes in the actual gate voltage and collector-emitter voltage waveforms, then this stage is determined to be the Miller platform stage, and the corresponding duration is the second actual duration of the Miller platform stage; If, in the gate voltage and collector-emitter voltage waveforms in the normal state, there is a stage in which the gate voltage changes but the collector-emitter voltage does not change, then this stage is determined to be the gate voltage falling stage, the corresponding duration is the first normal duration of the gate voltage falling stage, and the corresponding gate voltage is the normal gate voltage in the gate voltage falling stage; if, in the gate voltage and collector-emitter voltage waveforms in the normal state, there is a stage in which the gate voltage does not change but the collector-emitter voltage changes, then this stage is determined to be the Miller platform stage, and the corresponding duration is the second normal duration of the Miller platform stage.

2. The IGBT defect location method based on the gate voltage during the turn-off process according to claim 1, characterized in that: The step of determining the number of chips of the target IGBT having the first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage comprises: The number of chips with the first gate-emitter loop defect is determined by the following formula: m 1: Where n represents the total number of chips. u miller represents the normal gate voltage, u miller，fault represents the actual gate voltage, U T Represents the gate threshold voltage.

3. The IGBT defect location method based on the gate voltage during the turn-off process according to claim 1, characterized in that: The determining, according to the first normal duration, the first actual duration and the total number of chips, the number of chips of the target IGBT having the second gate-emitter loop defect comprises: Determine the number of chips with the second gate-emitter loop defect in the target IGBT according to the following formula: m 2: Where n represents the total number of chips, Δt A = t A,fault - t A , t A,fault Indicates the first actual duration, t A Indicates the first normal duration.

4. The IGBT defect location method based on the gate voltage during the turn-off process according to claim 1, characterized in that: The step of determining the number of chips of the target IGBT having collector-gate loop defects according to the second normal duration, the second actual duration and the total number of chips includes: The number of chips with collector gate loop defects is determined according to the following formula: m 3: Where n represents the total number of chips. t B,faul Indicates the second actual duration, t B Indicates the second normal duration.

5. An IGBT defect location system based on gate voltage during turn-off, characterized in that: include: An acquisition device is used to acquire the total number of chips and detection data of the target IGBT, wherein the detection data includes: a normal gate voltage, an actual gate voltage, a first normal duration, a first actual duration, a second normal duration and a second actual duration in a Miller platform phase of the shutdown process during a gate voltage drop phase of the shutdown process; A detection device, used for completing the internal defect location of the target IGBT according to the total number of chips of the target IGBT and the detection data; The detection device comprises: A first detection module is used to detect whether the actual gate voltage is greater than the normal gate voltage, and if so, locate the internal defect of the target IGBT as a first gate-emitter loop defect; A second detection module is used to detect whether the first actual duration is less than a first normal duration, and if so, the internal defect of the target IGBT is located as a second gate-emitter loop defect; A third detection module is used to detect whether the second actual duration is less than the second normal duration, and if so, the internal defect of the target IGBT is located as a collector gate loop defect; The IGBT defect location system based on the gate voltage during the turn-off process further includes: A first positioning device, used for determining that the target IGBT is a gate defect if the internal defect includes a first gate-emitter loop defect, a second gate-emitter loop defect and a collector-gate loop defect; A second positioning device, for determining that the target IGBT is an emitter defect if the internal defect includes a first gate-emitter loop defect and a second gate-emitter loop defect, but does not include a collector-gate loop defect; A third positioning device, for determining that the target IGBT is a collector defect if the internal defect includes a collector gate loop defect but does not include a first gate emitter loop defect and a second gate emitter loop defect; The IGBT defect location system based on the gate voltage during the turn-off process further includes: A first quantity determining device, for determining the number of chips of the target IGBT having a first gate-emitter loop defect according to the normal gate voltage, the actual gate voltage, the total number of chips and the pre-acquired gate threshold voltage; The IGBT defect location system based on the gate voltage during the turn-off process further includes: A second quantity determining device, used for determining the number of chips of the target IGBT having a second gate-emitter loop defect according to the first normal duration, the first actual duration and the total number of chips; The IGBT defect location system based on the gate voltage during the turn-off process further includes: A third quantity determining device, used to determine the number of chips of the target IGBT having collector gate loop defects according to the second normal duration and the second actual duration and the total number of chips; The acquisition device comprises: An acquisition module is used to acquire the total number of target IGBT chips, actual gate voltage and collector-emitter voltage waveforms, and gate voltage and collector-emitter voltage waveforms in a normal state; The first determination module is used to determine that if there is a stage in which the gate voltage changes and the collector-emitter voltage does not change in the actual gate voltage and collector-emitter voltage waveforms, the stage is determined to be a gate voltage falling stage, and the corresponding duration is the first actual duration of the gate voltage falling stage, and the corresponding gate voltage is the actual gate voltage in the gate voltage falling stage; if there is a stage in which the gate voltage does not change and the collector-emitter voltage changes in the actual gate voltage and collector-emitter voltage waveforms, the stage is determined to be a Miller platform stage, and the corresponding duration is the second actual duration of the Miller platform stage; The second determination module is used to determine that if there is a stage in which the gate voltage changes and the collector-emitter voltage does not change in the gate voltage and collector-emitter voltage waveforms in the normal state, then the stage is determined to be the gate voltage falling stage, and the corresponding duration is the first normal duration of the gate voltage falling stage, and the corresponding gate voltage is the normal gate voltage in the gate voltage falling stage; if there is a stage in which the gate voltage does not change and the collector-emitter voltage changes in the gate voltage and collector-emitter voltage waveforms in the normal state, then the stage is determined to be the Miller platform stage, and the corresponding duration is the second normal duration of the Miller platform stage.

6. The IGBT defect location system based on the gate voltage during the turn-off process according to claim 5, characterized in that: The first quantity determining device is used for: The number of chips with the first gate-emitter loop defect is determined by the following formula: m 1: Where n represents the total number of chips. u miller represents the normal gate voltage, u miller，fault represents the actual gate voltage, U T Represents the gate threshold voltage.

7. The IGBT defect location system based on the gate voltage during the turn-off process according to claim 5, characterized in that: The second quantity determining device is used for: Determine the number of chips with the second gate-emitter loop defect in the target IGBT according to the following formula: m 2: Where n represents the total number of chips, Δt A = t A,fault - t A , t A,fault Indicates the first actual duration, t A Indicates the first normal duration.

8. The IGBT defect location system based on the gate voltage during the turn-off process according to claim 5, characterized in that: The third quantity determining device is used for: The number of chips with collector gate loop defects is determined according to the following formula: m 3: Where n represents the total number of chips. t B,faul Indicates the second actual duration, t B Indicates the second normal duration.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the IGBT defect location method based on the gate voltage during the turn-off process according to any one of claims 1 to 4 is implemented.

10. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the instructions are executed by the processor, the IGBT defect location method based on the gate voltage during the turn-off process described in any one of claims 1 to 4 is implemented.

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