Signal delay detection circuit and signal delay detection device
By designing a signal delay detection circuit, the logic processing unit and the delay indication unit automatically detect the delay of the excitation signal and the feedback signal, solving the problems of low efficiency and misjudgment in the prior art, and achieving efficient and accurate delays Judgment and cost savings.
Patent Information
- Application Number
- CN202310805292.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2024-12-31
AI Technical Summary
The existing signal delay detection method is inefficient, and it is impossible to automatically determine whether the delay between the excitation signal and the feedback signal is less than the delay threshold, and there are misjudgments and high labor costs.
A signal delay detection circuit is designed, including a logic processing unit and a delay indication unit. By receiving and comparing the excitation signal and feedback signal, an indication signal is output to determine whether the delay is less than a threshold, and an AND gate circuit and light emitting diode are used, etc. Automatic detection of components.
It realizes automatic and accurate judgment of whether the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold, saving labor costs and reducing misjudgment.
Smart Images
Figure CN119224549A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of signal detection, and in particular to a signal delay detection circuit and a signal delay detection device. Background Art
[0002] During the EMC (Electro Magnetic Compatibility) test, the indirect field of view device in the vehicle needs to ensure that the delay between the excitation signal and the feedback signal is less than a certain delay threshold. If the delay between the excitation signal and the feedback signal is too high, the field of view information obtained by the indirect field of view device will not be timely for the vehicle user. If the user drives based on the field of view information obtained by the indirect field of view device with too high delay, there will be a great safety hazard.
[0003] The existing test scheme generally collects the excitation signal and feedback signal through an oscilloscope, and determines whether the delay between the excitation signal and the feedback signal is less than the delay threshold based on manual comparison. However, this method is too inefficient and cannot automatically determine whether the delay between the excitation signal and the feedback signal is less than the delay threshold. In addition, there are certain errors in oscilloscope signal collection and manual comparison, which can easily lead to misjudgment. In addition, due to the large amount of tests, manual comparison also consumes a lot of manpower costs. Summary of the invention
[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present disclosure provides a signal delay detection circuit and a signal delay detection device.
[0005] In a first aspect, the present disclosure provides a signal delay detection circuit, comprising:
[0006] Logic processing unit and delay indication unit;
[0007] The input end of the delay indication unit is connected to the reference voltage output end of the logic processing unit; the first signal input end of the logic processing unit is connected to the output end of the excitation source, and the second signal input end of the logic processing unit is connected to the signal feedback end of the device under test; the output end of the excitation source is used to output an excitation signal, and the pulse width of the excitation signal is equal to the delay threshold, and the signal feedback end of the device under test is used to output a feedback signal for the excitation signal; wherein the delay threshold is used to measure whether the feedback delay of the feedback signal exceeds the standard;
[0008] When and only when the first signal input terminal receives the excitation signal and the second signal input terminal receives the feedback signal within the delay threshold, the logic processing unit triggers the delay indication unit to output the first indication signal through the first reference signal output by the reference voltage output terminal.
[0009] Optionally, after the first signal input terminal does not receive the excitation signal, the second signal input terminal does not receive the feedback signal within the delay threshold, and the logic processing unit outputs a second reference signal through the reference voltage output terminal; wherein the second reference signal is used to trigger the delay indication unit to output a second indication signal, and the second indication signal is different from the first indication signal.
[0010] Optionally, the excitation signal and the feedback signal are both high level, the logic processing unit includes an AND gate circuit, the first input end of the AND gate circuit is the first signal input end, the second input end of the AND gate circuit is the second signal input end, and the output end of the AND gate circuit is the reference voltage output end.
[0011] Optionally, the AND gate circuit includes a first diode, a second diode, a first resistor, a second resistor and a first power supply;
[0012] The cathode of the first diode is connected to the first input terminal of the AND gate circuit, the cathode of the second diode is connected to the second input terminal of the AND gate circuit, the first end of the first resistor is connected to the output terminal of the first power supply, and the first end of the second resistor is connected to the ground; the anode of the first diode, the anode of the second diode, the second end of the first resistor and the second end of the second resistor are all connected to the output terminal of the AND gate circuit;
[0013] When the first input terminal receives the excitation signal at a high level, the first diode is reverse cutoff; when the first input terminal does not receive the excitation signal, the first diode is turned on; when the second input terminal receives the feedback signal at a high level, the second diode is reverse cutoff; when the second input terminal does not receive the feedback signal, the second diode is turned on.
[0014] Optionally, the voltage value corresponding to the first power supply is the same as the voltage value corresponding to the high level of the excitation signal, and the voltage value corresponding to the first power supply is the same as the voltage value corresponding to the high level of the feedback signal.
[0015] Optionally, the delay indication unit includes a light emitting diode and a second power supply, the first electrode of the light emitting diode is connected to the reference voltage output end, and the second electrode of the light emitting diode is connected to the second power supply; the first reference signal is used to trigger the light emitting diode to emit light or turn off.
[0016] Optionally, the delay indication unit includes a light emitting diode, an anode of the light emitting diode is connected to the reference voltage output terminal, and a cathode of the light emitting diode is grounded; and the first reference signal is used to trigger the light emitting diode to emit light.
[0017] Optionally, the delay indication unit further includes a storage capacitor, and the storage capacitor is connected in parallel with the light emitting diode.
[0018] In a second aspect, the present disclosure further provides a signal delay detection device, comprising a signal delay detection circuit as described in any one of the first aspects.
[0019] Optionally, the signal delay detection device further includes a counting unit, and the counting unit is used to sense the first indication signal and count the first indication signal.
[0020] The present disclosure provides a signal delay detection circuit and a signal delay detection device; the signal delay detection circuit comprises a logic processing unit and a delay indication unit; the input end of the delay indication unit is connected to the reference voltage output end of the logic processing unit; the first signal input end of the logic processing unit is connected to the output end of an excitation source, and the second signal input end of the logic processing unit is connected to the signal feedback end of a device under test; the output end of the excitation source is used to output an excitation signal, and the pulse width of the excitation signal is equal to a delay threshold, and the signal feedback end of the device under test is used to output a feedback signal for the excitation signal; wherein the delay threshold is used to measure whether the feedback delay of the feedback signal exceeds the standard; when and only when the first signal input end receives the excitation signal, and the second signal input end receives the feedback signal within the delay threshold, the logic processing unit outputs a first reference signal through the reference voltage output end to trigger the delay indication unit to output a first indication signal. Based on the above scheme, the signal delay detection circuit provided by the present invention can receive an excitation signal and a feedback signal, and can output a first indication signal only when the excitation signal is received and the feedback signal is received within the delay threshold, and the pulse width of the excitation signal is equal to the duration threshold, which ensures that as long as the first indication signal can be output, the delay between the excitation signal and the feedback signal must be less than or equal to the delay threshold; wherein, the first indication signal can be an easily recognizable indication signal, and as long as the first indication signal is issued, it means that the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold, that is, the detection personnel do not need to pay additional costs to determine the delay duration between the excitation signal and the feedback signal, and can only determine whether the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold based on whether the first indication signal can be detected, which greatly saves labor costs and is not prone to misjudgment. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 A schematic diagram of a signal delay detection circuit structure provided by an embodiment of the present disclosure;
[0022] Figure 2 A schematic diagram of a signal pulse provided by an embodiment of the present disclosure;
[0023] Figure 3 A schematic diagram of another signal delay detection circuit structure provided in an embodiment of the present disclosure;
[0024] Figure 4 A schematic diagram of another delay detection circuit structure provided in an embodiment of the present disclosure;
[0025] Figure 5 A schematic diagram of another delay detection circuit structure provided in an embodiment of the present disclosure;
[0026] Figure 6 A schematic diagram of the structure of a signal delay detection device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0027] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0028] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0029] The signal delay detection circuit and the signal delay detection device provided in the embodiments of the present disclosure are exemplarily described below in conjunction with the accompanying drawings.
[0030] Figure 1 A schematic diagram of a signal delay detection circuit structure provided in an embodiment of the present disclosure, the circuit comprising:
[0031] A logic processing unit 11 and a delay indication unit 12; an input terminal 121 of the delay indication unit 12 is connected to a reference voltage output terminal 111 of the logic processing unit 11; a first signal input terminal 112 of the logic processing unit 11 is connected to an output terminal 131 of an excitation source 13, and a second signal input terminal 113 of the logic processing unit 11 is connected to a signal feedback terminal 141 of a device under test 14; the output terminal 131 of the excitation source 13 is used to output an excitation signal, and a pulse width of the excitation signal is equal to a delay threshold, and the signal feedback terminal 141 of the device under test 14 is used to output a feedback signal for the excitation signal; wherein the delay threshold is used to measure whether the feedback delay of the feedback signal exceeds the standard; when and only when the first signal input terminal 112 receives the excitation signal, and the second signal input terminal 113 receives the feedback signal within the delay threshold, the logic processing unit 11 outputs a first reference signal through the reference voltage output terminal 111 to trigger the delay indication unit 12 to output a first indication signal.
[0032] Reference Figure 1 , the excitation source 13 represents a functional device that can output an excitation signal; in some scenarios, the excitation signal can be an electromagnetic wave, that is, the excitation source 13 can be a functional device that can emit electromagnetic waves, and the pulse width of the excitation signal represents the duration of a certain level (i.e., a high level or a low level) maintained by the excitation source 13 when emitting an excitation signal. Figure 2 A schematic diagram of a signal pulse provided for an embodiment of the present disclosure, wherein the horizontal axis t represents time, the vertical axis v represents voltage, and Δt represents the delay between the excitation signal and the feedback signal. From one perspective, when there is an excitation signal, it may be a high level, otherwise it may be a low level. The excitation source 13 may emit multiple excitation signals. Each time an excitation signal is emitted, the signal level corresponding to the excitation signal becomes a high level, and the duration of a high level is the pulse width. The feedback signal represents the reflected signal generated by the excitation signal emitted by the excitation source 13 acting on the device under test 14. The device under test 14 represents a functional device for realizing the delay of the test signal, which may be some specific artificially manufactured devices or some naturally formed objects, and its core function is to be able to receive the excitation signal and generate a feedback signal.
[0033] Continue reading Figure 2, assuming that the delay threshold is 200ms (time unit: milliseconds), the pulse width t1 of the excitation signal can also be 200ms. Based on this setting, if the delay between the feedback signal and the excitation signal is greater than 200ms, then for a certain excitation signal and the corresponding feedback signal, the first signal input terminal 112 and the second signal input terminal 113 will inevitably not be able to receive the excitation signal and the feedback signal at the same time. It should be noted that the number of times the excitation signal is transmitted and the number of times the feedback signal is fed back in the embodiment of the present disclosure are not necessarily limited to only once, and multiple excitation signals may also be transmitted, and multiple feedback signals may be received accordingly, but the transmission interval between the two excitation signals is much greater than the pulse width of the excitation signal. In a specific scenario, for example, after the first excitation signal is transmitted, a second excitation signal is transmitted at a certain interval, and both excitation signals generate corresponding feedback signals and are received. Then the feedback signal corresponding to the excitation signal transmitted for the second time will not be kept at a high level at the same time as the excitation signal transmitted for the first time.
[0034] In some scenarios, the excitation source 13 can be controlled to transmit an excitation signal to the device under test 14, and simultaneously output the excitation signal to the first signal input terminal 112. After the excitation signal acts on the device under test 14, the signal feedback terminal 141 outputs a feedback signal to the second signal input terminal 113. If the delay between the excitation signal and the feedback signal is less than the delay threshold, the excitation signal received by the first signal input terminal 112 and the feedback signal received by the second signal input terminal 113 are both kept at a high level, and the logic processing unit 11 can output a first reference signal through the reference voltage output terminal 111 based on this; the first reference signal can trigger the delay indication unit 12 to output a first indication signal. The first reference signal can be a voltage signal, such as a signal of a specific voltage value, the delay indication unit 12 can be a functional device that can make some obvious prompts for the first reference signal, such as a light-emitting element, a sound-emitting element, etc., and the first indication signal can be a signal that is easily accessible to some people, such as light, sound, etc.
[0035] Based on the above scheme, the signal delay detection circuit provided by the embodiment of the present disclosure can receive an excitation signal and a feedback signal, and can output a first indication signal only when the excitation signal is received and the feedback signal is received within the delay threshold, and the pulse width of the excitation signal is equal to the duration threshold, which ensures that as long as the first reference signal can be output, the delay between the excitation signal and the feedback signal must be less than or equal to the delay threshold; wherein, the first indication signal can be an easily recognizable indication signal, and as long as the first indication signal is issued, it means that the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold, that is, the detection personnel do not need to pay additional costs to determine the delay duration between the excitation signal and the feedback signal, and can only determine whether the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold based on whether the first indication signal can be detected, which greatly saves labor costs and is not prone to misjudgment.
[0036] In some embodiments, when the first signal input terminal does not receive an excitation signal, and / or the second signal input terminal does not receive a feedback signal, the logic processing unit 11 outputs a second reference signal through the reference voltage output terminal; wherein the second reference signal is used to trigger the delay indication unit 12 to output a second indication signal, and the second indication signal is different from the first indication signal.
[0037] For example, continue to refer to the above Figure 1 In the embodiments, taking the delay indication unit 12 as a light-emitting element as an example, the first reference signal can be used to instruct the light-emitting element to output the first indication signal, and the first indication signal can be the light emitted by the light-emitting element, that is, the light-emitting element is in a non-luminous state when the first reference signal is not received. In some other possible scenarios, still taking the delay indication unit 12 as a light-emitting element as an example, the first reference signal can be used to instruct the light-emitting element to output the second indication signal, and the second indication signal can be that the light-emitting element no longer emits light, that is, the light-emitting element is in a luminous state when the first reference signal is not received, and the light-emitting element no longer emits light after receiving the first reference signal.
[0038] Through the above solution, it is also possible to accurately determine whether the first reference signal is received, and further accurately determine whether the delay between the excitation signal and the feedback signal is greater than the delay threshold.
[0039] In some embodiments, the excitation signal and the feedback signal are both high level, the logic processing unit 11 also includes an AND gate circuit, the first input terminal of the AND gate circuit is the first signal input terminal 112, the second input terminal of the AND gate circuit is the second signal input terminal 113, and the output terminal of the AND gate circuit is the reference voltage output terminal 111.
[0040] Continue reading Figure 1In the embodiment, the excitation signal and the feedback signal can both be high level, and the logic processing unit 11 can be an AND gate circuit, that is, when the first input end of the AND gate circuit receives the excitation signal, the input signal it receives is "1", otherwise it is "0", and when the second input end of the AND gate circuit receives the feedback signal, the input signal it receives is "1", otherwise it is "0", when the first input end and the second input end of the AND gate circuit simultaneously receive the signal "1", the output end of the AND gate circuit outputs the signal "1", that is, it can output a high level signal, otherwise it outputs the signal "0", that is, it can output a low level signal, the signal "1" output by the output end of the AND gate circuit can be the first reference signal, and when the output end of the AND gate circuit outputs the signal "1", it can trigger the delay indication unit 12 to output the first indication signal.
[0041] Through the above scheme, it is possible to accurately indicate whether the excitation signal and the feedback signal are simultaneously maintained at a high level by means of an AND gate circuit. In fact, it is possible to accurately indicate whether the delay between the excitation signal and the feedback signal is greater than the delay threshold. When the delay between the excitation signal and the feedback signal is greater than the delay threshold, the output end of the AND gate circuit outputs a signal "0", and the delay indication unit 12 cannot output the first indication signal. Based on this, the detection personnel can determine that the delay between the excitation signal and the feedback signal is greater than the delay threshold.
[0042] Figure 3 A schematic diagram of another signal delay detection circuit structure provided for an embodiment of the present disclosure; in some embodiments, the AND gate circuit includes a first diode 311, a second diode 312, a first resistor 313, a second resistor 314 and a first power supply 315; the cathode of the first diode 311 is connected to the first input terminal of the AND gate circuit, the cathode of the second diode 312 is connected to the second input terminal of the AND gate circuit, the first end of the first resistor 313 is connected to the output terminal of the first power supply 315, and the first end of the second resistor 314 is connected to the ground; the anode of the first diode 311, the anode of the second diode 312, the second end of the first resistor 313 and the second end of the second resistor 314 are all connected to the output terminal of the AND gate circuit;
[0043] When the first input terminal receives an excitation signal of a high level, the first diode 311 is reversely cut off; when the first input terminal does not receive an excitation signal, the first diode 311 is turned on; when the second input terminal receives a feedback signal of a high level, the second diode 312 is reversely cut off; when the second input terminal does not receive a feedback signal, the second diode 312 is turned on.
[0044] In some embodiments, the voltage value corresponding to the first power supply 315 is the same as the voltage value corresponding to the high level of the excitation signal, and the voltage value corresponding to the first power supply 315 is the same as the voltage value corresponding to the high level of the feedback signal.
[0045] Exemplarily, the excitation signal and the feedback signal are both at high level. For example, when both are maintained at high level, the corresponding voltage is 5V (voltage unit: volt), otherwise it is 0V. The first power supply 315 can output 5V voltage, the first resistor 313 can be 2Ω (resistance unit: ohm), the second resistor 314 can be 3Ω, the first diode 311 and the second diode 312 can be used for clamping, and the clamping voltage of both can be 0.7V. Figure 2 , when the first input terminal does not receive the excitation signal and the second input terminal does not receive the feedback signal, that is, the cathode of the first diode 311 remains at a low level and the cathode of the second diode 312 remains at a low level, the first diode 311 and the second diode 312 are both turned on. When the first diode 311 and the second diode 312 are turned on, the cathodes of the first diode 311 and the second diode 312 can be considered to be grounded, and the voltage of the output terminal 111 of the AND gate circuit is clamped to 0.7V by the first diode 311 and / or the second diode 312, that is, it can be considered that the output terminal 111 of the AND gate circuit outputs a low level, and the delay indication unit 12 cannot output the first indication signal; when the cathode of the first diode 311 remains When the cathode of the first diode 311 and the cathode of the second diode 312 are both high level, the first diode 311 and the second diode 312 are reversely cut off, the second diode 312 is turned on, and the voltage of the output terminal 111 of the AND gate circuit is clamped to 0.7V by the second diode 312, that is, it can be considered that the output terminal 111 of the AND gate circuit outputs a low level, and the delay indication unit 12 cannot output the first indication signal; when the cathode of the first diode 311 and the cathode of the second diode 312 are both high level, the first diode 311 and the second diode 312 are reversely cut off, and the voltage of the output terminal 111 of the AND gate circuit is 3V, that is, it can be considered that the output terminal 111 of the AND gate circuit outputs a high level, and the delay indication unit 12 outputs the first indication signal. By setting the voltage value of the first power supply 315 to be the same as the voltage value corresponding to the high level of the excitation signal, and the voltage value corresponding to the first power supply 315 to be the same as the voltage value corresponding to the high level of the feedback signal, it is also possible to avoid, for example, the first diode 311 and the second diode 312 being damaged due to the excessively high voltage.
[0046] That is, through the above solution, it is possible to accurately determine whether the delay between the excitation signal and the feedback signal is greater than the delay threshold by means of an AND gate circuit.
[0047] Figure 4Another schematic diagram of a delay detection circuit structure provided for an embodiment of the present disclosure; in some embodiments, the delay indication unit 12 includes a light-emitting diode 122 and a second power supply 123, the first electrode 1221 of the light-emitting diode 122 is connected to the reference voltage output terminal 111, and the second electrode 1222 of the light-emitting diode is connected to the second power supply 123; the first reference signal is used to trigger the light-emitting diode to emit light or turn off.
[0048] Exemplarily, the second power supply 123 may be a functional unit capable of providing voltage to the light-emitting diode 122. The voltage provided by the second power supply 123 may be a positive voltage or a zero voltage. When the second power supply 123 provides a zero voltage, from one perspective, the second power supply 123 may also be understood as a ground line, that is, the second electrode of the light-emitting diode 122 is grounded. When the second power supply 123 is a ground line, the embodiment of the present disclosure may be exemplified as the delay indication unit 12 only including the light-emitting diode 122, the anode of the light-emitting diode 122 is connected to the reference voltage output terminal 111, and the cathode of the light-emitting diode 122 is grounded. When a certain voltage difference is formed between the anode of the light-emitting diode 122 and the cathode of the light-emitting diode 122, the light-emitting diode 122 may be turned on and emit light.
[0049] In some embodiments, the logic processing unit 11 includes an AND gate circuit; the anode of the light-emitting diode 122 is connected to the reference voltage output terminal 111, and the cathode of the light-emitting diode 122 is connected to the second power supply 123; the voltage value of the first reference signal is greater than the voltage value of the second power supply 123, and the first reference signal is used to trigger the light-emitting diode 122 to emit light.
[0050] Continue reading Figure 4 In the corresponding embodiment, the anode of the light-emitting diode 122 can be the first electrode 1221, and the cathode of the light-emitting diode can be the second electrode 1222; when the excitation signal and the feedback signal are both at high level, the reference voltage output terminal 111 outputs a 3V high-level signal, and the voltage output by the second power supply 123 can be 0V, that is, the cathode of the light-emitting diode 122 is grounded. In this way, a 3V voltage difference can be formed between the anode and the cathode of the light-emitting diode 122, so that the light-emitting diode 122 emits light. Applied to the above embodiment, the detection personnel can determine whether the delay between the excitation signal and the feedback signal is greater than the delay threshold only based on whether the light-emitting diode 122 emits light. If the light-emitting diode 122 emits light, it means that the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold, otherwise, the delay between the excitation signal and the feedback signal is greater than the delay threshold.
[0051] As another possible implementation, the anode of the light-emitting diode 122 can be connected to the second power supply 123, the cathode of the light-emitting diode 122 can be connected to the reference voltage output terminal 111, and the second power supply 123 can output a voltage of 3.7 V. In this way, when at least one of the cathode of the first diode 311 and the cathode of the second diode 312 is at a low level, the clamping voltage of the reference voltage output terminal 111 is 0.7 V, and a voltage difference of 3 V can be formed between the anode and cathode of the light-emitting diode 122, thereby making the light-emitting diode 122 emit light, and when the excitation signal and the feedback signal are both at a high level, that is, the delay between the excitation signal and the feedback signal is less than the delay threshold, the voltage at the output terminal of the reference voltage is 3 V, and a voltage difference of 3 V cannot be formed between the anode and cathode of the light-emitting diode 122, that is, the light-emitting diode 122 is extinguished. In this way, the inspector can determine whether the delay between the excitation signal and the feedback signal is greater than the delay threshold only based on whether the light-emitting diode 122 is illuminated. If the light-emitting diode 122 is not illuminated, it means that the delay between the excitation signal and the feedback signal is less than or equal to the delay threshold. Otherwise, the delay between the excitation signal and the feedback signal is greater than the delay threshold.
[0052] Figure 5 A schematic diagram of another delay detection circuit structure provided for an embodiment of the present disclosure; in some embodiments, the delay indication unit 12 further includes a storage capacitor 124, and the storage capacitor 124 is connected in parallel with the light emitting diode 122.
[0053] Exemplarily, the storage capacitor 124 can store a small amount of charge, so that when the reference voltage output terminal 111 changes from a high level to a low level, the storage capacitor 124 can provide a high level for the light-emitting diode 122 for a period of time, thereby extending the light-emitting duration of the light-emitting diode 122. This avoids misjudgment caused by the light-emitting duration of the light-emitting diode 122 being too short.
[0054] In some possible scenarios, the specifications of the storage capacitor 124 may be subject to certain restrictions, that is, although the storage capacitor 124 can be used to extend the light-emitting duration of the light-emitting diode, it cannot affect the next test. For example, the interval between the first excitation signal and the second excitation signal is 2s (time unit: seconds). If the storage capacitor 124 extends the light-emitting duration of the light-emitting diode 122 when the first excitation signal and the feedback signal are both high levels until the second excitation signal is received, it is impossible to determine whether the delay between the second excitation signal and its corresponding feedback signal is less than or equal to the delay threshold. Therefore, the specifications of the storage capacitor 124 can be set to a time length that is less than the interval between the two excitation signals, or it can be ensured that the two excitation signals do not interfere with each other.
[0055] An embodiment of the present disclosure further provides a signal delay detection device, comprising a signal delay detection circuit as in any one of the above signal delay detection circuit embodiments.
[0056] The signal delay detection circuit provided by the embodiments of the present disclosure includes the signal delay detection circuit of any one of the above-mentioned signal delay detection circuit embodiments, and therefore can also solve the same technical problems as the above-mentioned signal delay detection circuit and achieve the same technical effects, which will not be repeated here.
[0057] Figure 6 A schematic diagram of the structure of a signal delay detection device provided in an embodiment of the present disclosure; in some embodiments, the signal delay detection device further includes a counting unit 61, which is used to sense the first indication signal and count the first indication signal.
[0058] For example, since the number of tests is large, that is, multiple excitation signals need to be emitted to determine whether the delay between the multiple excitation signals and the feedback signal is greater than the delay threshold, although the delay indication unit 12 can save labor costs, it is still troublesome due to the large number of times. In order to further save labor costs, the embodiment of the present disclosure can also be provided with a counting unit 61 to count the first indication signal, which is applied to the above embodiment, that is, the light emission of the light-emitting diode 122 can be sensed and counted. In some embodiments, the counting unit 61 can include a flicker counter or a high-frequency camera.
[0059] That is, through the above solution, each time the light emitting diode 122 emits light, it can be counted by a scintillation counter or a high-frequency camera, so that the detection personnel no longer need to monitor and observe each detection in real time, but only need to collect the final detection result of the scintillation counter or the high-frequency camera. This greatly facilitates the detection process and further saves labor costs.
[0060] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0061] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A signal delay detection circuit, characterized in that: include: Logic processing unit and delay indication unit; The input end of the delay indication unit is connected to the reference voltage output end of the logic processing unit; the first signal input end of the logic processing unit is connected to the output end of the excitation source, and the second signal input end of the logic processing unit is connected to the signal feedback end of the device under test; the output end of the excitation source is used to output an excitation signal, and the pulse width of the excitation signal is equal to the delay threshold, and the signal feedback end of the device under test is used to output a feedback signal for the excitation signal; wherein the delay threshold is used to measure whether the feedback delay of the feedback signal exceeds the standard; When and only when the first signal input terminal receives the excitation signal and the second signal input terminal receives the feedback signal within the delay threshold, the logic processing unit triggers the delay indication unit to output the first indication signal through the first reference signal output by the reference voltage output terminal.
2. The signal delay detection circuit according to claim 1, characterized in that: After the first signal input terminal receives the excitation signal, the second signal input terminal does not receive the feedback signal within the delay threshold, and the logic processing unit outputs a second reference signal through the reference voltage output terminal; wherein the second reference signal is used to trigger the delay indication unit to output a second indication signal, and the second indication signal is different from the first indication signal.
3. The signal delay detection circuit according to claim 1, characterized in that: The excitation signal and the feedback signal are both at high levels, the logic processing unit includes an AND gate circuit, the first input end of the AND gate circuit is the first signal input end, the second input end of the AND gate circuit is the second signal input end, and the output end of the AND gate circuit is the reference voltage output end.
4. The signal delay detection circuit according to claim 3, characterized in that: The AND gate circuit includes a first diode, a second diode, a first resistor, a second resistor and a first power supply; The cathode of the first diode is connected to the first input terminal of the AND gate circuit, the cathode of the second diode is connected to the second input terminal of the AND gate circuit, the first end of the first resistor is connected to the output terminal of the first power supply, and the first end of the second resistor is connected to the ground; the anode of the first diode, the anode of the second diode, the second end of the first resistor and the second end of the second resistor are all connected to the output terminal of the AND gate circuit; When the first input terminal receives the excitation signal at a high level, the first diode is reverse cutoff; when the first input terminal does not receive the excitation signal, the first diode is turned on; when the second input terminal receives the feedback signal at a high level, the second diode is reverse cutoff; when the second input terminal does not receive the feedback signal, the second diode is turned on.
5. The signal delay detection circuit according to claim 4, characterized in that: The voltage value corresponding to the first power supply is the same as the voltage value corresponding to when the excitation signal is at a high level, and the voltage value corresponding to the first power supply is the same as the voltage value corresponding to when the feedback signal is at a high level.
6. The signal delay detection circuit according to claim 1, characterized in that: The delay indication unit includes a light emitting diode and a second power supply, wherein the first electrode of the light emitting diode is connected to the reference voltage output terminal, and the second electrode of the light emitting diode is connected to the second power supply; and the first reference signal is used to trigger the light emitting diode to emit light or turn off light.
7. The signal delay detection circuit according to claim 1, characterized in that: The delay indicating unit comprises a light emitting diode, an anode of the light emitting diode is connected to the reference voltage output terminal, and a cathode of the light emitting diode is grounded; the first reference signal is used to trigger the light emitting diode to emit light.
8. The signal delay detection circuit according to claim 6 or 7, characterized in that: The delay indication unit further includes a storage capacitor, and the storage capacitor is connected in parallel with the light emitting diode.
9. A signal delay detection device, characterized in that: The invention comprises the signal delay detection circuit as claimed in any one of claims 1 to 8.
10. The signal delay detection device according to claim 9, characterized in that: The signal delay detection device further includes a counting unit, and the counting unit is used to sense the first indication signal and count the first indication signal.