Photoelectric chip packaging structure

Abstract

The invention relates to the technical field of semiconductors, in particular to a photoelectric chip packaging structure which comprises a substrate, a signal transmission layer is arranged on the upper surface of the substrate, and a signal processing layer is arranged on the signal transmission layer; the signal transmission layer comprises a first electric chip which is provided with a first surface and a second surface, the first surface faces the substrate, and the second surface faces the signal processing layer; the signal processing layer comprises a signal conversion area and a data storage area; the signal conversion area is correspondingly provided with an optical chip, the optical chip comprises N * M photon calculation units, each photon calculation unit comprises an optical waveguide layer and a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or comprises a phase change material layer; the data storage area is correspondingly provided with a second electric chip which is used for receiving and storing calculation data. The problems that an existing packaging structure is high in preparation difficulty, poor in heat dissipation performance and the like are solved.

Description

[0001] Divisional application This application is a divisional application based on the Chinese invention patent application with application number CN2024109616281, application date July 18, 2024, and invention name “A photoelectric chip packaging structure”. Technical Field

[0002] The present invention relates to the technical field of chip packaging, and in particular to a photoelectric chip packaging structure. Background Art

[0003] Currently, there are usually two solutions for integrated circuit packaging: 1. Photonic chips (also known as optical chips) are placed above electronic chips (also known as electrical chips) For example, patent application CN115706058A discloses a semiconductor packaging device and a manufacturing method thereof, wherein a photonic chip in the semiconductor packaging device is arranged on the upper surface of an electronic chip through a first interconnection structure, an optical device, a rewiring structure and other structures, so that the photonic chip and the electronic chip achieve a better alignment and optical coupling effect.

[0004] For another example, patent application CN115706108A discloses a semiconductor packaging structure and a manufacturing method thereof, in which two electronic chips are arranged in parallel to jointly carry a photonic chip on their upper surfaces.

[0005] 2. The electronic chip is placed above the photonic chip For example, patent application CN114063229A discloses a semiconductor device. The semiconductor device includes: a PIC chip (also known as an optical chip), which includes a conductive structure in a hole; a first electronic integrated circuit chip, namely a first EIC chip (also known as an electrical chip), the first EIC chip is arranged on the first surface of the PIC chip; a second electronic integrated circuit chip, namely a second EIC chip, the second EIC chip is arranged on the second surface of the PIC chip. However, this solution of placing the optical chip under the electrical chip requires the provision of a through silicon via (TSV) on the optical chip. The processing technology of opening a through silicon via on an optical chip is very difficult and the cost is also very high.

[0006] However, with the continuous development of big data, artificial intelligence, telemedicine, the Internet of Things, e-commerce, and 5G communications, global data traffic has exploded, and lower-cost, more reliable, faster, and higher-density circuits are the goals pursued by integrated circuit packaging. However, the above traditional packaging solutions have certain defects in processing difficulty and working stability when dealing with high-density circuit integration. Summary of the invention

[0007] The purpose of the present invention is to provide an optoelectronic chip packaging structure (or, a 3D packaging structure of an optoelectronic chip) to partially solve or alleviate the above-mentioned deficiencies in the prior art, simplify the packaging structure of the optoelectronic chip (and thus simplify the processing technology), and improve the working stability of the optoelectronic chip.

[0008] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions: A first aspect of the present invention is to provide an optoelectronic chip packaging structure, comprising: A substrate, wherein a signal transmission layer is disposed on the upper surface of the substrate, and a signal processing layer is disposed on the signal transmission layer; The signal transmission layer comprises: at least one first electrical chip, the first electrical chip having a first surface and a second surface, wherein the first surface is arranged facing the substrate, and the second surface is arranged toward the signal processing layer; The signal processing layer includes: a signal conversion area, and a data storage area; At least one optical chip is correspondingly arranged in the signal conversion area, and the optical chip includes: N*M photon computing units, and the photon computing unit includes: an optical waveguide layer, and a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer; The optical chip is used to receive the modulation signal input by the first electrical chip, and at least one group of the photon computing units modulates the corresponding phase change material layer to a specific state in response to the modulation signal, and the photon computing unit completes the corresponding computing task in the specific state and outputs the corresponding computing data; At least one second electrical chip is correspondingly arranged in the data storage area, and the second electrical chip is used to receive and store the calculation data; wherein, the electrical connection path from the signal processing layer to the signal transmission layer includes a first bonding structure, a first redistribution layer, a through silicon via, and a second redistribution layer that are passed through in sequence.

[0009] In some embodiments, a size of at least one of the second electrical chips is smaller than a size of the signal transmission layer, and a size of the signal transmission layer is a total size of the at least one first electrical chip.

[0010] In some embodiments, at least two high-bandwidth memory chips are disposed on the second surface of the first electrical chip, and the at least two high-bandwidth memory chips are disposed on both sides of the optical chip respectively; The first electrical chip includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit, and a communication control circuit for communicating with the high-bandwidth memory chip; wherein, The XDAC control circuit is used to provide the corresponding modulation signal to the modulation layer, the XADC control circuit is used to receive the output signal of the photodetector in the photon computing unit, and the WDAC control signal is used to provide a calculation input signal to the photon computing unit after modulation, and the photon computing unit completes the calculation in response to the calculation input signal and outputs the calculation data.

[0011] In some embodiments, the signal processing layer also includes: a data conversion area communicatively connected to the data storage area, and the data conversion area is correspondingly provided with at least one second electrical chip, and the corresponding second electrical chip receives the corresponding calculation data through the first electrical chip, so as to convert the calculation data into a specific format according to the set data conversion rules, and input the calculation data converted into the specific format into the second electrical chip located in the data storage area.

[0012] In some embodiments, the system further comprises: at least one task allocation unit, and at least one of the task allocation units is connected to a corresponding functional partition, wherein a plurality of the second electrical chips are arranged in the functional partition; the functional partition comprises: a data storage area and / or a data conversion area; correspondingly, the task allocation unit is configured to perform the following steps: When at least one of the second electrical chips receives the corresponding calculation data, monitoring the power consumption data of the second electrical chip in the first time period; When the power consumption data is greater than a first set threshold value and less than or equal to a second set threshold value, the first allocation rule is used to allocate and process the current calculation data; wherein the first allocation rule requires suspending the transmission of new calculation data to the current second electrical chip within a second period of time, and selecting the second electrical chip whose spacing with the current second electrical chip is greater than the first spacing to receive the new calculation data to be processed subsequently; When the power consumption data is greater than the second set threshold value and less than or equal to the third set threshold value, the second allocation rule is used to allocate the calculation data; wherein the second allocation rule requires suspending the transmission of the new calculation data to the current second electrical chip during the second time period, and selecting the second electrical chip whose spacing with the current second electrical chip is greater than the second spacing to receive the new calculation data to be processed subsequently, and the second spacing is greater than the first spacing; When the power consumption data is greater than the third set threshold, the calculation data is allocated using a third allocation rule; wherein the third allocation rule requires pausing the processing of the current calculation data by the second electrical chip and reallocating the current calculation data to at least one of the second electrical chips whose spacing from the current second electrical chip is greater than the second spacing.

[0013] In some embodiments, at least one of the second electrical chips is a field programmable gate array chip.

[0014] In some embodiments, the first electronic chip is an application specific integrated circuit chip.

[0015] In some embodiments, a heat sink is disposed on the signal processing layer, and a lower surface of the heat sink at least covers at least the at least one optical chip and the at least one second electrical chip.

[0016] In some embodiments, a system integration board is further disposed on the lower surface of the substrate via a second bonding structure.

[0017] In some embodiments, the lower surface of the heat sink, the upper surface of the system integrated board, and the optical chip, the first electrical chip, and the same side end surface of the substrate sequentially arranged between the heat sink and the system integrated board together enclose a receiving space for arranging the optical fiber array, and a groove is arranged on the lower surface of the heat sink corresponding to the receiving space; wherein the optical fiber array includes: a first substrate and a second substrate connected to each other; Among them, the first substrate is arranged at the groove by a first glue, and the second substrate is connected to the side of the optical chip by a second glue with matching refractive index; a V-shaped groove is arranged on the second substrate to accommodate the optical fiber and enable the optical fiber to be optically coupled with the photosensitive area at the side.

[0018] Beneficial technical effects: In order to simplify the packaging structure (simplify the process and reduce the cost) and improve the working stability of the packaging structure during actual application, the present invention proposes a multi-chip combination packaging solution.

[0019] First of all, structurally speaking, the present invention adopts a structure in which a large-sized chip carries multiple small-sized chips (such as a "one-carry-many" packaging solution). This design scheme of small top and large bottom is relatively simple in packaging structure and easy to process. In addition, in order to reasonably allocate the overall computing power consumption, the present invention sets the large chip below as an optical chip for completing signal input and transmission, and sets at least one chip above as an optical chip made of phase change material, and the optical chip is used to complete the main computing tasks. Furthermore, the remaining chips are also set as electrical chips for converting and storing the calculation results output by the optical chip.

[0020] From another perspective, the present invention optimizes the distribution of functions between layers and within layers of the packaging structure, sets the inner layer as a signal transmission layer, and the outer layer as a signal processing layer, and divides different functional areas in the signal processing layer in turn, such as signal conversion, data conversion, and data storage areas.

[0021] In summary, this coordinated allocation of position and function can simplify the packaging structure on the one hand, and ensure that the overall power consumption of the packaging structure is reasonably distributed when it is working, thereby reducing its computing pressure when running big data calculations such as artificial intelligence, and improving its working stability and the reliability of calculation results.

[0022] Furthermore, for this packaging structure with optimized position and function (or distributed chip setting structure), the present invention also provides a multi-level task allocation rule to coordinate and maintain the power consumption and working stability of this distributed chip setting structure, which can reduce the power consumption generated by the distributed computing form to a certain extent (such as reasonably calling local chips to complete the current calculation), and at the same time quickly and reasonably allocate tasks based on different power consumption conditions, while maintaining the effective advancement of computing tasks and ensuring that the heat dissipation problem of the overall structure is reasonably optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0024] Figure 1 is a schematic diagram of the overall structure of an exemplary optoelectronic chip packaging structure in the present invention; Figure 2a It is a structural schematic diagram of an optoelectronic chip packaging structure in a specific embodiment; Figure 2b It is a structural schematic diagram of an optoelectronic chip packaging structure in another specific embodiment; Figure 2c It is a structural schematic diagram of an optoelectronic chip packaging structure in another specific embodiment; Figure 3 It is a schematic diagram of the structure of an optical chip in an exemplary embodiment of the present invention.

[0025] Summary of reference numerals: 1 is a substrate, 2 is a first electrical chip (also known as: a first electronic chip), 21 is a first surface, 22 is a second surface, 201 is a WDAC control circuit, 202 is an XDAC control circuit, 203 is an XADC control circuit, and 13 is an HBM chip; 3 is an optical chip (also known as: a photonic chip), 301 is an optical waveguide layer, 302 is a modulation layer (also known as: a phase change material layer), 303 is a first stop layer, 304 is a first oxide layer, 305 is a second stop layer, and 306 is a second oxide layer; 4 is a second electrical chip (also known as: a second electronic chip), 5 is a first bonding structure, 6 is a first redistribution layer, 7 is a through silicon via, 8 is a second redistribution layer, 9 is a second bonding structure, 10 is a system integrated board, 11 is an optical fiber array, 111 is a first substrate, 112 is a second substrate, 113 is an optical fiber, 114 is a first glue, 115 is a second glue, and 12 is a heat dissipation layer. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0027] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0028] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0029] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0030] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0032] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0033] As used in this specification, the term "about" typically means + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0034] In this specification, some embodiments may be disclosed in a format of being in a range. It should be understood that this description of "being in a range" is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent numerical values ​​within this range. For example, the description of the range 1-6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within this range, such as 1, 2, 3, 4, 5 and 6. Regardless of the breadth of the range, the above rules apply.

[0035] In this article, "Through Silicon Via" (English: Through Silicon Via, often abbreviated as TSV, also known as silicon through-hole) is a vertical interconnection that penetrates a silicon wafer or chip. TSV is an interconnection technology that allows 3D IC packaging to follow Moore's Law. TSV can stack multiple chips. Its design concept comes from the printed circuit board (PCB), drilling a small hole in the chip (the process can be divided into two types: drilling first and drilling later, Via First, Via Last), filling it with metal from the bottom, drilling holes (via) on the silicon wafer by etching or laser, and then filling it with conductive materials such as copper, polysilicon, tungsten and other substances.

[0036] In this article, "RDL (ReDistribution Layer)" is also called redistribution layer or rewiring layer. RDL refers to an additional metal layer on the chip that can rearrange the chip's electrodes or input / output pads (I / O pads) to other locations on the chip to facilitate connection with other integrated circuits or chips, or to connect electrodes or I / O pads of different chips together.

[0037] In this article, HBM refers to high-bandwidth memory chip, and FPGA (Field Programmable Gate Array) refers to field programmable gate array.

[0038] Herein, the modulation layer refers to any entity that affects the properties of light, including transmission, refraction, absorption, etc.

[0039] See also Figure 1 As shown, the present invention provides a novel optoelectronic chip packaging structure, the packaging structure comprising: A first electrical chip 2, wherein the first electrical chip 2 has a first surface 21 and a second surface 22; a second redistribution layer 8 is disposed on the first surface 21, and a second bonding structure 9 is disposed on the second redistribution layer 8, so that the first surface is connected to the substrate 1; a first redistribution layer 6 is disposed on the second surface 22, and a first bonding structure 5 is disposed on the first redistribution layer 6; At least one optical chip 3 and at least one second electrical chip 4, the lower surfaces of the optical chip 3 and the second electrical chip 4 are arranged on the second surface 22 through the first bonding structure 5; the upper surfaces of the optical chip 3 and the second electrical chip 4 are provided with a heat dissipation layer 12; wherein a plurality of through silicon vias 7 are provided in the first electrical chip 2 for connecting the circuits between the first electrical chip 2 and the optical chip 3 and the second electrical chip 4; At least two high-bandwidth memory chips are arranged on the second surface 22 of the first electrical chip 2, and at least two of the high-bandwidth memory chips are respectively arranged on both sides of the optical chip 3; the first electrical chip 2 includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit, and a communication control circuit that communicates with the high-bandwidth memory chip.

[0040] In order to further illustrate the technical effects of the above packaging structure, the following will exemplarily illustrate the working mode of the packaging structure in combination with the functional partitioning setting that can be achieved by the packaging structure. Figure 1 As shown, an optoelectronic chip packaging structure (i.e., a semiconductor device) includes: A substrate 1, wherein a signal transmission layer is disposed on the upper surface of the substrate, and a signal processing layer is disposed on the signal transmission layer; For example, in some embodiments, the signal transmission layer can be used to receive external signals (e.g., receive computing tasks input into the semiconductor device) and transmit the external signals to the signal processing layer. Preferably, the signal transmission layer can also be used to assist in data transmission and communication between different regions (or chips) in the signal processing layer.

[0041] The signal transmission layer includes: at least one first electrical chip 2, the first electrical chip 2 having a first surface and a second surface, wherein the first surface is arranged facing the substrate 1, and the second surface is arranged toward the signal processing layer; The signal processing layer includes: a signal conversion area and a data storage area; wherein the signal conversion area is used to process the calculation task and provide the corresponding calculation result; the data storage area is used to store the calculation result; At least one optical chip 3 is correspondingly arranged in the signal conversion area, and the optical chip 3 includes: N*M photon computing units, and the photon computing unit includes: an optical waveguide layer, a modulation layer located on the optical waveguide layer, and the modulation layer is a phase change material layer or the modulation layer includes a phase change material layer; The optical chip 3 is used to receive the modulation signal input by the first electrical chip 2, and at least one group of the photon computing units modulates the corresponding phase change material layer to a specific state in response to the modulation signal, and the photon computing unit completes the corresponding computing task in the specific state and outputs the corresponding computing data; At least one second electrical chip 4 is correspondingly arranged in the data storage area, and the second electrical chip 4 is used to receive and store the calculation data; wherein, the electrical connection path from the signal processing layer to the signal transmission layer includes successively passing through the first bonding structure 5, the first redistribution layer 6, the through silicon via 7, and the second redistribution layer 8.

[0042] It is worth noting that in order to simplify the packaging structure (simplify the process and reduce the cost) and improve the working stability of the packaging structure during actual application, the present invention proposes a multi-chip combination packaging solution.

[0043] First, structurally, the present invention adopts a structure in which a large chip carries multiple small chips. This design of a small top and a large bottom is relatively simple in packaging structure and is easy to process. In addition, in order to reasonably allocate the overall computing power consumption, the present invention sets the large chip below as an optical chip for completing signal input and transmission, and sets at least one chip above as an optical chip made of phase change material, and sets the remaining chips as electrical chips for converting and storing the calculation results output by the optical chip.

[0044] In summary, this coordinated allocation of position and function can simplify the packaging structure on the one hand, and ensure that the overall power consumption of the packaging structure is reasonably distributed when it is working, thereby reducing its computing pressure when running big data calculations such as artificial intelligence and improving its working stability.

[0045] In some embodiments, a size of at least one of the second electrical chips 4 is smaller than a size of the signal transmission layer, and a size of the signal transmission layer is a total size of the at least one first electrical chip 2 .

[0046] For example, in some embodiments, a first electrical chip 2 is provided in the signal transmission layer, an optical chip 3 is provided on the first electrical chip 2, and a plurality of second electrical chips 4 are provided adjacent to the optical chip 3. The first electrical chip 2 is larger than the size of the optical chip and the second electrical chip. In this embodiment, it is preferred to complete the installation of the optoelectronic chips by distributing a plurality of small-sized optical chips and electrical chips on a large-sized electrical chip (or a one-carry-multiple design).

[0047] In some embodiments, at least two high-bandwidth memory chips are disposed on the second surface of the first electrical chip 2, and the at least two high-bandwidth memory chips are disposed on both sides of the optical chip respectively; The first electrical chip includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit 201, and a communication control circuit for communicating with the high-bandwidth memory chip; wherein, The XDAC control circuit is used to provide the corresponding modulation signal to the modulation layer, the XADC control circuit is used to receive the output signal of the photodetector in the photon computing unit, and the WDAC control signal is used to provide a calculation input signal to the photon computing unit after modulation, and the photon computing unit completes the calculation in response to the calculation input signal and outputs the calculation data.

[0048] In some embodiments, the signal processing layer in the semiconductor device also includes: a data conversion area communicatively connected to the data storage area, and the data conversion area is correspondingly provided with at least one second electrical chip, and the corresponding second electrical chip receives the corresponding calculation data through the first electrical chip, so as to convert the calculation data into a specific format according to the set data conversion rules, and input the calculation data converted into the specific format into the second electrical chip located in the data storage area.

[0049] For example, in some embodiments, according to the different signal interfaces connected to the semiconductor device, the format of the calculation data needs to be converted into a format type that matches the signal interface, so different types of electrical chips can be adaptively selected to complete the conversion of the signal (i.e., calculation data) format. In other words, the conversion rule is determined by the type of signal interface in the actual application process.

[0050] For example, in some embodiments, the signal transmission layer (ie, the first electrical chip 2 ) is also used to complete signal transmission between the data conversion area and the data storage area.

[0051] It is worth mentioning that in the existing packaging structure design, in order to simplify the structure and processing technology, usually only a limited number of electrical chips and optical chips are stacked, and computing tasks are completed centrally on a single chip.

[0052] On the contrary, the present invention proposes a package in which multiple electrical chips are packaged with at least one optical chip, and for this new packaging structure, the present invention also proposes a distributed functional partitioning design to split the centralized computing tasks and distribute them to different functional intervals of the packaging structure to complete them, so as to ensure the reliability and accuracy of the computing results while efficiently completing the computing tasks. Furthermore, for this distributed functional design, the present invention also provides a task allocation scheme. For example, in some embodiments, the packaging structure also includes: At least one task allocation unit; and the task allocation unit is connected to at least one functional partition; the functional partition refers to one or more of a signal transmission layer, a signal conversion area, a data storage area, and a data conversion area; The following takes the second electrical chip as an example to illustrate the workflow of the task allocation unit: A plurality of second electrical chips 4 are arranged in the corresponding functional partitions; the second electrical chips are used to receive data transmitted by the previous chip and process it accordingly (for example, for the second electrical chip 4 located in the data conversion area, the previous chip refers to the first electrical chip 2 connected thereto); Monitor the power consumption data of at least one of the second electrical chips in a first time period (which can be set by the user); wherein the power consumption data may be the amount of data transmitted by the current second electrical chip (referred to as the current second electrical chip / current chip in this embodiment) in the first time period; or the power consumption data may be the strength value of the signal transmitted by the current chip in the first time period; When the power consumption data is greater than a first set threshold value and less than or equal to a second set threshold value, the first allocation rule is used for processing; wherein the first allocation rule requires suspending the transmission of new calculation data to the current second electrical chip within a second period of time, and selecting a second electrical chip whose distance from the current second electrical chip is greater than the first distance to receive new calculation data to be processed later; When the power consumption data is greater than the second set threshold value and less than or equal to the third set threshold value, the second allocation rule is used for processing; wherein the second allocation rule requires suspending the transmission of new data to the second electrical chip within the second time period, and selecting a second electrical chip whose distance from the current second electrical chip is greater than the second distance to receive the new data to be processed later; When the power consumption data is greater than a third set threshold, a third allocation rule is used for processing; wherein the third allocation rule requires suspending the computing task of the second electrical chip, and reallocating the current computing task to at least one second electrical chip whose spacing with the second electrical chip is greater than a second spacing; at the same time, a second electrical chip whose spacing with the current second electrical chip is greater than the second spacing is selected to receive new data to be processed later; For example, in some embodiments, a first electrical chip 2 is disposed on the signal processing layer. A data conversion area is arranged above the first electrical chip 2, and a plurality of second electrical chips (i.e., electrical chip I) are arranged in the data conversion area, which is used to convert the data format of the calculation result to meet the output conditions of the corresponding interface. The data conversion area is also connected to a data storage area, and a plurality of second electrical chips (i.e., electrical chip II) are arranged in the data storage area.

[0053] Among them, when the optoelectronic chip is working, the calculation results output by the optical chip will be transmitted to the electrical chip I via the first electrical chip 2. The electrical chip I will convert the format and then transmit the converted data to the electrical chip II for storage.

[0054] Among them, when the amount of calculated data is relatively limited, only one (or several) of the electric chips 1 can be preferentially enabled to perform data format conversion. As the calculation process advances, the electric chip 1 may cause abnormal power consumption due to reasons such as excessive calculation tasks (or accidental failures). At this time, in this embodiment, it is preferred to select different task allocation schemes according to abnormal power consumption conditions (such as the size of power consumption data) to maintain the effective advancement of the calculation tasks.

[0055] In other words, the multi-level task allocation rules adopted by the present invention can coordinate and maintain the power consumption and working stability of this distributed chip setting structure, which can reduce the power consumption generated by the distributed computing form to a certain extent (such as reasonably calling local chips to complete the current calculation), and at the same time, quickly and reasonably allocate tasks based on different power consumption conditions, while maintaining the effective advancement of computing tasks, ensuring that the heat dissipation problem of the overall structure is reasonably optimized.

[0056] It can be understood that the specific type of the electric chip in this embodiment can be adaptively selected according to the functional design, and the present invention does not limit this.

[0057] In some embodiments, the task allocation unit may be implemented by an electrical chip or other chips.

[0058] In some embodiments, at least one of the second electrical chips 4 is a field programmable gate array chip.

[0059] In some embodiments, the second electrical chip may include a chip that generates high-speed signals such as Serdes, a data storage chip for external data and calculation results such as HBM, a signal conversion processing chip, other customized ASIC chips, or one or more other chips.

[0060] In some embodiments, the first electrical chip 2 is a dedicated integrated circuit chip.

[0061] Figure 2a , Figure 2b Schematic diagrams of an exemplary packaging structure of an optoelectronic chip are shown respectively.

[0062] See also Figure 2a As shown, the optoelectronic chip packaging structure may include: a first electrical chip 2, an optical chip 3 and a second electrical chip 4 are respectively arranged on the second surface of the first electrical chip 2; and a plurality of HBM chips 13 are respectively arranged on both sides of the optical chip 3 and the second electrical chip 4.

[0063] See also Figure 2b As shown, the optoelectronic chip packaging structure may also include: a first electrical chip, an optical chip 3 and a second electrical chip 4 are respectively arranged on the second surface of the first electrical chip; and an XDAC control circuit 202 and an XADC control circuit 203 are respectively arranged on the first electrical chip, and one or more HBM chips 13 are respectively arranged on both sides of the second electrical chip 4.

[0064] In some embodiments, a heat sink 12 is disposed on the signal processing layer, and the lower surface of the heat sink 12 at least covers at least the at least one optical chip 3 and the at least one second electrical chip 4 .

[0065] In some embodiments, a system integration board 10 is further disposed on the lower surface of the substrate via a second bonding structure 9 .

[0066] For example, in some embodiments, the first and second bonding structures may be conductive bumps.

[0067] For example, in some embodiments, the first and second redistribution layers are wiring layers (RDL).

[0068] In some embodiments, the lower surface of the heat sink 12, the upper surface of the system integrated board 10, and the optical chip 3, the first electrical chip 2, and the same side end surface of the substrate 1 sequentially arranged between the heat sink 12 and the system integrated board 10 together enclose a receiving space for arranging the optical fiber array, and a groove is arranged on the lower surface of the heat sink corresponding to the receiving space; wherein the optical fiber array 11 includes: a first substrate 111 and a second substrate 112 connected to each other; Among them, the first substrate 111 is arranged at the groove through the first glue 114, and the second substrate 112 is connected to the side of the optical chip 3 through the second glue 115 with matching refractive index; a V-shaped groove is arranged on the second substrate 112 to accommodate the optical fiber 113 and enable the optical fiber 113 to be optically coupled with the photosensitive area at the side.

[0069] The optical output interface in the optical fiber array corresponds to the optical port in the photosensitive end face, so as to realize the end face optical coupling between the optical fiber array and the optical chip.

[0070] In some embodiments, the second bonding structure is a solder ball.

[0071] In some embodiments, the light modulation layer includes a phase change material layer made of a phase change material, or may be made of a phase change material.

[0072] Preferably, in some embodiments, the optical waveguide structure includes: a silicon oxide substrate, an optical waveguide layer 301, and a phase change material layer 302 located on the optical waveguide layer 301, a first stop layer 303 (i.e., a first isolation layer) is arranged between the optical waveguide layer 301 and the phase change material layer 302 (i.e., a modulation layer), and the phase change material layer 302 is covered with a first oxide layer 304 (i.e., a first protective layer).

[0073] See also Figure 3, on the substrate, a second stop layer 305 is arranged around the first stop layer 303 and the first region of the phase change material layer 302 close to the first stop layer 303 (i.e., a portion of the sidewall region around the bottom where the phase change material layer 302 contacts the first stop layer 303), and the first thickness of the second stop layer 305 is greater than the fourth thickness of the first stop layer 303, but less than the sum of the thicknesses of the phase change material layer 302 and the first isolation layer, so that the first stop layer and the second stop layer enclose a first region of the phase change material layer close to the optical waveguide layer on one side, which is upwardly encapsulated (i.e., the peripheral edge of the encapsulating component extends upward from the bottom of the encapsulated component along the peripheral sidewall height direction to form an enclosing sidewall); and on the first oxide layer, The second oxide layer 304, the second region of the phase-change material layer 302 close to the first oxide layer 304 (i.e., a portion of the sidewall region around the top where the phase-change material layer 302 contacts the first oxide layer 304), the second stop layer 305, and the second oxide layer 306 are arranged around the optical waveguide layer 301, so that the first oxide layer and the second oxide layer corresponding to the second region are enclosed to form a wrapping layer that wraps downward (i.e., the peripheral edge of the wrapping component extends downward from the top of the wrapped component along the peripheral sidewall height direction to form an enclosing sidewall) of the second region of the phase-change material layer away from the optical waveguide layer, that is, the phase-change material layer is wrapped in a closed cavity formed by the first oxide layer 05, the second oxide layer, the first stop layer, and the second stop layer.

[0074] Preferably, the optical chip in the present invention can be prepared using the optical waveguide in the patent application with publication number CN117706811A.

[0075] It should be noted that the present invention adopts an optical chip made of phase change material to work in coordination with a first electrical chip 2 and a plurality of second electrical chips 4, wherein the non-volatile characteristics of the phase change material layer are beneficial to reducing the input signal pressure of the first electrical chip 2. For example, in a single calculation process, the first electrical chip 2 may input a signal only once (or a limited number of times), and the optical chip can complete the corresponding calculation work normally.

[0076] The large-size electric chip used in this embodiment can complete the external signal input in the entire calculation process with limited power consumption. It can not only reduce its own high demand for heat dissipation (even if it is set in the middle layer, it will not cause poor heat dissipation and malfunction), but also avoid interference with the multiple small-size chips carried on it.

[0077] And after testing and verification, the working stability and accuracy of the packaging structure obtained by this coordinated design of function and position have been significantly improved.

[0078] It should be noted that Figure 1-2cThe matching relationship between the first electrical chip, the second electrical chip, and the optical chip shown may be one of the unit modules of the packaging structure. For example, the packaging structure may also be provided with a plurality of first electrical chips correspondingly, and the plurality of first electrical chips may respectively carry and provide corresponding optical chips and second electrical chips.

[0079] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0080] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0081] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. An optoelectronic chip packaging structure, characterized in that: include: A substrate (1), wherein a signal transmission layer is arranged on the upper surface of the substrate, and a signal processing layer is arranged on the signal transmission layer; The signal transmission layer comprises: at least one first electrical chip (2), the first electrical chip (2) having a first surface and a second surface, wherein the first surface is arranged facing the substrate (1), and the second surface is arranged towards the signal processing layer; The signal processing layer includes: a signal conversion area, and a data storage area; At least one optical chip (3) is correspondingly arranged in the signal conversion area, and the optical chip (3) comprises: N*M photon computing units, and the photon computing units comprise: an optical waveguide layer (301), and a modulation layer (302) located on the optical waveguide layer, wherein the modulation layer is a phase change material layer or the modulation layer comprises a phase change material layer; The optical chip (3) is used to receive a modulation signal input by the first electrical chip (2); at least one group of the photon computing units modulates the corresponding phase change material layer to a specific state in response to the modulation signal; and the photon computing unit completes a corresponding computing task in the specific state and outputs corresponding computing data; At least one second electrical chip (4) is provided corresponding to the data storage area, and the second electrical chip (4) is used to receive and store the calculation data; wherein the electrical connection path from the signal processing layer to the signal transmission layer includes a first bonding structure (5), a first redistribution layer (6), a through silicon via (7), and a second redistribution layer (8) which are passed through in sequence.

2. The optoelectronic chip packaging structure according to claim 1, characterized in that: A heat sink (12) is provided on the signal processing layer, and the lower surface of the heat sink (12) at least covers at least one of the optical chips (3) and the at least one second electrical chip (4).

3. The optoelectronic chip packaging structure according to claim 2, characterized in that: At least two high-bandwidth memory chips are arranged on the second surface of the first electrical chip (2), and the at least two high-bandwidth memory chips are arranged on both sides of the optical chip respectively; The first electrical chip includes: an XDAC control circuit, an XADC control circuit, a WDAC control circuit, and a communication control circuit for communicating with the high-bandwidth memory chip; wherein, The XDAC control circuit is used to provide the corresponding modulation signal to the modulation layer, the XADC control circuit is used to receive the output signal of the photodetector in the photon computing unit, and the WDAC control circuit is used to provide a calculation input signal to the photon computing unit after modulation, and the photon computing unit completes the calculation in response to the calculation input signal and outputs the calculation data.

4. The optoelectronic chip packaging structure according to claim 2, characterized in that: The signal processing layer also includes: a data conversion area communicatively connected to the data storage area, and the data conversion area is correspondingly provided with at least one second electrical chip, and the corresponding second electrical chip receives the corresponding calculation data through the first electrical chip, so as to convert the calculation data into a specific format according to the set data conversion rules, and input the calculation data converted into the specific format into the second electrical chip located in the data storage area.

5. The optoelectronic chip packaging structure according to claim 3 or 4, characterized in that: Also includes: At least one task allocation unit, and at least one of the task allocation units is connected to a corresponding functional partition, and a plurality of the second electrical chips are arranged in the functional partition; The functional partition includes: a data storage area and / or a data conversion area; correspondingly, the task allocation unit is configured to perform the following steps: When at least one of the second electrical chips receives the corresponding calculation data, monitoring the power consumption data of the second electrical chip in the first time period; When the power consumption data is greater than a first set threshold value and less than or equal to a second set threshold value, the first allocation rule is used to allocate and process the current calculation data; wherein the first allocation rule requires suspending the transmission of new calculation data to the current second electrical chip within a second period of time, and selecting the second electrical chip whose spacing with the current second electrical chip is greater than the first spacing to receive the new calculation data to be processed subsequently; When the power consumption data is greater than the second set threshold value and less than or equal to the third set threshold value, the second allocation rule is used to allocate the calculation data; wherein the second allocation rule requires suspending the transmission of the new calculation data to the current second electrical chip during the second time period, and selecting the second electrical chip whose spacing with the current second electrical chip is greater than the second spacing to receive the new calculation data to be processed subsequently, and the second spacing is greater than the first spacing; When the power consumption data is greater than the third set threshold, the calculation data is allocated using a third allocation rule; wherein the third allocation rule requires pausing the processing of the current calculation data by the second electrical chip and reallocating the current calculation data to at least one of the second electrical chips whose spacing from the current second electrical chip is greater than the second spacing.

6. The optoelectronic chip packaging structure according to claim 2, characterized in that: At least one of the second electrical chips (4) is a field programmable logic gate array chip.

7. The optoelectronic chip packaging structure according to claim 2, characterized in that: The first electrical chip (2) is a dedicated integrated circuit chip.

8. The optoelectronic chip packaging structure according to claim 2, characterized in that: The first bonding structure is a conductive bump.

9. The optoelectronic chip packaging structure according to claim 2, characterized in that: The second bonding structure is a conductive bump.

10. The optoelectronic chip packaging structure according to claim 2, characterized in that: The second bonding structure is a solder ball.

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