Time synchronization system and method, vehicle and storage medium

Abstract

The invention provides a time synchronization system and method, a vehicle and a storage medium, and belongs to the technical field of intelligent driving. The SOC comprises a first processing unit, a second processing unit and a hardware clock, the first processing unit and the second processing unit are respectively connected with the hardware clock, the first processing unit is further connected with the MCU, and the starting duration of the first processing unit is smaller than that of the second processing unit; the MCU is used for sending system time to the first processing unit; the first processing unit is used for writing system time received after starting is completed into a hardware clock; the hardware clock is used for updating the system time through a self clock by taking the written system time as the reference time; and the second processing unit is used for acquiring the newest system time from the hardware clock and recording the starting data in the starting process based on the newest system time. According to the scheme, the second processing unit can use accurate system time to record the starting data earlier.

Description

Technical Field

[0001] The present application belongs to the field of intelligent driving technology, and in particular, relates to a time synchronization system, method, vehicle and storage medium. Background Art

[0002] The intelligent driving domain controller or central controller plays a vital role in the intelligent driving process. Both the intelligent driving domain controller and the central controller include multiple processing units. In order to achieve safe and reliable intelligent driving, time synchronization is required between the multiple processing units.

[0003] In the related art, the intelligent driving domain controller or central controller can be a system on chip (System onChip, SOC). The time synchronization of SOC depends on the completion of system startup, so the time synchronization can only be performed after the processing unit (such as A core) used to record startup data in SOC completes the startup of the operating system. Therefore, before the startup of the operating system is completed, the system time of SOC is generally the default time or the time when SOC was last powered off.

[0004] In the above-mentioned related technologies, the SOC cannot obtain the accurate time before the operating system completes the startup, which leads to inaccurate time of the startup data recorded by the processing unit (such as A core) used to record the startup data during the startup of the operating system, for example, inaccurate timestamps on the log file name and log content, etc., which brings serious inconvenience to the subsequent analysis of the log file. Summary of the invention

[0005] The purpose of the present application is to provide a time synchronization system, method, vehicle and storage medium, aiming to solve the problem of inaccurate time synchronization in the traditional SOC startup process.

[0006] A first aspect of an embodiment of the present application provides a time synchronization system, the system comprising: a system on chip SOC and a microcontroller unit MCU; the SOC comprises a first processing unit, a second processing unit and a hardware clock, the first processing unit and the second processing unit are respectively connected to the hardware clock, the first processing unit is also connected to the MCU, and the startup time length of the first processing unit is shorter than that of the second processing unit;

[0007] The MCU is used to send system time to the first processing unit;

[0008] The first processing unit is used to write the system time received after the startup is completed into the hardware clock;

[0009] The hardware clock is used to update the system time by its own clock, taking the written system time as the reference time;

[0010] The second processing unit is used to obtain the latest system time from the hardware clock, and record the startup data in the startup process based on the latest system time.

[0011] In some embodiments, the first processing unit and the MCU are connected via a hardwire;

[0012] The MCU is further used to periodically generate a pulse and transmit the pulse to the first processing unit via the hard line;

[0013] The first processing unit is further configured to adjust the system time in response to the pulse after receiving the system time sent by the MCU to obtain the adjusted system time, and write the adjusted system time into the hardware clock.

[0014] In some embodiments, the MCU generates a pulse per second, and the first processing unit is used to round up the system time last received before receiving the pulse in response to the pulse to obtain the adjusted system time.

[0015] In some embodiments, the MCU is also connected to a clock device other than the time synchronization system;

[0016] The MCU is used for obtaining the system time from the clock device and updating the system time through its own clock after being awakened.

[0017] In some embodiments, the MCU is used to periodically send the system time to the first processing unit;

[0018] The first processing unit is further configured to perform a validity check on the received system time, and when the check passes, send a confirmation message to the MCU, wherein the confirmation message is used to notify the MCU that the system time has been received;

[0019] The MCU is further configured to stop periodically sending the system time to the first processing unit in response to receiving the confirmation information.

[0020] In some embodiments, the second processing unit is further used to continue to obtain the latest system time from the hardware clock after the startup is completed, and record the operation data after the startup based on the latest system time.

[0021] In some embodiments, the system further comprises a storage unit, wherein the storage unit is connected to the first processing unit and the second processing unit respectively;

[0022] The first processing unit is further used to record the number of startups of the second processing unit and write the number of startups into the storage unit;

[0023] The second processing unit is further configured to read the startup times of the first processing unit from the storage unit.

[0024] A second aspect of an embodiment of the present application provides a time synchronization method, which is applied to the time synchronization system described in the first aspect. The method includes:

[0025] Sending system time to the first processing unit via the control unit MCU;

[0026] Writing the system time received after the startup is completed into the hardware clock by the first processing unit;

[0027] The hardware clock uses the written system time as the reference time and updates the system time through its own clock;

[0028] Acquiring the latest system time from the hardware clock through the second processing unit, and recording the startup data in the startup process based on the latest system time;

[0029] The startup time of the first processing unit is shorter than that of the second processing unit.

[0030] A third aspect of an embodiment of the present application provides a vehicle, comprising a time synchronization system as described in the first aspect above; comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the time synchronization method as described above when executing the computer program.

[0031] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the time synchronization method described above is implemented.

[0032] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0033] In an embodiment of the present application, the first processing unit is connected to the MCU, so that the MCU can send the system time to the first processing unit, and the first processing unit can write the system time sent by the MCU into the hardware clock, and the hardware clock is connected to the first processing unit and the second processing unit at the same time. In this way, since the startup time of the first processing unit is short, the first processing unit can obtain the system time in time, so that the second processing unit can obtain the accurate system time earlier, so that the second processing can record the startup data with more accurate system time during the startup process, thereby improving the accuracy of the system time in the startup data and facilitating subsequent data analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of a time synchronization system provided by an exemplary embodiment is shown;

[0035] Figure 2 A schematic diagram of a time synchronization system and a clock device provided by an exemplary embodiment is shown;

[0036] Figure 3 A schematic diagram of a time synchronization system provided by an exemplary embodiment is shown;

[0037] Figure 4 shows the relationship between pulse generation time and system time provided by an exemplary embodiment;

[0038] Figure 5 shows the relationship between pulse generation time and system time provided by an exemplary embodiment;

[0039] Figure 6 A flowchart of a time synchronization method provided by an exemplary embodiment is shown;

[0040] Figure 7 A timing diagram of a time synchronization method provided by an exemplary embodiment is shown;

[0041] Figure 8 A schematic structural diagram of a vehicle is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0044] The vehicle is usually controlled by an intelligent driving domain controller or a central controller to realize intelligent driving functions such as automatic driving and assisted driving. Among them, the intelligent driving domain controller and the central controller both include multiple processing units, and the intelligent driving of the vehicle is controlled through the interaction between these processing units. Therefore, in order to realize safe and reliable intelligent driving, time synchronization is required between the multiple processing units.

[0045] In some embodiments, the intelligent driving domain controller or central controller may be a system on chip (System on Chip, SOC). The time synchronization of SOC depends on the completion of system startup, that is, only after the SOC startup is completed, can the time synchronization be performed based on the system time of SOC. During the system startup process of SOC, SOC can only use the default time or the time when SOC was last powered off as the system time, so the system time is not accurate.

[0046] However, during the process of operating system startup, the system time of the operating system is obtained, and the startup data is recorded based on the system time. For example, the system time of the operating system is used as the file name of the log file and the timestamp on the log content, so as to record the log file, etc. However, since the system time of the SOC is not accurate before the startup is completed, the time used when executing the system task is inaccurate, which brings serious inconvenience to the subsequent analysis of the results of the execution of the task.

[0047] The SOC includes a second processing unit (e.g., Acore) for recording startup data, operation data, human-computer interaction and other services, and a first processing unit (e.g., M core) with high real-time performance and low power consumption, wherein the operating system of the SOC is generally integrated in the second processing unit of the SOC. The startup time of the first processing unit is shorter than the startup time of the second processing unit. The startup time refers to the time required for the processing unit to fully start from receiving the startup instruction.

[0048] In summary, in order to enable the SOC to obtain accurate system time during the startup process, the present application provides a time synchronization system, method, vehicle and storage medium. Figure 1, which shows a schematic diagram of a time synchronization system provided by an exemplary embodiment. The time synchronization system includes: a SOC 10 and a microcontroller unit (MCU) 20 .

[0049] In some embodiments, please see Figure 1 The SOC 10 includes a first processing unit 11, a second processing unit 12 and a hardware clock 13. The first processing unit 11 and the second processing unit 12 are respectively connected to the hardware clock 13. The first processing unit 11 is also connected to the MCU 20. The startup time of the first processing unit 11 is shorter than that of the second processing unit 12.

[0050] The first processing unit 11 is a processing unit with high real-time performance and low power consumption, and the second processing unit 12 is a processing unit for recording startup data, operation data, human-computer interaction and other services. For example, the first processing unit 11 is the M core in the SOC10, and the second processing unit 12 is the A core in the SOC10. The hardware clock 13 can be any clock that can perform time synchronization, for example, the hardware clock 13 is a hw clock. The first processing unit 11 and the second processing unit 12 are both connected to the hardware clock 13.

[0051] The first processing unit 11 is also connected to the MCU20. The first processing unit 11 is connected to the MCU20 via a preset communication interface. For example, the first processing unit 11 is connected to the MCU20 via a serial peripheral interface (SPI) protocol. Alternatively, the first processing unit 11 is connected to the MCU20 via a universal asynchronous receiver / transmitter (UART). Alternatively, the first processing unit 11 is connected to the MCU20 via an inter-integrated circuit (I2C). In the embodiment of the present application, the connection method between the first processing unit 11 and the MCU20 is not specifically limited.

[0052] It should be noted that the number of the first processing unit 11, the second processing unit 12 and the hardware clock 13 in the SOC 10 can be one or more, and this is not specifically limited in the embodiment of the present application. In addition, the hardware clock 13 can be connected to one first processing unit 11 and one second processing unit 12 respectively; the hardware clock 13 can also be connected to one first processing unit 11 and multiple second processing units 12 respectively. This is not specifically limited in the embodiment of the present application.

[0053] The MCU 20 is used to send the current system time to the first processing unit 11 .

[0054] In some embodiments, the SOC10 is started by the MCU20, and accordingly, the MCU20 sends a start-up instruction to the SOC10. The SOC10 starts the first processing unit 11 and the second processing unit 12 in response to receiving the start-up instruction. In some embodiments, the MCU20 sends a start-up instruction to the SOC10, and the SOC10 controls the first processing unit 11 and the second processing unit 12 to start. In some embodiments, the MUC sends a start-up instruction to the first processing unit 11 and the second processing unit 12 in the SOC10, and accordingly, the first processing unit 11 and the second processing unit 12 start to start based on the start-up instruction.

[0055] After sending the startup instruction to the SOC 10 , the MCU 20 sends the current system time to the first processing unit 11 .

[0056] After being awakened, the MCU 20 first obtains the current system time, and calculates and updates the system time through its own clock, so as to be subsequently synchronized to the first processing unit 11 of the SOC 10 .

[0057] In some embodiments, see Figure 2 , which shows a schematic diagram of a time synchronization system and a clock device provided by an exemplary embodiment. The MCU 20 is also connected to a clock device 30 outside the time synchronization system; the MCU 20 is used to obtain the system time from the clock device 30 and update the system time through its own clock after being awakened.

[0058] The clock device 30 outside the time synchronization system may be any device that can provide system time to the MCU 20. For example, the clock device 30 may be a telematics-BOX (TBOX), a real-time clock (RTC), etc. In the embodiment of the present application, the type of the clock device 30 is not specifically limited.

[0059] Accordingly, when the clock device 30 is a TBOX, MCU20 can be connected to the TBOX through a preset communication interface. For example, MCU20 and TBOX are connected through an Ethernet (ETH) protocol interface. Alternatively, MCU20 and TBOX are connected through UART. Alternatively, MCU20 and TBOX are connected through SPI. In the embodiment of the present application, the communication connection mode between MCU20 and TBOX is not specifically limited. When the clock device 30 is an RTC, MCU20 can be connected to the RTC through a physical hard line.

[0060] The first processing unit 11 is used to write the system time received after the startup is completed into the hardware clock 13.

[0061] After MCU20 controls SOC10 to start, it sends the system time to the first processing unit 11. Since the startup time of the first processing unit 11 is short, the latest system time sent by MCU20 can be received in time after the first processing unit 11 is started. In some embodiments, the MCU20 is used to periodically send the system time to the first processing unit 11; the first processing unit 11 is also used to perform a validity check on the received system time, and when the check passes, send a confirmation message to the MCU20, the confirmation message is used to notify the MCU20 that the system time has been received; the MCU20 is also used to stop periodically sending the system time to the first processing unit 11 in response to receiving the confirmation message.

[0062] The period of sending the system time from the MCU 20 to the first processing unit 11 can be set as needed, and in the embodiment of the present application, the period of sending is not specifically limited. For example, the period of sending can be 1 second, 2 seconds, etc.

[0063] The first processing unit 11 performs a validity check on the system time sent by the MCU 20, which means determining whether the received system time is legal through a preset verification standard. The preset verification standard may be a preset time standard. The time standard may be the factory time of the MCU 20, the time set by the developer, etc. Accordingly, when the system time is after the time standard, it is determined that the system time has passed the validity check.

[0064] Since the first processing unit 11 and MCU20 are connected via a preset communication interface, MCU20 can send a synchronization message carrying the system time to the first processing unit 11 via the communication interface. During the transmission of the synchronization message, there may be a delay. In order to further prevent the transmission delay from affecting the accuracy of the system time sent by MCU20 to the first processing unit 11, the present application proposes a method for adjusting the system time by periodically generating pulses by MCU20. Accordingly, see Figure 3 , which shows a schematic diagram of a time synchronization system provided by an exemplary embodiment.

[0065] See also Figure 3The first processing unit 11 and the MCU 20 are connected via a hard line 40; the MCU 20 is also used to periodically generate a pulse and transmit the pulse to the first processing unit 11 via the hard line 40; the first processing unit 11 is also used to adjust the system time in response to the pulse after receiving the system time sent by the MCU 20, obtain the adjusted system time, and write the adjusted system time into the hardware clock 13.

[0066] MCU20 periodically generates a pulse and transmits the pulse to the first processing unit 11 through hard line 40. Since the pulse generation period is fixed and the delay of transmitting the pulse through hard line 40 is much smaller than the delay of transmitting the message through the preset communication interface, after receiving the pulse, the first processing unit 11 can adjust the system time that was most recently received before receiving the pulse based on the pulse period.

[0067] The pulse period of the pulse generated by the MCU 20 can be set as needed. In the embodiment of the present application, the pulse period is not specifically limited. For example, the pulse period can be 1 second, that is, the MCU 20 generates a pulse per second. Alternatively, the pulse period can be 0.5 seconds, that is, the MCU 20 generates a pulse every 0.5 seconds.

[0068] The following describes the manner in which the first processing unit 11 adjusts the received system time based on the pulse.

[0069] In some embodiments, the MCU 20 generates a pulse per second, and the first processing unit 11 is used to respond to the pulse and round up the system time last received before receiving the pulse to obtain the adjusted system time.

[0070] When MCU20 generates a pulse per second, MCU20 is set to generate a pulse at the whole second. When the first processing unit 11 receives the pulse, it can determine that the current time is the whole second. Therefore, the system time last received before receiving the pulse can be rounded online to determine the current whole second.

[0071] For example, see Figure 4 , which shows the relationship between the pulse generation time and the system time provided by an exemplary embodiment. Figure 4 , when MCU20 generates a pulse every second and at the whole second, each pulse is separated by 1 second. When MCU20 sends a synchronization message containing the system time to the first processing unit 11 at 1.6 seconds, due to communication delay, the actual time when the first processing unit 11 receives the message is Figure 4The time point corresponding to the SPI-Timesync shown in the figure shows that when the first processing unit 11 receives the synchronization message, if it is still recorded as 1.6 seconds, there is an error with the actual time. When the first processing unit 11 receives pulse 2, the first processing unit 11 determines that the current time is a whole second, and the system time recorded in the last received synchronization message before receiving the pulse is 1.6 seconds, then it can be determined that the current time is the smallest whole second after 1.6 seconds, that is, the current system time is 2 seconds.

[0072] For example, see Figure 5 , which shows the relationship between the pulse generation time and the system time provided by an exemplary embodiment. Figure 5 , when MCU20 generates pulses every 0.5 seconds and at full seconds and half seconds, that is, the interval between each pulse is 0.5 seconds, when MCU20 sends a synchronization message containing the system time to the first processing unit 11 at 1.1 seconds, due to communication delay, the actual time when the first processing unit 11 receives the message is Figure 5 The time point corresponding to the SPI-Timesync shown in the figure shows that when the first processing unit 11 receives the synchronization message, if it is still recorded as 1.1 seconds, there is an error with the actual time. When the first processing unit 11 receives pulse 2, the first processing unit 11 determines that the current time is a whole second or half a second, and the system time recorded in the last synchronization message received before receiving the pulse is 1.1 seconds, then it can be determined that the current time is the smallest whole second or half a second after 1.1 seconds, that is, the current system time is 1.5 seconds.

[0073] It should be noted that, in order to make the adjusted system time more accurate, in the embodiment of the present application, the MCU 20 sends a synchronization message containing the system time to the first processing unit 11 within a preset time length before each pulse is generated. The preset time length can be set as needed, and in the embodiment of the present application, the preset time length is not specifically limited. For example, the preset time length can be 500 milliseconds, 450 milliseconds, or 400 milliseconds.

[0074] After adjusting the system time, the first processing unit 11 writes the adjusted system time into the hardware clock 13. The hardware clock 13 is used to respond to the system time written by the first processing unit 11, take the system time as the startup time, and continue to automatically run to maintain the system time. The second processing unit 12 is used to obtain the current system time from the hardware clock 13 during the startup process, and execute the system application required by the second processing unit 12 during the startup process based on the system time.

[0075] It should be noted that SOC10 may include multiple hardware clocks 13. In order for the second processing unit 12 to obtain the latest system time from the hardware clock 13 in a timely manner, the hardware clock 13 needs to be a hardware clock 13 connected to the first processing unit 11 and the second processing unit 12 at the same time.

[0076] The second processing unit 12 is configured to use the hardware clock 13 as a system time source, so that during the startup of the second processing unit 12, the second unit can obtain the latest system time from the hardware clock 13. Therefore, the system application is executed and the startup data is recorded according to the latest system time obtained from the hardware clock 13. For example, the second processing unit 12 obtains the latest system time from the hardware clock 13, and timestamps the file name, file content and other data of the log file according to the latest system time.

[0077] The first processing unit 11 is connected to the MCU20, so that the MCU20 can send the system time to the first processing unit 11, and the first processing unit 11 can write the system time sent by the MCU20 into the hardware clock 13, and the hardware clock 13 is connected to the first processing unit 11 and the second processing unit 12 at the same time. In this way, since the startup time of the first processing unit 11 is short, the first processing unit 11 can obtain the system time in time, so that the second processing unit 12 can obtain the accurate system time earlier, so that the second processing can record the startup data with more accurate system time during the startup process, thereby improving the accuracy of the system time in the startup data and facilitating subsequent data analysis.

[0078] In some embodiments, after the startup is completed, the second processing unit 12 still uses the hardware clock 13 as the system time source and obtains the latest system time from the hardware clock 13. Accordingly, the second processing unit 12 is also used to continue to obtain the latest system time from the hardware clock 13 after the startup is completed, and record the operation data after the startup based on the latest system time.

[0079] After the second processing unit 12 is started, the hardware clock 13 continues to be used as the system time source, thereby improving the accuracy of the system for recording operating data.

[0080] In some embodiments, in addition to the system time, other information can also be synchronized through the above system. For example, the number of startups of the first processing unit 11. Accordingly, the system also includes a storage unit, which is connected to the first processing unit 11 and the second processing unit 12 respectively; the first processing unit 11 is also used to record the number of startups of the second processing unit 12 and write the number of startups into the storage unit; the second processing unit 12 is also used to read the number of startups of the first processing unit 11 from the storage unit.

[0081] By connecting a storage unit between the first processing unit 11 and the second processing unit 12 that can simultaneously exchange data with the first processing unit 11 and the second processing unit 12, the first processing unit 11 can write relevant information into the storage unit so that the second processing unit 12 can obtain accurate information in a timely manner, thereby preventing the second processing unit 12 from losing information or obtaining information in a timely manner due to slow startup.

[0082] The following is an introduction to the time synchronization method implemented by the above time synchronization system in a specific process. Figure 6 , which shows a flow chart of a time synchronization method provided by an exemplary embodiment. The method is applied to the above-mentioned time synchronization system.

[0083] S601, the MCU obtains the system time from a clock device other than the time system.

[0084] The clock device other than the time synchronization system can be any device that can provide the system time to the MCU. For example, the clock device can be a vehicle-mounted electrical component (Telematics-BOX, TBOX), a real-time clock (Real TimeClock, RTC), etc. In the embodiment of the present application, the type of the clock device is not specifically limited.

[0085] Accordingly, when the clock device is a TBOX, the MCU can be connected to the TBOX through a preset communication interface. For example, the MCU and the TBOX are connected through an Ethernet (ETH) protocol interface. Alternatively, the MCU and the TBOX are connected through a UART. Alternatively, the MCU and the TBOX are connected through an SPI. In the embodiment of the present application, the communication connection mode between the MCU and the TBOX is not specifically limited. When the clock device is an RTC, the MCU can be connected to the RTC through a physical hard line.

[0086] See also Figure 7 , which shows a timing diagram of a time synchronization method provided by an exemplary embodiment. After the MCU is awakened, the MCU starts to start, and after the MCU starts, the MCU sends a start instruction to the SOC, and the MUC obtains the system time.

[0087] S602: The MCU sends the system time to the first processing unit.

[0088] Since the startup time of the first processing unit is relatively short, the latest system time sent by the MCU can be received in time after the first processing unit is started. In some embodiments, the MCU periodically sends the system time to the first processing unit; the first processing unit performs a validity check on the received system time, and when the check passes, sends a confirmation message to the MCU, the confirmation message is used to notify the MCU that the system time has been received; in response to receiving the confirmation message, the MCU stops periodically sending the system time to the first processing unit.

[0089] The period of the MCU periodically sending the system time to the first processing unit can be set as needed, and in the embodiment of the present application, the period of the sending is not specifically limited. For example, the period of the sending can be 1 second, 2 seconds, etc.

[0090] The first processing unit performs a validity check on the system time sent by the MCU, which means determining whether the received system time is legal through a preset verification standard. The preset verification standard may be a preset time standard. The time standard may be the factory time of the MCU, the time set by the developer, etc. Accordingly, when the system time is after the time standard, it is determined that the system time has passed the validity check.

[0091] In order to further prevent the transmission delay from affecting the accuracy of the system time sent by the MCU to the first processing unit, the present application proposes a method for adjusting the system time by periodically generating pulses by the MCU. Accordingly, the MCU periodically generates a pulse, and transmits the pulse to the first processing unit through the hard line; after receiving the system time sent by the MCU, the first processing unit adjusts the system time in response to the pulse to obtain the adjusted system time, and writes the adjusted system time into the hardware clock.

[0092] The MCU periodically generates a pulse and transmits the pulse to the first processing unit via a hard line. Since the pulse generation period is fixed and the delay of transmitting the pulse via the hard line is much smaller than the delay of transmitting the message via the preset communication interface, after receiving the pulse, the first processing unit can adjust the system time that was most recently received before receiving the pulse based on the pulse period.

[0093] The pulse period of the pulse generated by the MCU can be set as needed. In the embodiment of the present application, the pulse period is not specifically limited. For example, the pulse period can be 1 second, that is, the MCU generates a pulse per second. Alternatively, the pulse period can be 0.5 seconds, that is, the MCU generates a pulse every 0.5 seconds.

[0094] The following describes the manner in which the first processing unit adjusts the received system time based on the pulse.

[0095] In some embodiments, the MCU generates a pulse per second, and the first processing unit is used to respond to the pulse and round up the system time last received before receiving the pulse to obtain the adjusted system time.

[0096] When the MCU generates a pulse per second, the MCU is set to generate a pulse at the whole second. When the first processing unit receives the pulse, it can determine that the current time is the whole second. Therefore, the system time last received before receiving the pulse can be rounded online to determine the current whole second.

[0097] For example, see Figure 4 , which shows the relationship between the pulse generation time and the system time provided by an exemplary embodiment of the present application. Figure 4 , when the MCU generates a pulse every second and at the whole second, each pulse is separated by 1 second. When the MCU sends a synchronization message containing the system time to the first processing unit at 1.6 seconds, due to the communication delay, the actual time when the first processing unit receives the message is Figure 4 The time point corresponding to the SPI-Timesync shown in the figure shows that when the first processing unit receives the synchronization message, if it is still recorded as 1.6 seconds, there is an error with the actual time. When the first processing unit receives the pulse, the first processing unit determines that the current time is a whole second, and the system time recorded in the last received synchronization message before receiving the pulse is 1.6 seconds, then it can be determined that the current time is the smallest whole second after 1.6 seconds, that is, the current system time is 2 seconds.

[0098] For example, see Figure 5 , which shows the relationship between the pulse generation time and the system time provided by an exemplary embodiment of the present application. Figure 5 , when the MCU generates pulses every 0.5 seconds and at full seconds and half seconds, that is, the interval between each pulse is 0.5 seconds, when the MCU sends a synchronization message containing the system time to the first processing unit at 1.1 seconds, due to communication delay, the actual time when the first processing unit receives the message is Figure 5 The time point corresponding to the SPI-Timesync shown in the figure shows that when the first processing unit receives the synchronization message, if it is still recorded as 1.1 seconds, there is an error with the actual time. When the first processing unit receives the pulse, the first processing unit determines that the current time is a whole second or half a second, and the system time recorded in the last received synchronization message before receiving the pulse is 1.1 seconds, then it can be determined that the current time is the smallest whole second or half a second after 1.1 seconds, that is, the current system time is 1.5 seconds.

[0099] It should be noted that, in order to make the adjusted system time more accurate, in the embodiment of the present application, the MCU sends a synchronization message containing the system time to the first processing unit within a preset time length before each pulse is generated. The preset time length can be set as needed, and in the embodiment of the present application, the preset time length is not specifically limited. For example, the preset time length can be 500 milliseconds, 450 milliseconds, or 400 milliseconds.

[0100] S603: The first processing unit writes the system time received after the startup is completed into the hardware clock.

[0101] The hardware clock can exchange data with the first processing unit and the second processing unit. Figure 7 , the first processing unit writes the system time into the hardware clock in a timely manner.

[0102] S604: The hardware clock uses the written system time as the reference time and updates the system time through its own clock.

[0103] The hardware clock uses the written system time as the reference time, starts the clock, and updates the system time through its own clock, so that the system time in the hardware clock can remain accurate.

[0104] S605: The second processing unit obtains the latest system time from the hardware clock, and records the startup data in the startup process based on the latest system time.

[0105] The second processing unit is configured to use the hardware clock as a system time source, so that during the startup of the second processing unit, the second unit can obtain the latest system time from the hardware clock. Thus, the system application is executed and the startup data is recorded using the latest system time obtained from the hardware clock. For example, the second processing unit obtains the latest system time from the hardware clock and timestamps the file name, file content and other data of the log file using the latest system time.

[0106] In some embodiments, after the second processing unit is started up, it still uses the hardware clock as the system time source and obtains the latest system time from the hardware clock. Accordingly, after the second processing unit is started up, it continues to obtain the latest system time from the hardware clock and records the operation data after the start-up based on the latest system time.

[0107] After the second processing unit is started up, the hardware clock continues to be used as the system time source, thereby improving the accuracy of the system for recording operating data.

[0108] In some embodiments, in addition to the system time, other information may also be synchronized through the above system. For example, the number of times the first processing unit is started. Accordingly, the first processing unit records the number of times the second processing unit is started, and writes the number of times the second processing unit is started into the storage unit; the second processing unit reads the number of times the first processing unit is started from the storage unit.

[0109] By connecting a storage unit between the first processing unit and the second processing unit that can exchange data with the first processing unit and the second processing unit at the same time, the first processing unit can write relevant information into the storage unit so that the second processing unit can obtain accurate information in a timely manner, thereby preventing the second processing unit from losing information or obtaining information in a timely manner due to slow startup.

[0110] In an embodiment of the present application, the first processing unit is connected to the MCU, so that the MCU can send the system time to the first processing unit, and the first processing unit can write the system time sent by the MCU into the hardware clock, and the hardware clock is connected to the first processing unit and the second processing unit at the same time. In this way, since the startup time of the first processing unit is short, the first processing unit can obtain the system time in time, so that the second processing unit can obtain the accurate system time earlier, so that the second processing can record the startup data with more accurate system time during the startup process, thereby improving the accuracy of the system time in the startup data and facilitating subsequent data analysis.

[0111] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0112] Figure 8 FIG. 1 is a schematic diagram of a vehicle provided by an exemplary embodiment of the present application. Figure 8 As shown, the vehicle 8 of this embodiment includes: a processor 80, a memory 81, and a computer program 82 stored in the memory 81 and executable on the processor 80, such as a time synchronization program. When the processor 80 executes the computer program 82, the steps in the above-mentioned various time synchronization method embodiments are implemented, such as Figure 6 Alternatively, when the processor 80 executes the computer program 82, the functions of each unit in the above-mentioned time synchronization system embodiment are realized, for example Figure 1 The functions of the first processing unit, the second processing unit and the MCU are shown.

[0113] Exemplarily, the computer program 82 may be divided into one or more units, which are stored in the memory 81 and executed by the processor 80 to complete the present application. The one or more units may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program 82 in the vehicle 8.

[0114] The vehicle 8 may be any vehicle with intelligent driving function. The vehicle 8 may include, but is not limited to, a processor 80 and a memory 81. Those skilled in the art will appreciate that Figure 8 It is only an example of the vehicle 8 and does not constitute a limitation of the vehicle 8. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the vehicle 8 may also include input and output devices, network access devices, buses, etc.

[0115] The processor 80 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0116] The memory 81 may be an internal storage unit of the vehicle 8, such as a hard disk or memory of the vehicle 8. The memory 81 may also be an external storage device of the vehicle 8, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the vehicle 8. Further, the memory 81 may also include both an internal storage unit of the vehicle 8 and an external storage device. The memory 81 is used to store the computer program and other programs and data required by the terminal device. The memory 81 may also be used to temporarily store data that has been output or is to be output.

[0117] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0118] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0119] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0120] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0121] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0123] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0124] The embodiments of the present application further provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0125] The embodiment of the present application also provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0126] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A time synchronization system, characterized in that: The system comprises: a system on chip SOC and a microcontroller unit MCU; the SOC comprises a first processing unit, a second processing unit and a hardware clock, the first processing unit and the second processing unit are respectively connected to the hardware clock, the first processing unit is also connected to the MCU, and the startup time of the first processing unit is shorter than that of the second processing unit; The MCU is used to send system time to the first processing unit; The first processing unit is used to write the system time received after the startup is completed into the hardware clock; The hardware clock is used to update the system time by its own clock, taking the written system time as the reference time; The second processing unit is used to obtain the latest system time from the hardware clock, and record the startup data in the startup process based on the latest system time.

2. The system according to claim 1, characterized in that The first processing unit and the MCU are connected via a hard line; The MCU is further used to periodically generate a pulse and transmit the pulse to the first processing unit via the hard line; The first processing unit is further configured to adjust the system time in response to the pulse after receiving the system time sent by the MCU to obtain the adjusted system time, and write the adjusted system time into the hardware clock.

3. The system according to claim 2, characterized in that The MCU generates a pulse per second, and the first processing unit is used to respond to the pulse and round up the system time last received before receiving the pulse to obtain the adjusted system time.

4. The system according to any one of claims 1 to 3, characterized in that: The MCU is also connected to a clock device outside the time synchronization system; The MCU is used for obtaining the system time from the clock device and updating the system time through its own clock after being awakened.

5. The system according to any one of claims 1 to 3, characterized in that: The MCU is used to periodically send the system time to the first processing unit; The first processing unit is further configured to perform a validity check on the received system time, and when the check passes, send a confirmation message to the MCU, wherein the confirmation message is used to notify the MCU that the system time has been received; The MCU is further configured to stop periodically sending the system time to the first processing unit in response to receiving the confirmation information.

6. The system according to any one of claims 1 to 3, characterized in that: The second processing unit is further configured to continue to obtain the latest system time from the hardware clock after the startup is completed, and record the operation data after the startup based on the latest system time.

7. The system according to any one of claims 1 to 3, characterized in that: The system further comprises a storage unit, wherein the storage unit is connected to the first processing unit and the second processing unit respectively; The first processing unit is further used to record the number of startups of the second processing unit and write the number of startups into the storage unit; The second processing unit is further configured to read the startup times of the first processing unit from the storage unit.

8. A time synchronization method, characterized in that: The method is applied to the time synchronization system according to any one of claims 1 to 7, and the method comprises: Sending system time to the first processing unit via the control unit MCU; Writing the system time received after the startup is completed into the hardware clock by the first processing unit; The hardware clock uses the written system time as the reference time and updates the system time through its own clock; Acquiring the latest system time from the hardware clock through the second processing unit, and recording the startup data in the startup process based on the latest system time; The startup time of the first processing unit is shorter than that of the second processing unit.

9. A vehicle, characterized in that: The vehicle comprises a time synchronization system as claimed in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the time synchronization method according to claim 8 when executed by a processor.

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