EDPP function implementation method

Abstract

The invention belongs to the technical field of power supply control, and discloses an EDPP function implementation method, which comprises the following steps: output gain is high enough, the problem of saturation of a heavy-load resonant inductor is avoided, an input preceding stage cannot drop too deep, a PFC voltage loop is fast enough, BULK capacitance is as large as possible, output capacitance is as large as possible, output ripple is small, and output support time is long. Current oscillation downtime caused by EDDP mutual grabbing of different-source input is avoided, the loop algorithm needs to be as fast and stable as possible, and the ADC sampling interruption frequency is improved. The method has the beneficial effects that the compatibility of a power supply matching system is effectively improved, and the method can better adapt to current mainstream AI servers, ChatGPT applications and GPU applications; eDPP pressure tests of 2 + 0, 3 + 0, 3 + 1 and the like of the system are met.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply control, and in particular to a method for realizing an EDPP function. Background Art

[0002] The GPU cards developed by the current mainstream graphics card (hereinafter referred to as GPU cards) manufacturers (NVIDIA, Intel, AMD) all have a performance parameter called EDPP (Electrical Date Peak Processing). The specific definition is: under certain test conditions, the GPU card is working, and the performance of the GPU chip can be exerted to more than 90%. At this time, the average current of the 12V power input of the CPU card within 200us / 1ms / 5ms is called the EDPP of the GPU card. Usually combined with the system EDPP test, under the 10Hz and 1kHz test conditions, the LLC_IP is most likely to be triggered.

[0003] (OPP) pin protection, namely CT protection, is connected to the secondary side microcontroller comparator after resonant cavity current filtering, and the comparator threshold is set to 3.15V.

[0004] Therefore, it is necessary to provide a method specifically for implementing the EDPP function, effectively improving the compatibility of the power supply system, and better adapting to the current mainstream AI servers, ChatGPT applications, and GPU applications; meeting the system 2+0, 3+0, 3+1 and other EDPP stress tests. Summary of the invention

[0005] The invention discloses a method for realizing an EDPP function, which relates to a power supply current sharing loop control technology, the LLC digital control technology field, and in particular to LLC output gain, and can effectively solve the technical problems involved in the background technology.

[0006] To achieve the above object, the technical solution of the present invention is:

[0007] A method for implementing an EDPP function comprises the following steps:

[0008] S1. Improve the output gain of the power supply circuit;

[0009] S2. Reduce the drop of input voltage of the power supply circuit;

[0010] S3, increase the output capacitance of the power supply circuit;

[0011] S4, increase the speed of the current sharing loop of the power supply circuit;

[0012] S5. Reduce the output ripple of the power supply circuit;

[0013] S6. The output overcurrent protection is designed around the EDDP condition and cannot trigger the protection action by mistake.

[0014] S7. Increase the ADC sampling interrupt frequency of the power supply circuit.

[0015] As a preferred improvement of the present invention: the power supply circuit includes an input terminal Vin, the positive end of the input terminal Vin is connected to the drain of the MOS tube Q1, the source of the MOS tube Q1 is connected to the drain of the MOS tube Q2 and one end of the capacitor Cr, the other end of the capacitor Cr is connected to one end of the inductor Ls, the other end of the inductor Ls is connected to one end of the inductor Lp and the pin 1 of the transformer T1, and the negative end of the input terminal Vin is connected to the source of the MOS tube Q2, the other end of the inductor Lp and the pin 2 of the transformer T1;

[0016] Pin 3 of the transformer T1 is connected to the positive end of the diode D1, the negative end of the diode D1 is connected to the negative end of the diode D2, one end of the capacitor Cout and one end of the output port, pin 4 of the transformer T1 is connected to pin 5 of the transformer T1, the other end of the capacitor Cout and the other end of the output port, and pin 6 of the transformer T1 is connected to the positive end of the diode D2.

[0017] As a preferred improvement of the present invention: the power supply circuit outputs Vo=12V, k=Lp / Ls, and in step S1, k is 10.

[0018] As a preferred improvement of the present invention: in the step S2, the input terminal Vin is a bus capacitor, and the capacitance value of the bus capacitor is increased.

[0019] As a preferred improvement of the present invention: in step S3, the capacitance value of capacitor Cout is increased.

[0020] As a preferred improvement of the present invention: in step S4, the current sharing loop process is: the I-SHAER voltage and the Isense voltage are both subjected to software moving average filtering, and then the difference is taken to obtain the current error. When the current error passes through the error hysteresis comparator, the relevant PI loop operation is performed to obtain the output of the current sharing loop, which is then processed by the limiter and its output is superimposed on the compensation amount of the output voltage.

[0021] As a preferred improvement of the present invention: in the step S5, the power frequency ripple is reduced by the software AC ripple suppression function, and the output ripple of the power supply circuit is reduced to within 80mv.

[0022] As a preferred improvement of the present invention: the lowest protection point of the input terminal Vin is set to 310V.

[0023] As a preferred improvement of the present invention: in step S7, the ADC sampling interrupt frequency is set to 152 kHz.

[0024] The beneficial effects of the present invention are as follows:

[0025] The method is simple and easy to operate, and can better adapt to the current mainstream AI servers, ChatGPT applications, and GPU applications; it meets the system 2+0, 3+0, 3+1 and other EDPP stress tests. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0027] Figure 1 is a schematic diagram of LLC circuit;

[0028] Figure 2 It is a schematic diagram of loop control;

[0029] Figure 3 Schematic diagram of load conditions. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present invention will be described clearly and completely below in combination with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0032] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0033] In the present invention, unless otherwise clearly specified and limited, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "fixation" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0035] The present invention provides a method for realizing EDPP function, comprising the following steps:

[0036] S1. Improve the output gain of the power supply circuit;

[0037] S2. Reduce the drop of input voltage of the power supply circuit;

[0038] S3, increase the output capacitance of the power supply circuit;

[0039] S4, increase the speed of the current sharing loop of the power supply circuit;

[0040] S5. Reduce the output ripple of the power supply circuit;

[0041] S6. The output overcurrent protection is designed around the EDDP condition and cannot trigger the protection action by mistake.

[0042] S7. Increase the ADC sampling interrupt frequency of the power supply circuit.

[0043] See also Figure 1 As shown, the power supply circuit includes an input terminal Vin, a positive end of the input terminal Vin is connected to the drain of the MOS tube Q1, a source of the MOS tube Q1 is connected to the drain of the MOS tube Q2 and one end of the capacitor Cr, the other end of the capacitor Cr is connected to one end of the inductor Ls, the other end of the inductor Ls is connected to one end of the inductor Lp and the pin 1 of the transformer T1, and a negative end of the input terminal Vin is connected to the source of the MOS tube Q2, the other end of the inductor Lp and the pin 2 of the transformer T1;

[0044] Pin 3 of the transformer T1 is connected to the positive end of the diode D1, the negative end of the diode D1 is connected to the negative end of the diode D2, one end of the capacitor Cout and one end of the output port, pin 4 of the transformer T1 is connected to pin 5 of the transformer T1, the other end of the capacitor Cout and the other end of the output port, and pin 6 of the transformer T1 is connected to the positive end of the diode D2.

[0045] The power supply circuit outputs Vo=12V, k=Lp / Ls, in the step S1, k is 10, in the step S2, the input terminal Vin is a bus capacitor, and the capacitance value of the bus capacitor is increased, in the step S3, the capacitance value of the capacitor Cout is increased, and in the step S4, the current sharing loop process is: the I-SHAER voltage and the Isense voltage are both filtered by software moving average, and then the difference is obtained to obtain the current error, when the current error passes through the error hysteresis comparator, the relevant PI loop operation is performed to obtain the output of the current sharing loop, and then processed by the limiter, and its output is superimposed on the compensation amount of the output voltage, in the step S5, the power frequency ripple is reduced by the software AC ripple suppression function, and the output ripple of the power supply circuit is within 80mv, the minimum protection point of the input terminal Vin is set to 310V, and in the step S7, the ADC sampling interrupt frequency is set to 152kHz.

[0046] Specifically, the adjustments are divided into two aspects: hardware and software.

[0047] hardware:

[0048] 1. The server power supply output Vo = 12V, LLC gain should be sufficient, k value should be about 10 to avoid saturation of heavy-load resonant inductor Ls. In the half-bridge LLC circuit, k = Lp / Ls, Lp is the main transformer inductance, Ls is the resonant inductance.

[0049] 2. The voltage drop of the input front-stage busbar should not be too deep. The busbar capacitor (Vin) should be based on the maximum capacitance and size that can be placed in the internal space of the existing product. The larger the busbar capacitor, the smaller the busbar capacitor voltage drop, the smaller the output Vo fluctuation, and the more stable it is.

[0050] 3. Use as many 12V output capacitors (Cout) as possible, based on the maximum capacitance and size that can fit into the product's internal space. The larger the Cout, the smaller the 12V output ripple and the longer the output support time.

[0051] software:

[0052] 1. The current balancing PI loop must be fast enough: active current balancing function > passive current balancing function (voltage droop method), and the current balancing loop must run fast. The filter coefficient is optimized to increase its dynamic current balancing capability. The current balancing loop control block diagram inside the PSU is as follows: Figure 2As shown, the I-SHAER voltage (8V for full load and 4V for half load) and the Isense voltage (output current*RS1*amplification factor) are both filtered by software moving average, and then the current error is obtained by difference. After the current error passes through the error hysteresis comparator, the relevant PI loop operation is performed to obtain the output of the current sharing loop. After passing through the limiter, its output will be superimposed on the compensation amount of the output voltage.

[0053] 2. The output ripple of the 12V product (Vo) is as small as possible. Because the output ripple of the product is mainly composed of switching ripple and power frequency ripple, we increase the output capacitance Cout of the product; at the same time, the power frequency ripple is reduced through the software AC ripple suppression function; the output ripple of the 12V product is reduced to less than 80mv to avoid the EDDP current shock and downtime caused by different input sources.

[0054] 3. Output overcurrent protection design needs to focus on Figure 3 The EDDP test conditions are set. During the process of 10A 10ms jumping to 500A 200us, the product CT protection and OCP protection cannot be triggered by mistake, and the product cannot shut down. The secondary ADC sampling frequency is changed from 80kHz to 84kHz to avoid the same frequency as the primary switching frequency, optimize the low-frequency current oscillation caused by the output ripple, and effectively reduce the peak current of a single product, with a 10% margin from the CT protection setting value. (EDPP test equipment: 1. AC source: Ainuo ANBGS060T; 2. DC Load: Chroma 63205A-600-350; 3. Oscilloscope: Tektronix MS058B).

[0055] 4. The PFC (bus voltage, Vin of LLC circuit) loop algorithm should be as fast and stable as possible.

[0056] 1) The bus voltage (Vin of LLC circuit) minimum protection point is changed from 340V to 310V. The bus voltage minimum protection point is the protection point set by the software. If the voltage is lower than this point during the operation of the product, the product will restart for protection. Normally, the lower this point is, the better. The product is not easy to protect.

[0057] 2) Optimize the Bulk voltage peak under EDPP load shedding, change the slow loop voltage loop to a fast loop, and change the judgment of the fast and slow loops to 20V.

[0058] The bulk step (bulk voltage increment) was changed from 0.2 to 1; the current limit (product over-power input current limit Iopp = Pout / Vinmin / PF / *1.414) was changed from 20A to 24A.

[0059] 5. The ADC sampling interrupt frequency is increased from 80kHz to 152kHz. As the sampling frequency increases, more data is collected per unit time, which is equivalent to faster loop operation. When the product performs output load shedding, the bus voltage can respond and recover better, making its fluctuation range smaller and the product output more stable.

[0060] Example

[0061] Figure 3 The power supply simulates the EDPP test conditions of the system end with a 12V output of 2000W. The peak current value can be reduced by moving average to avoid triggering OCP2. To better adapt to customer systems, the power supply output overcurrent protection point and protection time are improved. The secondary ADC sampling frequency is avoided to be the same frequency as the primary switching frequency, and the low-frequency current oscillation caused by the output ripple is optimized, especially in the case of heterogeneous input.

[0062] The filter coefficient of the maximum current balancing method is optimized to increase its dynamic current balancing capability:

[0063] 1) The filtering of the current-sharing bus voltage Ibus is appropriately slowed down, from 8 times*125us(1ms)->4096 times*25us(102.4ms).

[0064] 2) The output current and voltage Isense filtering is appropriately slowed down, 8 times * 125us (1ms) -> 4096 times * 25us (102.4ms).

[0065] Adjust the error hysteresis setting of the maximum current sharing loop

[0066] The system load is less than 15%, the error hysteresis is set to 0.003 (0.49A) before improvement, and the error hysteresis is set to 0.003 (0.49A) after improvement.

[0067] When the system load is greater than 15% and less than 50%, the error hysteresis is set to 0.010 (1.64A) before improvement and 0.010 (1.64A) after improvement.

[0068] When the system load is greater than 50%, the error hysteresis is set to 0.010 (1.64A) before improvement and 0.030 (4.92A) after improvement.

[0069] Cancel the voltage droop compensation strategy under dynamic load, adjust the voltage droop compensation range from + / -50mV to + / -75mV (12.275V at no load, 12.125V at full load), adjust the Pmbus filter window from 8*13ms=104ms to 32*13ms=416ms, and the sampling value used for filtering is the average value.

[0070] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the embodiments. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A method for implementing EDPP function, characterized in that: The following steps are involved: S1. Improve the output gain of the power supply circuit; S2. Reduce the drop of input voltage of the power supply circuit; S3, increase the output capacitance of the power supply circuit; S4, increase the speed of the current sharing loop of the power supply circuit; S5. Reduce the output ripple of the power supply circuit; S6. The output overcurrent protection is designed around the EDDP condition and cannot trigger the protection action by mistake. S7. Increase the ADC sampling interrupt frequency of the power supply circuit.

2. The method for realizing EDPP function according to claim 1, characterized in that: The power supply circuit includes an input terminal Vin, a positive end of the input terminal Vin is connected to the drain of the MOS tube Q1, a source of the MOS tube Q1 is connected to the drain of the MOS tube Q2 and one end of the capacitor Cr, the other end of the capacitor Cr is connected to one end of the inductor Ls, the other end of the inductor Ls is connected to one end of the inductor Lp and the pin 1 of the transformer T1, and a negative end of the input terminal Vin is connected to the source of the MOS tube Q2, the other end of the inductor Lp and the pin 2 of the transformer T1; Pin 3 of the transformer T1 is connected to the positive end of the diode D1, the negative end of the diode D1 is connected to the negative end of the diode D2, one end of the capacitor Cout and one end of the output port, pin 4 of the transformer T1 is connected to pin 5 of the transformer T1, the other end of the capacitor Cout and the other end of the output port, and pin 6 of the transformer T1 is connected to the positive end of the diode D2.

3. The method for realizing EDPP function according to claim 2, characterized in that: The power supply circuit outputs Vo=12V, k=Lp / Ls, and in step S1, k is 10.

4. The method for realizing EDPP function according to claim 2, characterized in that: In the step S2, the input terminal Vin is a bus capacitor, and the capacitance value of the bus capacitor is increased.

5. The method for realizing EDPP function according to claim 2, characterized in that: In step S3, the capacitance value of capacitor Cout is increased.

6. The method for realizing EDPP function according to claim 1, characterized in that: In step S4, the current sharing loop process is as follows: the I-SHAER voltage and the Isense voltage are both filtered by software moving average, and then the difference is taken to obtain the current error. After the current error passes through the error hysteresis comparator, the relevant PI loop operation is performed to obtain the output of the current sharing loop, which is then processed by the limiter and its output is superimposed on the compensation amount of the output voltage.

7. The method for realizing EDPP function according to claim 1, characterized in that: In step S5, the AC ripple suppression function of the software is used to reduce the power frequency ripple, and the output ripple of the power supply circuit is reduced to within 80mv.

8. The method for realizing EDPP function according to claim 2, characterized in that: The lowest protection point of the input terminal Vin is set to 310V.

9. The method for realizing EDPP function according to claim 1, characterized in that: In step S7, the ADC sampling interrupt frequency is set to 152 kHz.

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