Self-adaptive interrupt aggregation implementation method and device for solid state disk and computer equipment
Through the adaptive interrupt aggregation method, the interrupt aggregation strategy of solid-state drives is adjusted to adapt to different load scenarios, improving the concurrency and performance of the command processing of solid-state drives, and solving the problem of low host command concurrency and high load in high pressure scenarios.
Patent Information
- Application Number
- CN202411300666.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2024-12-31
AI Technical Summary
During the interaction between the solid-state drive and the host, the host's command concurrency is not high, resulting in frequent interruptions, increasing the host's load and affecting performance, especially in high-pressure scenarios.
Through the adaptive interrupt aggregation method, the system powers on to configure the interrupt aggregation timeout time and number of commands, periodically counts the number and time of recent interrupt commands, adjusts the timeout time and number of commands according to the comparison results, realizes intelligent interrupt aggregation and adapts to different load conditions.
It improves the concurrency and performance of the command processing of the solid-state drive side, meets the needs of low latency and high QD scenarios in low QD scenarios, and avoids frequent interruptions and interference with host command issuance.
Smart Images
Figure CN119225649A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a method, device, computer equipment and storage medium for implementing adaptive interrupt aggregation of solid state hard disks. Background Art
[0002] SSD (Solid State Drive) has been widely used in various occasions. At present, it has gradually replaced the traditional HDD in the PC market, providing users with a better experience in terms of reliability and performance. In the process of interaction between the host and SSD, the corresponding protocol specifications need to be followed so that commands and data can be exchanged correctly. The host first submits the command to the disk end, and then the SSD obtains the command for execution and data transmission. After the data transmission is completed, the command completion information is replied to the host. This process includes writing the command completion message to the host and triggering an interrupt. After receiving the interrupt, the host will obtain the command completion information and return the data and command completion status to the upper application.
[0003] In some scenarios, the host has a low concurrency in issuing commands and processing command completion information, which means that when it receives a command completion interrupt, it needs to process the command completion event before it can issue a new command to the disk. This results in a limited number of commands that the SSD can receive and process, and low concurrency, which in turn leads to performance degradation. Furthermore, in high-stress scenarios, if each command completion triggers an interrupt, the host load will be increased, resulting in the inability to fully utilize the performance. Therefore, how to dynamically adjust the command completion interrupt according to different host workload behaviors is one of the key design factors for optimizing host + disk performance. Summary of the invention
[0004] Based on this, it is necessary to provide a method, device, computer equipment and storage medium for implementing adaptive interrupt aggregation of solid-state drives in response to the above technical problems.
[0005] A method for implementing adaptive interrupt aggregation of a solid state drive, the method comprising:
[0006] Power on the system and configure interrupt aggregation, set the interrupt aggregation timeout and the number of interrupt aggregation commands;
[0007] When processing host commands, periodically count the number of commands aggregated when interrupts are sent in the recent period and the corresponding time when the interrupt occurs;
[0008] The number of commands aggregated when sending interrupts is compared with the set number of interrupt aggregation commands, and the time corresponding to the occurrence of the interrupt is compared with the set interrupt aggregation timeout time;
[0009] The corresponding interrupt aggregation timeout and the number of interrupt aggregation commands are adjusted according to the comparison result to ensure that the number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest.
[0010] In one embodiment, the step of comparing the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and comparing the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time includes:
[0011] Determine whether the time corresponding to the interruption occurrence is greater than or equal to the interruption aggregation timeout;
[0012] If yes, increase the number of interrupt aggregation commands and exit the current interrupt aggregation self-regulation process;
[0013] If not, determine whether the number of commands aggregated when sending interrupts recently is less than the number of interrupt aggregation commands;
[0014] If yes, reduce the interrupt aggregation timeout, if no, increase the interrupt aggregation timeout.
[0015] In one embodiment, the step of increasing the interrupt aggregation timeout period if otherwise further includes:
[0016] The number of commands aggregated when interrupts are sent in the recent period and the time corresponding to the interruption occurrence are counted again, and it is determined whether the number of commands aggregated when interrupts are sent recently is less than the number of interruption aggregation commands;
[0017] If yes, reduce the interrupt aggregation timeout and the number of interrupt aggregation commands;
[0018] Otherwise, exit the current interrupt aggregation self-regulation process.
[0019] In one of the embodiments, the interrupt aggregation configuration further includes setting an interval duration of autonomous adjustment of the interrupt aggregation, and the method further includes:
[0020] Monitor whether the time from the last interruption aggregation self-adjustment exceeds the set interruption aggregation self-adjustment interval;
[0021] If it has not been exceeded, the host command will continue to be processed; if it has been exceeded, interrupt aggregation autonomous adjustment will be initiated.
[0022] A device for implementing adaptive interrupt aggregation of a solid state drive, the device comprising:
[0023] A configuration module, which is used to power on the system and perform interrupt aggregation configuration, and set the interrupt aggregation timeout time and the number of interrupt aggregation commands;
[0024] A statistics module, which is used to periodically count the number of commands aggregated when interrupts are sent in a recent period of time and the time corresponding to the occurrence of the interrupts when processing host commands;
[0025] A comparison module, the comparison module is used to compare the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and to compare the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time;
[0026] An adjustment module is used to adjust the corresponding interrupt aggregation timeout and the number of interrupt aggregation commands according to the comparison results to meet the actual statistical number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest.
[0027] In one embodiment, the comparison module is further used for:
[0028] Determine whether the time corresponding to the interruption occurrence is greater than or equal to the interruption aggregation timeout;
[0029] If yes, increase the number of interrupt aggregation commands and exit the current interrupt aggregation self-regulation process;
[0030] If not, determine whether the number of commands aggregated when sending interrupts recently is less than the number of interrupt aggregation commands;
[0031] If yes, reduce the interrupt aggregation timeout, if no, increase the interrupt aggregation timeout.
[0032] In one embodiment, the comparison module is further used for:
[0033] The number of commands aggregated when interrupts are sent in the recent period and the time corresponding to the interruption are counted again, and it is determined whether the number of commands aggregated when interrupts are sent recently is less than the number of interruption aggregated commands;
[0034] If yes, reduce the interrupt aggregation timeout and the number of interrupt aggregation commands;
[0035] Otherwise, exit the current interrupt aggregation self-regulation process.
[0036] In one of the embodiments, the interrupt aggregation configuration further includes setting an interval duration of autonomous adjustment of the interrupt aggregation, and the device further includes a monitoring module, wherein the monitoring module is used to:
[0037] Monitor whether the time from the last interruption aggregation self-adjustment exceeds the set interruption aggregation self-adjustment interval;
[0038] If it has not been exceeded, the host command will continue to be processed; if it has been exceeded, interrupt aggregation autonomous adjustment will be initiated.
[0039] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any one of the above methods when executing the computer program.
[0040] A computer-readable storage medium stores a computer program, wherein the computer program implements the steps of any one of the above methods when executed by a processor.
[0041] The above-mentioned adaptive interrupt aggregation implementation method, device, computer equipment and storage medium of the solid-state hard disk are as follows: by powering on the system and performing interrupt aggregation configuration, the interrupt aggregation timeout time and the number of interrupt aggregation commands are set; when processing host commands, the number of commands aggregated when sending interrupts and the corresponding time when the interrupt occurs in a recent period of time are periodically counted; the number of commands aggregated when sending interrupts is compared with the set number of interrupt aggregation commands, and the corresponding time when the interrupt occurs is compared with the set interrupt aggregation timeout time; the corresponding interrupt aggregation timeout time and the number of interrupt aggregation commands are adjusted according to the comparison result to meet the actual number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout time is the shortest. The present invention introduces an intelligent interrupt aggregation scheme, which can perform autonomous interrupt aggregation according to different load conditions of the host, so as to meet the requirements of notifying the host immediately after the command is completed in a low QD scenario, and notifying the host only after completing multiple commands in a high QD scenario, so as not to interrupt the command issuance of the host, thereby improving the concurrency and performance of command processing on the SSD side. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 This is a schematic diagram of the traditional SSD command processing flow;
[0043] Figure 2 Schematic diagram of time distribution in traditional SSD processing flow;
[0044] Figure 3 It is a flowchart of a method for implementing adaptive interrupt aggregation of a solid state drive in one embodiment;
[0045] Figure 4 is a schematic diagram of host command interruption behavior in different QD scenarios in one embodiment;
[0046] Figure 5 It is a flowchart of a method for implementing adaptive interrupt aggregation of a solid state drive in another embodiment;
[0047] Figure 6 It is a structural block diagram of a device for implementing adaptive interrupt aggregation of a solid state drive in one embodiment;
[0048] Figure 7It is a structural block diagram of a device for implementing adaptive interrupt aggregation of a solid state drive in another embodiment;
[0049] Figure 8 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION
[0050] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0051] Currently, if Figure 1 The figure shows a schematic diagram of the traditional SSD command processing flow, and the specific steps are as follows:
[0052] 1.1, S0: The host sends command 1;
[0053] 1.2, S1: SSD obtains command 1;
[0054] 1.3, S2: SSD processing command 1;
[0055] 1.4, S3: The SSD writes the command completion information to the host memory (CQ). At this time, the host does not know that command 1 has been completed;
[0056] 1.5, S4: SSD triggers an interrupt to notify the host that a command has been completed (only then does the host know that a command has been completed);
[0057] 1.6, S5: The host originally intended to send command 2 (but it could not actually initiate it because a command had been received and completed, which needed to be processed first);
[0058] 1.7, S5: Host processing command 1 complete event;
[0059] 1.8, S6: The host sends command 2.
[0060] During this process, the host originally intended to send command 2 at 1.6, but because the interruption from the disk in 1.5 indicated that a command had been completed, the completed command information was processed first, resulting in a delay in sending command 2. This caused the disk end to be in an idle waiting state.
[0061] like Figure 2 The figure below is a schematic diagram of the time distribution in the traditional SSD processing flow. It can be seen that after each command is completed, the host needs to process the completed command before issuing a new command. During the processing of the completed command, the SSD end is in an invalid waiting state. As a result, the command interaction between the host and the disk degenerates to QD 1 (the disk end always processes the host's commands serially).
[0062] In actual application scenarios, the host is expected to send multiple commands, such as QD 32. The host sends new commands at a certain interval, such as 2us, but the CQ interrupt replied by the disk interrupts the host's sending of new commands (typically delayed by 10+us under Windows). Therefore, in high QD scenarios, the disk can only see one command from the host. In SSD application scenarios, the larger the QD, the higher the concurrent processing capability of the disk, and thus the higher the performance. The existing SSD interrupt reporting strategy makes it impossible to optimize the sending of host commands, that is, the QD is suppressed to a very low level (for example, 1).
[0063] Based on this, the present invention provides a method for implementing adaptive interrupt aggregation of a solid-state drive, aiming to simultaneously meet the high concurrency performance of the SSD in both low QD scenarios and high QD scenarios.
[0064] In one embodiment, Figure 3 As shown, a method for implementing adaptive interrupt aggregation of a solid state drive is provided, the method comprising:
[0065] Step 302, the system is powered on and interrupt aggregation configuration is performed, and the interrupt aggregation timeout and the number of interrupt aggregation commands are set;
[0066] Step 304, when processing host commands, periodically counting the number of commands aggregated when interrupts are sent in a recent period of time and the time corresponding to when the interrupts occur;
[0067] Step 306, comparing the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and comparing the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time;
[0068] Step 308 , adjusting the corresponding interrupt aggregation timeout and the number of interrupt aggregation commands according to the comparison result, so as to ensure that the number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest.
[0069] In this embodiment, a method for implementing adaptive interrupt aggregation of a solid-state drive is provided, which dynamically adjusts interrupt aggregation parameters for different host access scenarios to meet the performance requirements of low latency / high concurrency. When processing host commands, the interrupt aggregation timeout (Aggregation Time) and the number of interrupt aggregation commands (AggregationThreshold) are set. When periodic statistical interrupts are triggered, the number of commands that can be aggregated is compared with the set number of interrupt aggregation commands, and the interrupt sending time is compared with the set interrupt aggregation timeout. The corresponding threshold is adjusted according to the result until the optimal setting is found, that is, the number of aggregation commands actually counted is greater than or equal to the set number of interrupt aggregation commands, and the interrupt aggregation timeout is the shortest. SSD can dynamically identify the optimal interrupt aggregation method, maximize the host command concurrent processing capability at high QD (Queue Depth, the number of commands issued by the host at the same time), minimize command latency at low QD, and improve performance.
[0070] In one embodiment, the interrupt aggregation configuration also includes setting an interval duration for autonomous adjustment of interrupt aggregation, and the method also includes: monitoring whether the time from the last autonomous adjustment of interrupt aggregation exceeds the set interval duration for autonomous adjustment of interrupt aggregation; if it does not exceed, continuing to process the host command, and if it has exceeded, starting the autonomous adjustment of interrupt aggregation.
[0071] Specifically, the interrupt aggregation configuration includes the following fields:
[0072] -Aggregation Time: Interrupt aggregation waiting timeout;
[0073] -Aggregation Threshold: The maximum number of commands to be aggregated (for example, if it is set to 5, an interrupt is triggered when 5 commands are completed cumulatively);
[0074] -Adaptive_Adjust_Time, the period of interrupt aggregation monitoring startup.
[0075] Interrupt aggregation monitoring is used to trigger autonomous interrupt aggregation detection and adjustment according to a preset period (Adaptive_Adjust_Time, such as 100ms). Interrupt aggregation statistics are used to collect statistics on host interrupts triggered in the recent period, including:
[0076] The number of commands aggregated when sending interrupts (denoted as Avg_Aggregated_Command);
[0077] The time corresponding to when the interrupt occurs (Avg_Aggregated_TO).
[0078] First, the host command is received and parsed, and then handed over to the internal module to perform read and write operations. Then, read and write operations are performed according to the command type. After the command processing is completed, the relevant command completion information is written to the host memory (CQ).
[0079] Command completion interrupt aggregation: Controls the sending of command completion interrupts. According to the set value, the interrupt is triggered to notify the host only when the timeout (Aggregation Time) or the cumulative number of completed commands reaches the threshold (Aggregation Threshold), so that the host can process command completion events in batches and avoid frequent interruptions to the host to send new commands.
[0080] like Figure 4 As shown, it is a schematic diagram of the host command interruption behavior in different QD scenarios in this embodiment:
[0081] In the low QD scenario (taking QD 1 as an example), the host only issues one command at a time, and the next command needs to be issued after the current command is completed. In this scenario, it is necessary to ensure that the host is notified of the interrupt in time after the command is completed, because even if the disk waits longer, no host command will be issued, which will affect the delay of the completed command. Therefore, in this scenario, the response delay requirements of low QD command processing are met through the disk-side autonomous interrupt aggregation adjustment and non-interrupt aggregation.
[0082] High QD scenario (taking QD 2 as an example), that is, the host sends two commands each time, and only sends the next batch of two commands after these two commands are completed. In this scenario, in order to maximize the concurrent processing of the disk side, the best implementation is to receive two commands from the disk side at a time for concurrent processing, and interrupt the host batch processing command completion event only after both are completed. Compared with the implementation of traditional SSDs, an idle waiting window will appear on the disk side for every two commands, while for traditional SSDs, a waiting window will appear on the disk side for each command (refer to QD 1). In this embodiment, through the autonomous interrupt aggregation adjustment on the disk side, the interrupt aggregation is set to 2, and the command completion information is immediately written to the host memory (CQ) after each command is completed, but the host does not know that a command has been completed at this time; when two commands are completed cumulatively, or a timeout occurs, an interrupt is triggered to notify the host that the command is completed.
[0083] It can be seen that through the autonomous interrupt aggregation identification and adjustment on the disk side, the interrupt aggregation behavior in different QD scenarios can be met, which not only meets the low latency in low QD scenarios (triggering interrupts immediately), but also meets the concurrent processing in high QD scenarios (triggering interrupts after a certain number of aggregations).
[0084] In the above embodiment, the interrupt aggregation timeout and the number of interrupt aggregation commands are set by powering on the system and configuring interrupt aggregation; when processing host commands, the number of commands aggregated when sending interrupts and the corresponding time when the interrupt occurs in a recent period of time are periodically counted; the number of commands aggregated when sending interrupts that are counted is compared with the set number of interrupt aggregation commands, and the corresponding time when the interrupt occurs is compared with the set interrupt aggregation timeout; the corresponding interrupt aggregation timeout and the number of interrupt aggregation commands are adjusted according to the comparison results to meet the requirement that the number of commands aggregated when sending interrupts that are actually counted is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest. The present invention introduces an intelligent interrupt aggregation scheme, which can perform autonomous interrupt aggregation according to different load conditions of the host, so as to meet the requirement of notifying the host immediately after the command is completed in a low QD scenario, and to meet the requirement of notifying the host only after completing multiple commands in a high QD scenario, so as not to interrupt the command issuance of the host, thereby improving the concurrency and performance of command processing on the SSD side.
[0085] In one embodiment, a method for implementing adaptive interrupt aggregation of a solid state drive is provided. The method comprises the steps of comparing the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and comparing the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time, including:
[0086] Determine whether the time corresponding to the interruption occurrence is greater than or equal to the interruption aggregation timeout;
[0087] If yes, increase the number of interrupt aggregation commands and exit the current interrupt aggregation self-regulation process;
[0088] If not, determine whether the number of commands aggregated when sending interrupts recently is less than the number of interrupt aggregation commands;
[0089] If yes, reduce the interrupt aggregation timeout, if no, increase the interrupt aggregation timeout;
[0090] The number of commands aggregated when interrupts are sent in the recent period and the time corresponding to the interruption are counted again, and it is determined whether the number of commands aggregated when interrupts are sent recently is less than the number of interruption aggregated commands;
[0091] If yes, reduce the interrupt aggregation timeout and the number of interrupt aggregation commands;
[0092] Otherwise, exit the current interrupt aggregation self-regulation process.
[0093] Specifically, please refer to Figure 5 The flowchart of the method for implementing the adaptive interrupt aggregation of the solid state drive shown in FIG. 1 is as follows:
[0094] Step 5.1: Power on the system.
[0095] Step 5.2, initialize interrupt aggregation configuration:
[0096] -Aggregation Time: 0, do not wait for aggregation;
[0097] -Aggregation Threshold: 1, no aggregation;
[0098] -Adaptive_Adjust_Time: N milliseconds (for example, 100 milliseconds), interrupt aggregation is autonomously adjusted at fixed intervals.
[0099] Step 5.3: Process host commands.
[0100] Step 5.4: The interrupt aggregation statistics module counts the average number of commands completed corresponding to each interrupt and the interrupt timeout time.
[0101] Step 5.5, the interrupt aggregation monitoring module monitors whether the time from the last interrupt aggregation autonomous adjustment exceeds Adptive_Adjut_Time.
[0102] Step 5.6: Check whether Adptive_Adjut_Time is exceeded; if not, go to step 5.3; if yes, go to step 5.7.
[0103] Step 5.7: Interrupt aggregation monitoring starts the interrupt aggregation self-regulation process.
[0104] Step 5.8: Process host commands.
[0105] Step 5.9: The interrupt aggregation statistics module averages the information sent each time an interrupt is triggered.
[0106] Step 5.10: Query the interrupt aggregation statistics module to obtain the number of commands aggregated when sending interrupts recently (Avg_Aggregated_Command) and the time when the interrupt occurs (Avg_Aggregated_TO).
[0107] Step 5.11: Is Avg_Aggregated_TO greater than or equal to Aggregation Time? If not, proceed to step 5.12; if yes, jump to step 5.13.
[0108] Step 5.12: Increase Aggregation Threshold by one step (for example, add 1), and jump to step 5.19.
[0109] Step 5.13: Is Avg_Aggregated_Command less than Aggregation Threshold? If so, proceed to step 5.14; if not, jump to step 5.15.
[0110] Step 5.14: Reduce the Aggregation Time by one step (for example, add 10ms), and then go to step 5.19.
[0111] Step 5.15: Increase the Aggregation Time by one step (for example, 10 ms).
[0112] Step 5.16, query the interruption aggregation statistics module, the number of commands aggregated when sending interruptions recently (Avg_Aggregated_Command) and the corresponding time when the interruption occurs (Avg_Aggregated_TO).
[0113] Step 5.17: Is Avg_Aggregated_Command less than Aggregation Threshold? If so, proceed to step 5.18; if not, jump to step 5.19.
[0114] Step 5.18: Reduce Aggregation Time by two steps (for example, add 20 ms); reduce Aggregation Threshold by one step (for example, subtract 1).
[0115] Step 5.19: Exit the current interrupt aggregation self-regulation process and jump to step 5.3.
[0116] In this embodiment, autonomous interrupt aggregation identification and adjustment on the disk side can meet the interrupt aggregation behavior in different QD scenarios, which not only meets the low latency in low QD scenarios, but also meets the concurrent processing in high QD scenarios, effectively improving the concurrency and performance of command processing on the SSD side.
[0117] It should be understood that although Figure 1-Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1-Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.
[0118] In one embodiment, Figure 6 As shown, a device 600 for implementing adaptive interrupt aggregation of a solid state drive is provided, and the device includes:
[0119] Configuration module 601, which is used to power on the system and perform interrupt aggregation configuration, and set the interrupt aggregation timeout time and the number of interrupt aggregation commands;
[0120] A statistics module 602, which is used to periodically count the number of commands aggregated when interrupts are sent in a recent period of time and the time corresponding to when the interrupts occur when processing host commands;
[0121] A comparison module 603, which is used to compare the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and to compare the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time;
[0122] The adjustment module 604 is used to adjust the corresponding interrupt aggregation timeout and the number of interrupt aggregation commands according to the comparison result to meet the actual statistical number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest.
[0123] In one embodiment, the comparison module 603 is further used to:
[0124] Determine whether the time corresponding to the interruption occurrence is greater than or equal to the interruption aggregation timeout;
[0125] If yes, increase the number of interrupt aggregation commands and exit the current interrupt aggregation self-regulation process;
[0126] If not, determine whether the number of commands aggregated when sending interrupts recently is less than the number of interrupt aggregation commands;
[0127] If yes, reduce the interrupt aggregation timeout, if no, increase the interrupt aggregation timeout.
[0128] In one embodiment, the comparison module 603 is further used to:
[0129] The number of commands aggregated when interrupts are sent in the recent period and the time corresponding to the interruption are counted again, and it is determined whether the number of commands aggregated when interrupts are sent recently is less than the number of interruption aggregated commands;
[0130] If yes, reduce the interrupt aggregation timeout and the number of interrupt aggregation commands;
[0131] Otherwise, exit the current interrupt aggregation self-regulation process.
[0132] In one embodiment, Figure 7As shown, a device 600 for implementing adaptive interrupt aggregation of a solid state drive is provided. The interrupt aggregation configuration of the device further includes setting an interval duration of autonomous adjustment of the interrupt aggregation. The device also includes a monitoring module 605 for:
[0133] Monitor whether the time from the last interruption aggregation self-adjustment exceeds the set interruption aggregation self-adjustment interval;
[0134] If it has not been exceeded, the host command will continue to be processed; if it has been exceeded, interrupt aggregation autonomous adjustment will be initiated.
[0135] The specific limitations on the device for implementing adaptive interrupt aggregation of a solid-state drive can be found in the above-mentioned limitations on the method for implementing adaptive interrupt aggregation of a solid-state drive, which will not be repeated here.
[0136] In one embodiment, a computer device is provided, whose internal structure diagram can be as follows: Figure 8 As shown. The computer device includes a processor, a memory and a network interface connected through a device bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating device, a computer program and a database. The internal memory provides an environment for the operation of the operating device and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for implementing adaptive interrupt aggregation of a solid-state hard disk is implemented.
[0137] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.
[0138] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps in the above method embodiments when executing the computer program.
[0139] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.
[0140] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
[0141] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0142] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A method for implementing adaptive interrupt aggregation of a solid state drive, the method comprising: Power on the system and configure interrupt aggregation, set the interrupt aggregation timeout and the number of interrupt aggregation commands; When processing host commands, periodically count the number of commands aggregated when interrupts are sent in the recent period and the corresponding time when the interrupt occurs; Compare the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and compare the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time; The corresponding interrupt aggregation timeout and the number of interrupt aggregation commands are adjusted according to the comparison result to ensure that the number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest.
2. The method for implementing adaptive interrupt aggregation of a solid state drive according to claim 1, characterized in that: The steps of comparing the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and comparing the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time include: Determine whether the time corresponding to the interruption occurrence is greater than or equal to the interruption aggregation timeout; If yes, increase the number of interrupt aggregation commands and exit the current interrupt aggregation self-regulation process; If not, determine whether the number of commands aggregated when sending interrupts recently is less than the number of interrupt aggregation commands; If yes, reduce the interrupt aggregation timeout, if no, increase the interrupt aggregation timeout.
3. The method for implementing adaptive interrupt aggregation of a solid state drive according to claim 2, characterized in that: After the step of increasing the interrupt aggregation timeout period, the following steps are further included: The number of commands aggregated when interrupts are sent in the recent period and the time corresponding to the interruption occurrence are counted again, and it is determined whether the number of commands aggregated when interrupts are sent recently is less than the number of interruption aggregation commands; If yes, reduce the interrupt aggregation timeout and the number of interrupt aggregation commands; Otherwise, exit the current interrupt aggregation self-regulation process.
4. The method for implementing adaptive interrupt aggregation of a solid state drive according to any one of claims 1 to 3, characterized in that: The interrupt aggregation configuration further includes setting an interval duration of autonomous adjustment of interrupt aggregation, and the method further includes: Monitor whether the time from the last interruption aggregation self-adjustment exceeds the set interruption aggregation self-adjustment interval; If it has not been exceeded, the host command will continue to be processed; if it has been exceeded, interrupt aggregation autonomous adjustment will be initiated.
5. A device for implementing adaptive interrupt aggregation of a solid state drive, characterized in that: The device comprises: A configuration module, which is used to power on the system and perform interrupt aggregation configuration, and set the interrupt aggregation timeout time and the number of interrupt aggregation commands; A statistics module, which is used to periodically count the number of commands aggregated when interrupts are sent in a recent period of time and the time corresponding to when the interrupts occur when processing host commands; A comparison module, the comparison module is used to compare the number of commands aggregated when sending interrupts with the set number of interrupt aggregation commands, and to compare the time corresponding to the occurrence of the interrupt with the set interrupt aggregation timeout time; An adjustment module is used to adjust the corresponding interrupt aggregation timeout and the number of interrupt aggregation commands according to the comparison results to meet the actual statistical number of commands aggregated when sending interrupts is greater than or equal to the number of interrupt aggregation commands and the interrupt aggregation timeout is the shortest.
6. The device for implementing adaptive interrupt aggregation of a solid state drive according to claim 5, characterized in that: The comparison module is also used for: Determine whether the time corresponding to the interruption occurrence is greater than or equal to the interruption aggregation timeout; If yes, increase the number of interrupt aggregation commands and exit the current interrupt aggregation self-regulation process; If not, determine whether the number of commands aggregated when sending interrupts recently is less than the number of interrupt aggregation commands; If yes, reduce the interrupt aggregation timeout, if no, increase the interrupt aggregation timeout.
7. The device for implementing adaptive interrupt aggregation of a solid state drive according to claim 6, characterized in that: The comparison module is also used for: The number of commands aggregated when interrupts are sent in the recent period and the time corresponding to the interruption occurrence are counted again, and it is determined whether the number of commands aggregated when interrupts are sent recently is less than the number of interruption aggregation commands; If yes, reduce the interrupt aggregation timeout and the number of interrupt aggregation commands; Otherwise, exit the current interrupt aggregation self-regulation process.
8. The device for implementing adaptive interrupt aggregation of a solid state drive according to any one of claims 5 to 7, characterized in that: The interrupt aggregation configuration further includes setting an interval duration of autonomous adjustment of interrupt aggregation, and the device further includes a monitoring module, wherein the monitoring module is used to: Monitor whether the time from the last interruption aggregation self-adjustment exceeds the set interruption aggregation self-adjustment interval; If it has not been exceeded, the host command will continue to be processed; if it has been exceeded, interrupt aggregation autonomous adjustment will be initiated.
9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.