Register overflow optimization method and device, storage medium and program product

Abstract

The embodiment of the invention provides a register overflow optimization method and device, a storage medium and a program product, and relates to the technical field of chips, and the method comprises the step of performing register allocation on a target thread for executing an operator in an operator compiling process. And if the register overflows in the process of executing the register allocation, writing the overflowed virtual register to a target stack space corresponding to the target thread in the on-chip cache. According to the method and the device, the corresponding target stack space is set for the target thread in the on-chip cache, and the access speed of the on-chip cache is higher compared with the access speed of a video memory, so that when register overflow occurs in register allocation for the target thread, the access speed of the on-chip cache is improved. According to the method, the overflowed virtual register is written into the target stack space corresponding to the target thread in the on-chip cache, so that the access speed to the stack space is higher, the delay caused by register overflow is reduced, and the operator performance is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular to a register overflow optimization method, device, storage medium, and program product. Background Art

[0002] Artificial intelligence models usually refer to neural network models that are trained to perform inference and prediction, such as image inference models, speech inference models, etc. The operations of artificial intelligence models can be implemented by operators in the computation graph. Operators refer to various operations performed on tensors at each layer in the artificial intelligence model. For example, the convolution operation performed by the convolution layer of the artificial intelligence model on the input data of the artificial intelligence model is the convolution operator.

[0003] When registers are allocated to operators, register overflow often occurs. When register overflow occurs, the overflowed virtual registers are written out to the video memory. Since the video memory is a lower-level memory in the artificial intelligence chip, the access speed of this memory is relatively slow. Therefore, the speed of writing the overflowed virtual registers to the video memory is relatively slow, resulting in a decrease in operator performance. Summary of the invention

[0004] The embodiments of the present application provide a register overflow optimization method, device, storage medium and program product for reducing the delay caused by register overflow and thereby improving operator performance.

[0005] On the one hand, an embodiment of the present application provides a register overflow optimization method, including:

[0006] During operator compilation, register allocation is performed on a target thread that executes the operator;

[0007] If register overflow occurs during the register allocation process, the overflowed virtual register is written out to the target stack space corresponding to the target thread in the on-chip cache.

[0008] On the one hand, an embodiment of the present application provides a register overflow optimization device, including:

[0009] A register allocation module, used to allocate registers to a target thread executing the operator during operator compilation;

[0010] The writing module is used for writing the overflowed virtual register to the target stack space corresponding to the target thread in the on-chip cache if register overflow occurs during the execution of the register allocation.

[0011] Optionally, a reading module is also included;

[0012] The reading module is specifically used for:

[0013] During execution of the operator, the overflowed virtual register is read from the target stack space.

[0014] Optionally, the multiple physical registers associated with the target thread include: a stack pointer register for pointing to the target stack space;

[0015] The writing module is specifically used for:

[0016] If register overflow occurs during the execution of the register allocation, the overflowed virtual register is written out to the target stack space pointed to by the stack pointer register.

[0017] Optionally, the multiple physical registers associated with the target thread include: a stack pointer register for pointing to a starting address of the target stack space;

[0018] The writing module is specifically used for:

[0019] If register overflow occurs during the execution of the register allocation, the overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

[0020] Optionally, the writing module is specifically used for:

[0021] If a register overflow occurs during the register allocation process, and the register overflow occurs for the first time, obtaining a starting address of the target stack space, and storing the starting address of the target stack space in the stack pointer register;

[0022] The overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

[0023] Optionally, the target thread is any thread in a thread group, and each thread in the thread group corresponds to a stack space in an on-chip cache;

[0024] The writing module is specifically used for:

[0025] The starting address of the target stack space is determined based on the initial address of the on-chip cache, the number of the target thread in the thread group, and the size of the stack space allocated to each thread.

[0026] Optionally, the writing module is specifically used for:

[0027] If register overflow occurs during the register allocation process and the storage space of the on-chip cache meets the register overflow requirement, the overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

[0028] Optionally, the writing module is further used for:

[0029] If register overflow occurs during the register allocation process, and the storage space of the on-chip cache does not meet the register overflow requirement, the overflowed virtual register is written out to the video memory.

[0030] On the one hand, an embodiment of the present application provides a computer device, including a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, wherein the artificial intelligence chip implements the steps of the above-mentioned register overflow optimization method when executing the computer program.

[0031] On the one hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program executable by a computer device. When the computer program runs on the computer device, the computer device executes the steps of the above-mentioned register overflow optimization method.

[0032] On the one hand, an embodiment of the present application provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer device, the computer device executes the steps of the above-mentioned data access method.

[0033] In an embodiment of the present application, a corresponding target stack space is set for the target thread in the on-chip cache. Compared with the access speed of the video memory, the access speed of the on-chip cache is faster. Therefore, when a register overflow occurs in the register allocation for the target thread, the overflowed virtual register is written to the target stack space corresponding to the target thread in the on-chip cache. In this way, the access speed to the stack space is faster, thereby reducing the delay caused by the register overflow, and further improving the operator performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0035] Figure 1 A schematic diagram of the structure of an artificial intelligence chip provided in an embodiment of the present application;

[0036] Figure 2 A flow chart of a register overflow optimization method provided in an embodiment of the present application Figure 1 ;

[0037] Figure 3 A schematic diagram of a stack pointer register provided in an embodiment of the present application;

[0038] Figure 4 A flow chart of a register overflow optimization method provided in an embodiment of the present application Figure 2 ;

[0039] Figure 5 A schematic diagram of the structure of a register overflow optimization device provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] refer to Figure 1 , which is a structural diagram of an artificial intelligence chip applicable to an embodiment of the present application, the artificial intelligence chip 100 at least includes: a video memory 101, a plurality of programmable multiprocessors 102, wherein the programmable multiprocessor 102 can be a streaming processing cluster (SPC for short).

[0043] Each programmable multiprocessor 102 includes: a plurality of computing units 104. Each computing unit 104 includes: an on-chip cache 103 and a plurality of execution units 105. The plurality of execution units 105 inside the computing unit 104 share the on-chip cache 103.

[0044] Each execution unit 105 includes: physical registers 106 of each of the multiple threads in the thread group. The multiple threads can be executed concurrently, and each thread corresponds to one or more physical registers 106 .

[0045] The video memory 101 may be a high bandwidth memory (HBM) or other types of memory. The on-chip cache 103 is a temporary memory, which has a smaller capacity than the video memory 101, but a faster data exchange speed than the video memory 101. The on-chip cache 103 may be a group-shared memory (GSM), a general matrix main buffer (GMB), or the like.

[0046] In addition to the above-mentioned structure, the artificial intelligence chip 100 in the present application may also include other structures, which are not specifically limited in the present application.

[0047] The artificial intelligence chip 100 may be: a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a domain specific architecture (DSA), etc.

[0048] In practical applications, register allocation is a fundamental problem of compiler technology and plays a vital role in the performance of compiled code. When registers are allocated to operators, register overflow often occurs. When register overflow occurs, the overflowed virtual registers are written to the video memory. Since the video memory is a lower-level memory in the artificial intelligence chip, the access speed of this memory is relatively slow. Therefore, the speed of writing the overflowed virtual registers to the video memory is relatively slow. In this way, even if the number of register overflows is not large, the additional overhead of accessing the video memory caused by the register overflow will cause a decrease in program performance, thereby causing a decrease in operator performance.

[0049] In view of this, this application is based on Figure 1 The architecture diagram of the artificial intelligence chip shown in FIG. 1 provides a flow chart of a register overflow optimization method, such as Figure 2 As shown, the process of the method is executed by an artificial intelligence chip and includes the following steps:

[0050] Step 201: During the operator compilation process, registers are allocated to the target thread that executes the operator.

[0051] Specifically, in an artificial intelligence chip, a preset number of physical registers are allocated to multiple threads respectively, and the number of physical registers allocated to each thread is associated with the specific hardware properties of the artificial intelligence chip.

[0052] In the present application, the target thread may be any one of the above-mentioned multiple threads, and therefore, the artificial intelligence chip includes a preset number of physical registers pre-allocated to the target thread.

[0053] During operator compilation, the kernel function of the operator is converted from the intermediate representation in the form of a syntax tree to the intermediate representation in the form of a three-address. For the intermediate representation in the form of a syntax tree, the dependencies between the operands and results of the operations can be expressed through a tree structure. After conversion to the intermediate representation in the form of a three-address, the dependencies between the operands and results of the operations need to be expressed by creating a large number of temporary variables, and then all variables (including temporary variables and variables in the original kernel function) are assigned corresponding virtual registers, that is, virtual registers are used to represent variables.

[0054] Next, register allocation is performed on the target thread that executes the operator, that is, each virtual register generated above is mapped to the physical register corresponding to the target thread (that is, a preset number of physical registers pre-allocated to the target thread), that is, the variables associated with each virtual register are written out to the physical register mapped by the virtual register.

[0055] In this way, during the execution of an operator, when a variable associated with a virtual register is needed, the variable is read from the physical register mapped by the virtual register and executed.

[0056] Since the number of virtual registers is infinite, but the number of physical registers is limited, if the number of physical registers is insufficient during register allocation, register overflow will occur.

[0057] For example, suppose the target thread corresponds to 128 physical registers, and the number of virtual registers associated with the operator is 130. After allocating a physical register to each virtual register, there are still 2 virtual registers that have not been allocated physical registers, and register overflow occurs at this time.

[0058] In addition, in this application, the target thread can be any thread in the thread group, multiple threads in the thread group concurrently execute operators, and each thread in the thread group is applicable to the register overflow optimization method in this application. Of course, the target thread may not belong to any thread group, and this application does not make specific limitations on this.

[0059] Step 202: If register overflow occurs during the register allocation process, the overflowed virtual register is written out to the target stack space corresponding to the target thread in the on-chip cache.

[0060] Specifically, the overflowed virtual register is a virtual register that has no physical register assigned to it in the operator. A stack (also called a stack or an overflow stack) is a storage medium for register overflow. The stack is used as a storage medium for register overflow, and its advantage is strong scalability. The present application pre-allocates storage space for the stack in the on-chip cache, and the storage space is the stack space.

[0061] For a thread group, each thread in the thread group corresponds to a stack space in the on-chip cache, and the target thread is any thread in the thread group.

[0062] When register overflow occurs in register allocation for the target thread, that is, when the number of physical registers of the target thread is insufficient, the overflowed virtual registers are written out to the target stack space corresponding to the target thread in the on-chip cache.

[0063] In an embodiment of the present application, a corresponding target stack space is set for the target thread in the on-chip cache. Compared with the access speed of the video memory, the access speed of the on-chip cache is faster. Therefore, when a register overflow occurs in the register allocation for the target thread, the overflowed virtual register is written to the target stack space corresponding to the target thread in the on-chip cache. In this way, the access speed to the stack space is faster, thereby reducing the delay caused by the register overflow, and further improving the operator performance.

[0064] In some embodiments, after the related technology writes the overflowed virtual register to the video memory, the overflowed virtual register needs to be read back from the video memory for processing during the operator execution. Since the reading and writing speeds of the video memory are relatively slow, in this case, even if the number of register overflows is small, the additional read and write stack overhead caused by the register overflow will cause a decrease in program performance, thereby affecting the operator performance.

[0065] In view of this, the present application writes the overflowed virtual register to the target stack space corresponding to the target thread in the on-chip cache, and then reads the overflowed virtual register from the target stack space during the execution of the operator, and then performs related calculations based on the read-back overflowed virtual register to obtain the calculation results.

[0066] In the embodiment of the present application, based on the high read and write speed of the on-chip cache, the overflowed virtual register is written to the on-chip cache during the compilation of the operator. When the data of the overflowed virtual register is needed, the data is retrieved from the on-chip cache, thereby reducing the overhead of reading and writing video memory and improving the running speed of the program.

[0067] In some embodiments, the plurality of physical registers associated with the target thread include: a stack pointer register for pointing to a target stack space.

[0068] If register overflow occurs during register allocation, the overflowed virtual register is written out to the target stack space pointed to by the stack pointer register.

[0069] Specifically, a physical register is reserved from multiple physical registers associated with the target thread as a stack pointer register, and the stack pointer register points to the target stack space corresponding to the target thread in the on-chip cache. Other physical registers associated with the target thread can be allocated to the virtual registers of the operator.

[0070] The stack pointer register stores the attribute information of the target stack space. In this way, when a register overflow occurs in the register allocation for the target thread, the target stack space corresponding to the target thread is quickly located in the on-chip cache based on the attribute information of the target stack space stored in the stack pointer register, and the overflowed virtual register is written to the target stack space.

[0071] In addition, in the scenario where multiple threads in a thread group concurrently execute operators, the target thread is a thread in the thread group, and each other thread in the thread group can reserve a physical register as a stack pointer register in the same way. When a register overflow occurs, the overflowed virtual register is written out to the stack space pointed to by the stack pointer register.

[0072] For example, see Figure 3 The thread group includes multiple threads. For each thread, the thread corresponds to N physical registers, namely register 0, register 1, ..., register (N-1), and register N. The reserved register (N-1) is used as the stack pointer register SP. The stack pointer register SP is used to point to the stack space corresponding to the thread in the on-chip cache.

[0073] In the embodiment of the present application, a physical register is reserved from multiple physical registers associated with the target thread to point to the target stack space corresponding to the target thread in the on-chip cache. Therefore, when register overflow occurs in the register allocation of the target thread, the overflowed virtual register can be quickly written to the target stack space corresponding to the target thread, thereby reducing the delay caused by the register overflow and improving the operator performance.

[0074] In practical applications, the attribute information of the target stack space may be the start address of the target stack space, the end address of the target stack space, the address range of the target stack space, and the like.

[0075] The following uses the attribute information of the target stack space as the starting address of the target stack space as an example for explanation:

[0076] The multiple physical registers associated with the target thread include: a stack pointer register for pointing to the start address of the target stack space.

[0077] Specifically, the starting address of the target stack space is the starting physical address of the target stack space in the on-chip cache. If register overflow occurs during register allocation, the overflowed virtual register is written to the starting address of the target stack space pointed to by the stack pointer register.

[0078] In some embodiments, calculating the starting address of the target stack space requires consumption of computing resources, and register overflow occurs frequently. If the starting address of the target stack space is calculated once every time a register overflow occurs, this will result in a large overhead of computing resources, thereby affecting operator performance.

[0079] In view of this, in the present application, if register overflow occurs during register allocation, and the register overflow occurs for the first time, the starting address of the target stack space is obtained, and the starting address of the target stack space is saved in the stack pointer register. Then the overflowed virtual register is written to the starting address of the target stack space pointed to by the stack pointer register.

[0080] When register overflow occurs for the target thread later, the overflowed virtual register can be directly written to the target stack space pointed to by the stack pointer register according to the starting address of the target stack space in the stack pointer register. This avoids frequent calculation of the starting address of the target stack space, reduces computing resource overhead, and thus improves operator performance.

[0081] In some embodiments, the target thread is any thread in the thread group, each thread in the thread group corresponds to a stack space in the on-chip cache, and each thread corresponds to a number in the thread group. In this case, the embodiment of the present application at least uses the following method to obtain the starting address of the target stack space:

[0082] The starting address of the target stack space is determined based on the initial address of the on-chip cache, the number of the target thread in the thread group, and the size of the stack space allocated to each thread.

[0083] Specifically, a storage space (i.e., stack space) of the size of stackSize is allocated in advance in the on-chip cache for each thread. Then, based on the number of the target thread in the thread group and the size of the stack space allocated to each thread, the offset of the target stack space in the on-chip cache is determined. Then, based on the initial address of the on-chip cache and the offset of the target stack space in the on-chip cache, the starting address of the target stack space is obtained.

[0084] It should be noted that each thread in the thread group can obtain the starting address of the corresponding stack space in the above manner, as shown in the following formula (1):

[0085] SP=sm_base+threadIdx*stackSize…………(1)

[0086] Among them, sm_base is the initial address of the on-chip cache, threadIdx is the number of each thread in the thread group, and stackSize is the size of the stack space allocated for each thread.

[0087] In some embodiments, since the on-chip cache is not only used to save overflowed virtual registers but also needs to serve other functions of the artificial intelligence chip, the on-chip cache may be short of storage space.

[0088] In view of this, in the present application, if register overflow occurs during register allocation and the storage space of the on-chip cache meets the register overflow requirement, the overflowed virtual register is written to the starting address of the target stack space pointed to by the stack pointer register.

[0089] That is, before writing the overflowed virtual register to the on-chip cache, it is first determined whether the storage space of the on-chip cache is sufficient to store the overflowed virtual register (ie, whether the storage space of the on-chip cache meets the register overflow requirement).

[0090] If the storage space of the on-chip cache is sufficient to hold the overflowed virtual registers, the overflowed virtual registers are written out to the starting address of the target stack space pointed to by the stack pointer register.

[0091] In some embodiments, when the storage space of the on-chip cache is insufficient to save the overflowed virtual registers, in order to avoid the loss of the overflowed virtual registers, the present application proposes that if a register overflow occurs during the execution of register allocation and the storage space of the on-chip cache does not meet the register overflow requirements, the overflowed virtual registers will be written out to the video memory.

[0092] That is, when the storage space of the on-chip cache is insufficient to store the overflowed virtual registers, the overflowed virtual registers are written out to the video memory, thus avoiding the loss of the overflowed virtual registers and ensuring the integrity of the data.

[0093] For example, see Figure 4 , is a process of a register overflow optimization method provided in an embodiment of the present application. The process of the method is executed by an artificial intelligence chip, and for each thread in a thread group, the following steps are performed respectively:

[0094] Step 401 : reserve a physical register from multiple physical registers associated with a thread as a stack pointer register.

[0095] The stack pointer register is used to point to the corresponding stack space of the thread in the on-chip cache.

[0096] Step 402: During the operator compilation process, a register allocation operation is performed.

[0097] Step 403, determine whether register overflow occurs, if so, execute step 404, otherwise execute step 409.

[0098] Step 404, determine whether it is the first time that register overflow occurs, if so, execute step 405, otherwise execute step 406.

[0099] Step 405 , calculate the starting address of the stack space pointed to by the stack pointer register, and then execute step 406 .

[0100] Step 406 , determining whether the storage space of the on-chip cache is sufficient, if so, executing step 407 , otherwise executing step 408 .

[0101] Step 407, write the overflowed virtual register to the stack space pointed to by the stack pointer register.

[0102] Specifically, the variables associated with the overflowed virtual register are written out to the stack space pointed to by the stack pointer register.

[0103] Step 408, write the overflowed virtual register to the video memory.

[0104] Specifically, the variables associated with the overflowed virtual registers are written out to the video memory.

[0105] Step 409: Allocate physical registers of the thread to multiple virtual registers of the operator.

[0106] In an embodiment of the present application, a corresponding stack space is set for the thread in the on-chip cache. Compared with the access speed of the video memory, the access speed of the on-chip cache is faster. Therefore, when a register overflow occurs in the register allocation for the thread, the overflowed virtual register is written out to the target stack space corresponding to the thread in the on-chip cache. In this way, the access speed to the stack space is faster, thereby reducing the delay caused by the register overflow, and further improving the operator performance.

[0107] Based on the same technical concept, the present application embodiment provides a structural diagram of a register overflow optimization device, such as Figure 5 As shown, the register overflow optimization device 500 includes:

[0108] A register allocation module 501 is used to allocate registers to a target thread executing the operator during operator compilation;

[0109] The writing module 502 is used for writing the overflowed virtual register to the target stack space corresponding to the target thread in the on-chip cache if register overflow occurs during the execution of the register allocation.

[0110] Optionally, it also includes a reading module 503;

[0111] The reading module 503 is specifically used for:

[0112] During execution of the operator, the overflowed virtual register is read from the target stack space.

[0113] Optionally, the multiple physical registers associated with the target thread include: a stack pointer register for pointing to the target stack space;

[0114] The writing module 502 is specifically used for:

[0115] If register overflow occurs during the execution of the register allocation, the overflowed virtual register is written out to the target stack space pointed to by the stack pointer register.

[0116] Optionally, the multiple physical registers associated with the target thread include: a stack pointer register for pointing to a starting address of the target stack space;

[0117] The writing module 502 is specifically used for:

[0118] If register overflow occurs during the execution of the register allocation, the overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

[0119] Optionally, the writing module 502 is specifically used for:

[0120] If a register overflow occurs during the register allocation process, and the register overflow occurs for the first time, obtaining a starting address of the target stack space, and storing the starting address of the target stack space in the stack pointer register;

[0121] The overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

[0122] Optionally, the target thread is any thread in a thread group, and each thread in the thread group corresponds to a stack space in an on-chip cache;

[0123] The writing module 502 is specifically used for:

[0124] The starting address of the target stack space is determined based on the initial address of the on-chip cache, the number of the target thread in the thread group, and the size of the stack space allocated to each thread.

[0125] Optionally, the writing module 502 is specifically used for:

[0126] If register overflow occurs during the register allocation process and the storage space of the on-chip cache meets the register overflow requirement, the overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

[0127] Optionally, the writing module 502 is further used for:

[0128] If register overflow occurs during the register allocation process, and the storage space of the on-chip cache does not meet the register overflow requirement, the overflowed virtual register is written out to the video memory.

[0129] In an embodiment of the present application, a corresponding target stack space is set for the target thread in the on-chip cache. Compared with the access speed of the video memory, the access speed of the on-chip cache is faster. Therefore, when a register overflow occurs in the register allocation for the target thread, the overflowed virtual register is written to the target stack space corresponding to the target thread in the on-chip cache. In this way, the access speed to the stack space is faster, thereby reducing the delay caused by the register overflow, and further improving the operator performance.

[0130] Based on the same technical concept, the embodiment of the present application provides a computer device, such as Figure 6 As shown, it includes at least one artificial intelligence chip 100 and a memory 601 connected to the at least one artificial intelligence chip 100. The specific connection medium between the artificial intelligence chip 100 and the memory 601 is not limited in the embodiment of the present application. Figure 6 In the example, the artificial intelligence chip 100 and the memory 601 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0131] In an embodiment of the present application, the memory 601 stores instructions that can be executed by at least one artificial intelligence chip 100. At least one artificial intelligence chip 100 can perform the steps of the above-mentioned register overflow optimization method by executing the instructions stored in the memory 601.

[0132] Among them, the artificial intelligence chip 100 is the control center of the computer device, and various interfaces and lines can be used to connect various parts of the computer device, and register overflow optimization can be achieved by running or executing instructions stored in the memory 601 and calling data stored in the memory 601. Optionally, the artificial intelligence chip 100 may include one or more processing units, and the artificial intelligence chip 100 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 601 can be implemented on the same chip, and in some embodiments, they can also be implemented separately on independent chips.

[0133] The artificial intelligence chip 100 can be a general-purpose processor, such as a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application can be directly embodied as a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0134] Memory 601, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules. Memory 601 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (Random Access Memory, RAM), static random access memory (Static Random Access Memory, SRAM), programmable read-only memory (Programmable Read Only Memory, PROM), read-only memory (Read Only Memory, ROM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic memory, disk, optical disk, etc. Memory 601 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer device, but is not limited thereto. The memory 601 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0135] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program executable by a computer device. When the computer program runs on the computer device, the computer device executes the steps of the above-mentioned register overflow optimization method.

[0136] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer device, the computer device executes the steps of the above-mentioned register overflow optimization method.

[0137] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0138] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer device or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0139] These computer program instructions may also be stored in a computer readable memory capable of directing a computer device or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0140] These computer program instructions can also be loaded onto a computer device or other programmable data processing device so that a series of operation steps are executed on the computer device or other programmable device to produce a process implemented by the computer device, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0141] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0142] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A register overflow optimization method, characterized in that: include: During operator compilation, register allocation is performed on a target thread that executes the operator; If register overflow occurs during the register allocation process, the overflowed virtual register is written out to the target stack space corresponding to the target thread in the on-chip cache.

2. The method according to claim 1, characterized in that Also includes: During execution of the operator, the overflowed virtual register is read from the target stack space.

3. The method according to claim 1, characterized in that The multiple physical registers associated with the target thread include: a stack pointer register for pointing to the target stack space; If register overflow occurs during the register allocation, the overflowed virtual register is written out to the target stack space corresponding to the target thread in the on-chip cache, including: If register overflow occurs during the execution of the register allocation, the overflowed virtual register is written out to the target stack space pointed to by the stack pointer register.

4. The method according to claim 1, characterized in that The multiple physical registers associated with the target thread include: a stack pointer register for pointing to the starting address of the target stack space; If register overflow occurs during the register allocation, the overflowed virtual register is written out to the target stack space corresponding to the target thread in the on-chip cache, including: If register overflow occurs during the execution of the register allocation, the overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

5. The method according to claim 4, characterized in that If register overflow occurs during the register allocation, the overflowed virtual register is written to the starting address of the target stack space pointed to by the stack pointer register, comprising: If a register overflow occurs during the register allocation process, and the register overflow occurs for the first time, obtaining a starting address of the target stack space, and storing the starting address of the target stack space in the stack pointer register; The overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

6. The method according to claim 5, characterized in that The target thread is any thread in a thread group, and each thread in the thread group corresponds to a stack space in an on-chip cache; The obtaining the starting address of the target stack space includes: The starting address of the target stack space is determined based on the initial address of the on-chip cache, the number of the target thread in the thread group, and the size of the stack space allocated to each thread.

7. The method according to claim 4, characterized in that If register overflow occurs during the register allocation, the overflowed virtual register is written to the starting address of the target stack space pointed to by the stack pointer register, comprising: If register overflow occurs during the register allocation process and the storage space of the on-chip cache meets the register overflow requirement, the overflowed virtual register is written out to the starting address of the target stack space pointed to by the stack pointer register.

8. The method according to claim 7, characterized in that Also includes: If register overflow occurs during the register allocation process, and the storage space of the on-chip cache does not meet the register overflow requirement, the overflowed virtual register is written out to the video memory.

9. A computer device comprising a memory, an artificial intelligence chip, and a computer program stored in the memory and executable on the artificial intelligence chip, characterized in that: When the artificial intelligence chip executes the computer program, the steps of the method as claimed in any one of claims 1 to 8 are implemented.

10. A computer-readable storage medium, characterized in that: It stores a computer program executable by a computer device. When the computer program is run on the computer device, the computer device executes the steps of the method according to any one of claims 1 to 8.

11. A computer program product, characterized in that The computer program product comprises a computer program stored on a computer-readable storage medium, wherein the computer program comprises program instructions, and when the program instructions are executed by a computer device, the computer device is caused to execute the steps of the method according to any one of claims 1 to 8.

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