BROM (Broadband Read Only Memory) implementation method and device based on storage equipment, equipment and medium
By introducing the smallest and most stable system and secondary boot program in BROM, the nonvolatile storage media of UFS devices or EMMC devices is solved, and the problems of limited space and poor flexibility of eFuse are achieved, achieving more efficient SOC startup and parameter reading Reduce costs and debugging difficulty.
Patent Information
- Application Number
- CN202411067476.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-06
- Publication Date
- 2024-12-31
AI Technical Summary
When existing BROMs are implemented through eFuse, they have limited space, high cost, poor flexibility, and poor startup performance and unstable traditional methods, making debugging difficult.
Using the BROM implementation method based on storage device, the control parameter information is read and verified by the nonvolatile storage medium of UFS device or EMMC device through the minimum and most stable system and the secondary boot program to start the SOC and support OTA Upgrade and rollback mechanisms for increased flexibility and performance.
Reduce SOC startup costs, improve startup performance and parameter read stability, enhance startup flexibility, and simplify debugging process.
Smart Images
Figure CN119225824A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of embedded system development, and in particular to a storage device-based BROM implementation method, device, equipment, and medium. Background Art
[0002] BROM (Boot Read-Only Memory) contains the initial level code required to start the SOC (System on Chip) and is a key component for starting the SOC. BROM is fixed in the SOC and is located in the chip's ROM (Read-Only Memory). It is a piece of software code that cannot be modified and is executed in the initial stage of system startup. eFuse is similar to EEPROM, which is a one-time programmable memory that is written with information before the chip leaves the factory. In a chip, the capacity of eFuse is usually very small. BROM usually uses eFuse to achieve limited configuration. At present, the operation of BROM is controlled by modifying the one-time programmable memory (electronic fuse, eFuse), but the eFuse space is limited, calculated in bits, the cost is high, and it can only be modified once, which has poor flexibility. Traditional BROM reads the boot code directly from the non-volatile memory in the UFS device. In order to meet high performance, traditional BROM tries to use a faster frequency for reading from the beginning. When problems occur in the mass production process, it cannot be modified or can only be modified once, which has poor flexibility. It can be seen that the current method of starting SOC has poor startup performance, instability, high cost, poor flexibility and difficulty in debugging. Summary of the invention
[0003] The present application aims to solve one of the technical problems in the related art at least to some extent.
[0004] To this end, the embodiments of the present application provide a BROM implementation method and apparatus, device, and medium based on a storage device, which can reduce the SOC startup cost, improve startup performance, parameter reading stability, and startup flexibility.
[0005] In a first aspect, an embodiment of the present application provides a BROM implementation method based on a storage device, including:
[0006] Based on the preset first control parameter information, configuring a minimum and most stable system; the minimum and most stable system is used to provide a basic system operating environment for starting the system;
[0007] The BROM code is started to determine the startup object; wherein the BROM code is divided into a first-level boot program and a second-level boot program;
[0008] When it is determined that the boot object is a storage device, the first level boot program in the BROM code is executed under the minimum and most stable system, and second control parameter information is read from a preset parameter space of the storage device according to the first control parameter information;
[0009] Perform data verification processing on the second control parameter information. If the data verification processing passes, execute the second-level boot program in the BROM code, perform second data reading processing according to the second control parameter information, and read the boot code from the storage device to start the SOC.
[0010] According to some embodiments of the present application, after performing data verification processing on the second control parameter information, the method further includes:
[0011] In the case that the data verification process fails, a first data reading process is performed according to the first control parameter information to read a boot code from the storage device to start the SOC.
[0012] According to some embodiments of the present application, the storage device is: a UFS device or an EMMC device.
[0013] According to some embodiments of the present application, when the storage device is a UFS device, the second data reading process includes:
[0014] Determine a new read rate, a new UFS parameter, a UFS BROM strategy, and a system parameter according to the second control parameter information;
[0015] The boot code is read from the UFS device according to the new read rate, the new UFS parameter, the UFS BROM policy, and the system parameter.
[0016] According to some embodiments of the present application, the second control parameter information includes debug printing control information, and the method further includes:
[0017] Acquire debug printing control information from the second control parameter information;
[0018] In the process of reading the boot code from the storage device, or in the case of an error in the mass production stage, debug printing processing is performed according to the debug printing control information to obtain debug information.
[0019] According to some embodiments of the present application, the method further includes:
[0020] When the second control parameter information needs to be modified, receiving an update package sent by the OTA server through a wireless network;
[0021] According to the update package, the second control parameter information is updated to obtain updated third control parameter information.
[0022] According to some embodiments of the present application, the method further includes:
[0023] When the second control parameter information does not need to be updated and an error occurs during the mass production phase, a rollback mechanism is triggered;
[0024] Under the rollback mechanism, the second control parameter information is rolled back to the first control parameter information, so that during the execution of the second-level boot program, the boot code is read according to the first control parameter information.
[0025] In a second aspect, the present application provides a BROM implementation device, comprising at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the BROM implementation method based on the storage device as described in any one of the embodiments of the first aspect.
[0026] In a third aspect, the present application provides an electronic device, comprising a BROM implementation device as provided in the embodiment of the second aspect.
[0027] In a fourth aspect, the present application provides a storage medium, which is a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the BROM implementation method based on a storage device as described in any one of the embodiments of the first aspect.
[0028] The embodiments of the present application include: first, configuring a minimum and most stable system based on preset first control parameter information; the minimum and most stable system is used to provide a basic system operating environment for starting the system; secondly, the BROM code is started to determine the startup object; wherein the BROM code is divided into a first-level boot program and a second-level boot program; then, when it is determined that the startup object is a storage device, the first-level boot program in the BROM code is executed under the minimum and most stable system, and the second control parameter information is read from a preset parameter space of the storage device according to the first control parameter information; then, the second control parameter information is subjected to data verification processing, and when the data verification processing passes, the second-level boot program in the BROM code is executed, and a second data reading processing is performed according to the second control parameter information, and the boot code is read from the storage device to start the SOC. The embodiment of the present application utilizes a storage device (such as a UFS device) to replace the eFuse. The non-volatile medium of the storage device (such as a UFS device) has a large capacity, can store a lot of data, can be modified multiple times, has good flexibility and scalability, and is conducive to providing flexibility at startup and reducing the SOC startup cost. By introducing the minimum and most stable system and the second-level boot, the first-level boot is performed under the minimum and most stable system to ensure that the second control parameter information stored in the parameter space of the storage device can be stably read, thereby improving the stability of the startup parameter reading. And based on the second control parameter information, high-performance second data reading processing is performed to improve the startup performance. That is to say, the embodiment of the present application can reduce the SOC startup cost, improve the startup performance, parameter reading stability, and startup flexibility.
[0029] Other features and advantages of the invention will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a flowchart of a BROM implementation method based on a storage device provided by an embodiment of the present application;
[0031] Figure 2 It is a specific flow chart of a BROM implementation method based on a storage device provided by an embodiment of the present application;
[0032] Figure 3 This is a schematic diagram of a specific process of OTA upgrade provided by an embodiment of the present application;
[0033] Figure 4 It is a schematic diagram of the hardware structure of a BROM implementation device provided by an embodiment of the present application. DETAILED DESCRIPTION
[0034] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0035] It should be noted that although a logical order is shown in the flowchart in the description of the present application, in some cases, the steps shown or described may be performed in an order different from that in the flowchart. In the description of the present application, a number of means one or more, and a plurality of means two or more. The description of "first" and "second" is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.
[0037] First, some terms used in this application are explained:
[0038] BROM usually refers to Boot Read-Only Memory. It is a key component in the boot process and contains the initial level code required for system startup. BROM is located in the chip's ROM (Read-Only Memory) and is the code executed in the initial stage of system startup.
[0039] SOC, which stands for System on a Chip, is an integrated circuit design method that integrates the main components of a traditional computer or other electronic system into a single chip. These components usually include a central processing unit (CPU), a graphics processing unit (GPU), memory, input / output (I / O) interface, and possible other functional modules such as analog circuits, digital signal processors (DSP), wireless communication modules, etc.
[0040] eFuse, the full name of which is electronic fuse, is a one-time programmable memory and a non-volatile memory device; it is used to store information and protect chips.
[0041] Boot code, also known as startup code or boot code, is a program that is first executed when a computer or embedded system is turned on or restarted. Its main functions are to initialize hardware devices, establish memory space mapping, load the operating system kernel, and prepare the system operating environment. Boot code is the basis for the system to start and run the operating system normally. Boot code is usually stored on non-volatile storage media such as ROM, EPROM, EEPROM or flash memory to ensure that the code is not lost after power failure.
[0042] UFS (Universal Flash Storage) is a high-performance, highly integrated storage device interface standard developed by JEDEC (Joint Electron Device Engineering Council). UFS is designed to meet the growing demand for high-speed read and write performance and high data throughput in mobile devices. It is designed to replace the old eMMC (embedded Multimedia Card) standard and provide higher data transfer rates and better energy efficiency.
[0043] Static Random-Access Memory (SRAM) is a common system memory. The data in SRAM does not need to be refreshed, and the data will not be lost during power-on. The cost of SRAM is relatively high.
[0044] Dump registers usually refer to the function of outputting the processor's register status to a log file or other storage medium when an error, exception, or debugging occurs. It is very important for system debugging and error analysis.
[0045] OTA (Over-The-Air) remote upgrade is a wireless update technology that allows device manufacturers and software developers to push software updates to devices via wireless networks without manual user intervention. It can be used to update firmware, data, and applications without physically connecting to the device. During the OTA upgrade process, the device needs to establish a connection with the OTA server, which is usually achieved through Wi-Fi, cellular networks, or other wireless communication technologies. The OTA server can send the upgrade package to the target device, so that the target device can be upgraded.
[0046] BROM (Boot Read-Only Memory) contains the initial level code required to start the SOC (System on Chip) and is a key component for starting the SOC. BROM is fixed in the SOC and is located in the chip's ROM (Read-Only Memory). It is a piece of software code that cannot be modified and is executed in the initial stage of system startup. eFuse is similar to EEPROM, which is a one-time programmable memory that is written with information before the chip leaves the factory. In a chip, the capacity of eFuse is usually very small. BROM usually uses eFuse to achieve limited configuration. At present, the operation of BROM is controlled by modifying the one-time programmable memory (electronic fuse, eFuse), but the eFuse space is limited, calculated in bits, the cost is high, and it can only be modified once, which has poor flexibility. Traditional BROM reads the boot code directly from the non-volatile memory of the UFS device. In order to meet high performance, traditional BROM tries to use a faster frequency for reading from the beginning. When problems occur in the mass production process, it cannot be modified or can only be modified once, which has poor flexibility. It can be seen that the current method of starting SOC has poor startup performance, instability, high cost, poor flexibility and difficulty in debugging.
[0047] In addition, the UFS protocol is a 4-layer protocol stack. In order to achieve high-speed transmission (up to 11.6Gps perlane), its design is very complex, and even uses the MIPI protocol M-PHY as the physical layer. The complex protocol makes the parameters that need to be configured complex and numerous. In addition, the UFS controller also needs to run firmware, and provide firmware upgrade services when problems are found. However, in order to save costs and simplify the manufacturing process, the UFS controller does not use non-volatile storage media, only a small amount of SRAM. In this way, the firmware can only be updated to the SRAM every time the power is turned on. The internal firmware of the UFS controller can only ensure that the low rate is stable.
[0048] This makes it a big challenge to implement BROM based on UFS devices. On the one hand, setting a large number of parameters in BROM will bring great risks to mass production. It is understandable that once BROM is mass-produced, it cannot be changed. Moreover, if eFuse is used to control a large number of parameters, it will bring huge startup costs. In the existing solution, only a small number of parameters can be controlled by eFuse, and eFuse has only one modification opportunity, which is poor in flexibility. On the other hand, if the firmware is upgraded in BROM, it will not only bring complicated operations, but also greatly increase the risk of mass production, resulting in UFS devices can only use the lowest rate. The large number of parameters and the need to upgrade the firmware also lead to the conservative design of UFS BROM, and the parameters choose conservative parameters and low rates, which in turn limits the startup performance of UFS BROM, resulting in the startup performance of UFS BROM being even worse than that of emmc. For performance, stability and other reasons, BROM has few debug methods, not even basic printing, and only a few debug registers. For complex UFS BROM, how to debug in mass production is also an important issue.
[0049] Currently, UFS devices are widely used in electronic products such as tablets as the main storage device. Therefore, the BROM on the SOC side needs to read the boot code from the UFS device to finally complete the startup of the entire OS system. In order to achieve higher performance, the design of the UFS master control is very complex, with many parameters. Even the master control itself is equivalent to a SOC, which needs to run firmware and even needs to update the firmware of the UFS master control according to the subsequent mass production situation. This puts forward relatively high requirements for the implementation of the UFS BROM on the SOC side. It is necessary to strike a balance between startup performance and stability, ensure performance while ensuring stability, and provide relatively detailed debug functions to analyze the causes of mass production problems.
[0050] Based on this, the present application provides a BROM implementation method based on a storage device, a BROM implementation device, an electronic device, and a computer-readable storage medium; the method includes: configuring the minimum and most stable system based on the preset first control parameter information; starting the BROM code and determining the startup object; when it is determined that the startup object is a storage device, executing the first-level boot program in the BROM code under the minimum and most stable system, and reading the second control parameter information from the preset parameter space of the storage device according to the first control parameter information; performing data verification processing on the second control parameter information, and executing the second-level boot program in the BROM code when the data verification processing passes, performing second data reading processing according to the second control parameter information, and reading the boot code from the storage device to start the SOC. It can reduce the startup cost of the SOC, improve the startup performance, parameter reading stability, and startup flexibility.
[0051] The embodiments of the present application are further described below in conjunction with the accompanying drawings.
[0052] First, as Figure 1 As shown, Figure 1 It is a flowchart of a BROM implementation method based on a storage device provided by an embodiment of the present application; the BROM implementation method based on a storage device may include but is not limited to steps S110 to S140.
[0053] Step S110: configuring a minimum and most stable system based on the preset first control parameter information; the minimum and most stable system is used to provide a basic system operating environment for starting the system.
[0054] Step S120: The BROM code is started and a startup object is determined; wherein the BROM code is divided into a first-level boot program and a second-level boot program.
[0055] Step S130: When it is determined that the boot object is a storage device, the first-level boot program in the BROM code is executed under the minimum and most stable system, and the second control parameter information is read from the preset parameter space of the storage device according to the first control parameter information.
[0056] Step S140: Perform data verification processing on the second control parameter information. If the data verification processing passes, execute the second-level boot program in the BROM code, perform second data reading processing according to the second control parameter information, and read the boot code from the storage device to start the SOC.
[0057] It is understandable that in step S110, during the process of starting the SOC, the minimum and most stable system generally refers to an operating system environment that contains only the most basic functions and drivers, which is sufficient to support the lowest level operation of the device and further system startup process. The minimum and most stable system is used to perform: hardware initialization, setting and configuring various hardware components on the SOC; system configuration, such as setting the clock, network interface, etc.
[0058] It is understandable that in step S110, the first control parameter information refers to the most basic, reliable and fully verified configuration settings and performance indicators in the system design. The first control parameter information includes: the lowest reading rate, the most stable and conservative parameters. These parameters and rates ensure that the SOC can operate stably under various conditions, even in the most demanding working environment or the most unfavorable external conditions.
[0059] It is understandable that during the boot process, according to the system design and the boot sequence, boot data in the storage device (eg, UFS device) may be read. Therefore, firstly, step S120 is executed to start the BROM code and check the boot mode to determine the boot object.
[0060] According to some embodiments of the present application, step S140 is further described, wherein, after performing data verification processing on the second control parameter information, the method further includes: if the data verification processing fails, performing first data reading processing according to the first control parameter information, and reading the boot code from the storage device to start the SOC.
[0061] According to some embodiments of the present application, the storage device is: a UFS device or an EMMC device. It is understandable that the storage device is an embedded storage device. The BROM implementation method provided in the embodiments of the present application can also be applied to other storage devices similar to UFS devices. Therefore, the present application does not specifically limit the type of storage device.
[0062] Through step S110 to step S140, first, based on the preset first control parameter information, the minimum and most stable system is configured; the minimum and most stable system is used to provide a basic system operating environment for starting the system; secondly, the BROM code is started to determine the startup object; wherein the BROM code is divided into a first-level boot program and a second-level boot program; then, when it is determined that the startup object is a storage device, the first-level boot program in the BROM code is executed under the minimum and most stable system, and the second control parameter information is read from the preset parameter space of the storage device according to the first control parameter information; then, the second control parameter information is subjected to data verification processing, and when the data verification processing passes, the second-level boot program in the BROM code is executed, and the second data reading processing is performed according to the second control parameter information, and the boot code is read from the storage device to start the SOC. The embodiment of the present application utilizes a storage device (such as a UFS device) to replace the eFuse. The non-volatile medium of the storage device (such as a UFS device) has a large capacity, can store a lot of data, can be modified multiple times, has good flexibility and scalability, and is conducive to providing flexibility at startup and reducing the SOC startup cost. By introducing the minimum and most stable system and the second-level boot, the first-level boot is performed under the minimum and most stable system to ensure that the second control parameter information stored in the parameter space of the storage device can be stably read, thereby improving the stability of the startup parameter reading. And based on the second control parameter information, high-performance second data reading processing is performed to improve the startup performance. Therefore, the embodiment of the present application can reduce the SOC startup cost, improve the startup performance, parameter reading stability, and startup flexibility.
[0063] Taking an example to further illustrate steps S110 to S140 of the BROM implementation method provided in the embodiment of the present application when the storage device is a UFS device.
[0064] In one embodiment, before executing step S130, a parameter space is pre-set in the UFS device; and the second control parameter information is stored in the parameter space. It can be understood that a parameter space is pre-reserved in the non-volatile storage medium of the UFS device, and the parameter space is used to store the control parameters of the UFS BROM (i.e., the second control parameter information). That is, the UFS device is used to replace the eFuse to obtain a larger, cheaper, lower-cost and reusable parameter range. Since the capacity of the non-volatile storage medium of the UFS device is large, the number of parameters that can be saved is large, and the non-volatile storage medium of the UFS device can be modified multiple times, its flexibility and scalability are better than eFuse. When the UFS device is used in electronic products such as tablet computers, the UFS device is the main storage device that must be used. Opening up a parameter space in it to replace the eFuse space can save eFuse space and reduce the SOC hardware cost. In addition, the parameter space of the UFS device is very small compared to the UFS device, and the required control parameters can be read out quickly from the parameter space, which has little effect on the startup performance of the BROM; it is conducive to improving the startup performance.
[0065] It should be noted that in the embodiment of the present application, the BROM code is divided into a first-level boot program and a second-level boot program, that is, two-level boot is implemented in the BROM, the first-level boot reads the second control parameter information from the parameter space of the UFS device, and the second-level boot reads the real boot code according to the second control parameter information to start the SOC.
[0066] It is understandable that the smallest and most stable system is selected, and the first control parameter information (including the most stable and conservative parameters and the lowest reading rate) is used as a bottom line solution. The first level boot is performed based on the first control parameter information to ensure that the second control parameter information is stably read from the parameter space of the UFS device; then, according to the second control parameter information, the subsequent BROM is controlled to run with high performance; to solve the problem of how to stably and efficiently read the control parameters of the BROM. The embodiment of the present application configures a minimum and most stable system operating environment (i.e., a bottom line solution) to ensure that the second control parameter information can be stably read out. In addition, it is also ensured that once there is a problem (for example, a firmware upgrade is required, and the existing firmware can only ensure that the low rate is stable), the BROM can use this minimum stable environment to safely read the boot data in the first and second level boots through OTA and other methods, thereby improving the robustness of the BROM. The setting of the bottom line solution, i.e., the setting of the first control parameter information, also provides a reliable emergency guarantee for the second level boot to improve performance. The second level boot can not only increase the UFS frequency, but also increase the CPU frequency, bus frequency and other system parameters that help improve performance.
[0067] According to some embodiments of the present application, step S140 is further described. After performing data verification processing on the second control parameter information, the method also includes: if the data verification processing fails, performing first data reading processing according to the first control parameter information, reading the boot code from the UFS device to start the SOC.
[0068] When the storage device is a UFS device, through step S110 to step S140, first, based on the preset first control parameter information, the minimum and most stable system is configured; the minimum and most stable system is used to provide a basic system operating environment for starting the system; secondly, the BROM code is started to determine the startup object; wherein the BROM code is divided into a first-level boot program and a second-level boot program; then, when it is determined that the startup object is a UFS device, the first-level boot program in the BROM code is executed under the minimum and most stable system, and according to the first control parameter information, the second control parameter information is read from the preset parameter space of the UFS device; then, the second control parameter information is subjected to data verification processing, and when the data verification processing passes, the second-level boot program in the BROM code is executed, and a second data reading processing is performed according to the second control parameter information, and the boot code is read from the UFS device to start the SOC. The embodiment of the present application uses a UFS device to replace eFuse. The UFS device has a large non-volatile medium capacity, can store a lot of data, can be modified multiple times, has good flexibility and scalability, and is conducive to providing flexibility at startup and reducing the SOC startup cost. By introducing the minimum and most stable system and the second-level boot, the first-level boot is performed under the minimum and most stable system to ensure that the second control parameter information stored in the parameter space of the UFS device can be stably read, thereby improving the stability of the startup parameter reading. And based on the second control parameter information, high-performance second data reading processing is performed to improve the startup performance. Therefore, the embodiment of the present application can reduce the SOC startup cost, improve the startup performance, parameter reading stability, and startup flexibility.
[0069] According to some embodiments of the present application, when the storage device is a UFS device, the second data reading process includes but is not limited to the following steps:
[0070] According to the second control parameter information, a new read rate, a new UFS parameter, a UFS BROM policy, and a system parameter are determined; according to the new read rate, the new UFS parameter, the UFS BROM policy, and the system parameter, the boot code is read from the UFS device. In this way, the BROM can be run with high performance based on the second control parameter information, which is conducive to improving the boot performance.
[0071] Specifically, the UFS BROM policy may be: reinitialize the host and the UFS device using new UFS parameters and then read the data.
[0072] Specifically, the system parameters include, for example, CPU frequency, bus frequency, and so on.
[0073] According to some embodiments of the present application, the second control parameter information includes debug printing control information. The BROM implementation method based on the storage device provided in the embodiment of the present application also includes but is not limited to the following steps:
[0074] The debug printing control information is obtained from the second control parameter information; in the process of reading the boot code from the UFS device, or in the case of an error in the mass production stage, debug printing processing is performed according to the debug printing control information to obtain debug information. In this way, controllable debug printing processing is achieved.
[0075] Specifically, you can add an option to turn on printing in the parameter space, and turn on BROM printing when there are mass production problems. This will improve debug efficiency and solve the problem of BROM not printing and debugging difficulties. In addition, you can also add a dump register function. When mass production errors occur, you can print out the registers to get the first-hand information of the problem.
[0076] For example, when the storage device is a UFS device, combined with Figure 2 The specific process of the BROM implementation method based on the UFS device provided in the embodiment of the present application is described.
[0077] Step S201: UFS BROM starts.
[0078] Step S202: Perform UFS initialization processing using the most conservative parameters and the lowest read rate to initialize the UFS controller and the UFS device.
[0079] Step S203: Use the most conservative parameters and the lowest reading rate to read the second control parameter information stored in the parameter space of the UFS device. The most conservative parameters and the lowest reading rate are the first control parameter information of the embodiment of the present application.
[0080] Step S204: verify the second control parameter information.
[0081] Step S205: Determine whether the verification is passed; if the verification is passed, execute steps S206 to S209; if the verification is not passed, execute step S210.
[0082] Step S206: Determine a new read rate, new UFS parameters, and system parameters according to the second control parameter information.
[0083] Step S207: Determine whether to perform debug printing processing or open debug information according to the second control parameter information.
[0084] Step S208: Determine the UFS BROM strategy according to the second control parameter information, such as reinitializing the host and the UFS device with new UFS parameters and then reading data.
[0085] Step S209: Read boot data from the UFS device according to the new read rate, new UFS parameters, UFS BROM policy and system parameters.
[0086] Step S210: Continue to use the most conservative parameters and the lowest reading rate to read the boot data.
[0087] In the BROM implementation method based on the storage device provided in the embodiment of the present application, an OTA remote upgrade function is also configured.
[0088] According to some embodiments of the present application, the BROM implementation method based on the storage device also includes but is not limited to the following steps:
[0089] When the second control parameter information needs to be modified, an update package sent by the OTA server is received through a wireless network; the second control parameter information is updated according to the update package to obtain updated third control parameter information.
[0090] According to some embodiments of the present application, the BROM implementation method based on the storage device also includes but is not limited to the following steps:
[0091] When the second control parameter information does not need to be updated and an error occurs in the mass production stage, the rollback mechanism is triggered; under the rollback mechanism, the second control parameter information is rolled back to the first control parameter information, so that during the execution of the second-level boot program, the boot code is read according to the first control parameter information.
[0092] It is understandable that the parameter space of the UFS device can be modified multiple times, so that remote control of BROM behavior can be achieved. If a problem with the control parameters is found and the parameters need to be updated, or if a problem occurs during the mass production stage, the BROM parameters can be remotely modified through OTA upgrades, or even the second control parameter information can be directly restored to the most conservative parameters and the lowest read rate (i.e. the first control parameter information) based on the rollback mechanism.
[0093] Take an example, combined with Figure 3 , explaining the specific process of OTA upgrade.
[0094] Step S301: OTA upgrade starts.
[0095] Step S302, determine whether the parameters need to be updated; if so, execute step S303; if not, execute steps S304 to S305.
[0096] Step S303: Update parameters.
[0097] Step S304: When a mass production problem is found, it is necessary to roll back to conservative parameters and the lowest read rate.
[0098] Step S305: Roll back to the conservative parameters and the lowest reading rate, and use the conservative parameters and the lowest reading rate.
[0099] It is understandable that, based on the BROM implementation method based on the storage device provided in the embodiment of the present application, burning and mass production are carried out to achieve product differentiation and customization. Specifically, after mass production begins, the type of parameters used is determined according to the customer category or differentiated needs. For customers who pursue stability, the first control parameter information is used. For customers who do not pursue stability, the second control parameter information is used. In this way, product differentiation can be achieved at the same time, with high-end products having a high rate and low-end products having a low rate.
[0100] In summary, the embodiment of the present application reduces the startup cost by introducing the smallest and most stable system in BROM, introducing secondary boot, and using UFS devices instead of eFuse. At the same time, the performance of ufs brom can be controlled, the parameters and policies can be controlled and rewritten multiple times, the printing debug can be controlled, and remote control can be achieved through OTA upgrade, so that the mass production process can be differentiated and customized. The flexibility, compatibility, and performance of the BROM implementation method based on storage devices are improved, and debugging is easy.
[0101] Second, as Figure 4 As shown, the present application also provides a BROM implementation device 400, including:
[0102] The processor 401 may be implemented by a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;
[0103] The memory 402 may be implemented in the form of a read-only memory, a static storage device, a dynamic storage device, or a random access memory. The memory 402 may store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 402, and the processor 401 calls and executes the BROM implementation method based on the storage device in the embodiment of this application;
[0104] Input / output interface 403, used to implement information input and output;
[0105] Communication interface 404, used to realize communication interaction between the present apparatus and other devices, which can be realized by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);
[0106] Bus 405 , which transmits information between various components of the device (e.g., processor 401 , memory 402 , input / output interface 403 , and communication interface 404 );
[0107] The processor 401 , the memory 402 , the input / output interface 403 and the communication interface 404 are connected to each other in communication within the device via the bus 405 .
[0108] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the BROM implementation device as described above.
[0109] In a fourth aspect, an embodiment of the present application provides a storage medium, which is a computer-readable storage medium. The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the BROM implementation method based on a storage device as in the above embodiment.
[0110] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.
[0111] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
[0112] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.
[0113] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above-mentioned implementation mode. Technical personnel familiar with the field can also make various equivalent deformations or substitutions without violating the spirit of the present application. These equivalent deformations or substitutions are all included in the scope defined by the present application.
Claims
1. A BROM implementation method based on a storage device, characterized in that: include: Based on the preset first control parameter information, configuring the minimum and most stable system; The minimum and most stable system is used to provide a basic system operating environment for starting the system; The BROM code is started to determine the startup object; wherein the BROM code is divided into a first-level boot program and a second-level boot program; When it is determined that the boot object is a storage device, the first level boot program in the BROM code is executed under the minimum and most stable system, and second control parameter information is read from a preset parameter space of the storage device according to the first control parameter information; Perform data verification processing on the second control parameter information. If the data verification processing passes, execute the second-level boot program in the BROM code, perform second data reading processing according to the second control parameter information, and read the boot code from the storage device to start the SOC.
2. The BROM implementation method based on a storage device according to claim 1, characterized in that: After performing data verification processing on the second control parameter information, the method further includes: In the case that the data verification process fails, a first data reading process is performed according to the first control parameter information to read a boot code from the storage device to start the SOC.
3. The BROM implementation method based on a storage device according to claim 1, characterized in that: The storage device is: a UFS device or an EMMC device.
4. The BROM implementation method based on a storage device according to claim 1, characterized in that: When the storage device is a UFS device, the second data reading process includes: Determine a new read rate, a new UFS parameter, a UFS BROM strategy, and a system parameter according to the second control parameter information; The boot code is read from the UFS device according to the new read rate, the new UFS parameter, the UFS BROM policy, and the system parameter.
5. The BROM implementation method based on a storage device according to claim 1, characterized in that: The second control parameter information includes debug printing control information, and the method further includes: Acquire debug printing control information from the second control parameter information; In the process of reading the boot code from the storage device, or in the case of an error in the mass production stage, debug printing processing is performed according to the debug printing control information to obtain debug information.
6. The BROM implementation method based on a storage device according to claim 1, characterized in that: The method further comprises: When the second control parameter information needs to be modified, receiving an update package sent by the OTA server through a wireless network; According to the update package, the second control parameter information is updated to obtain updated third control parameter information.
7. The BROM implementation method based on a storage device according to claim 1, characterized in that: The method further comprises: When the second control parameter information does not need to be updated and an error occurs during the mass production phase, a rollback mechanism is triggered; Under the rollback mechanism, the second control parameter information is rolled back to the first control parameter information, so that during the execution of the second-level boot program, the boot code is read according to the first control parameter information.
8. A BROM implementation device, characterized in that: It includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the BROM implementation method based on the storage device as described in any one of claims 1 to 7.
9. An electronic device, characterized in that: It comprises the BROM implementation device as claimed in claim 8.
10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the BROM implementation method based on a storage device as described in any one of claims 1 to 8.