Cooperative training method and device of model, equipment, chip and program product

Abstract

The embodiment of the invention discloses a collaborative training method and device of a model, equipment, a chip and a program product. The method comprises the following steps: deploying a target network model into a storage and calculation integrated chip; obtaining sample data in a training data set and a true value corresponding to the sample data; according to the sample data and the target network model deployed in the storage and calculation integrated chip, obtaining a predicted value corresponding to the sample data; and updating the target network model deployed in the storage and calculation integrated chip according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

Description

Technical Field

[0001] The present application belongs to the field of artificial intelligence (AI) technology, and in particular relates to a collaborative training method, device, equipment, chip and program product of a model. Background Art

[0002] In related technologies, in order to compensate for the calculation errors in the integrated storage and computing chip, it is necessary to analyze the sources of errors in the calculation process, including errors generated by the model quantization process, chip simulation calculation errors, analog-to-digital (A / D) conversion errors, and current accumulation errors; for various types of errors, it is necessary to measure the errors and record the error values, and then compensate based on the recorded error values. It can be seen that this error compensation scheme has a high complexity problem because it needs to analyze the error sources and record the error values. Summary of the invention

[0003] In order to solve the problem of high complexity of the error compensation process of the storage and computing integrated chip existing in the related art, the embodiments of the present application propose a collaborative training method, device, equipment, chip and program product of the model.

[0004] The embodiment of the present application provides a collaborative training method of a model, which is applied to an electronic device, and the method includes:

[0005] Deploy the target network model to the storage-computing integrated chip;

[0006] Obtaining sample data in a training data set and true values ​​corresponding to the sample data;

[0007] Obtaining a prediction value corresponding to the sample data according to the sample data and the target network model deployed in the storage-computing integrated chip;

[0008] According to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, the target network model deployed in the storage and computing integrated chip is updated.

[0009] In some embodiments, the target network model deployed in the storage-computing integrated chip is updated according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, including: when the difference is greater than or equal to a preset value, the target network model deployed in the storage-computing integrated chip is updated, and the step of returning to obtaining the sample data in the training data set and the true value corresponding to the sample data is returned.

[0010] In some embodiments, the method further includes: when the difference is less than a preset value, stopping updating the target network model deployed in the storage and computing integrated chip, and determining the target network model deployed in the storage and computing integrated chip as the trained target network model.

[0011] In some embodiments, before deploying the target network model to the storage and computing integrated chip, the method also includes: deploying a floating-point model, quantizing the floating-point model, and obtaining the target network model; obtaining the predicted value corresponding to the sample data based on the sample data and the target network model deployed in the storage and computing integrated chip, including: when the sample data is floating-point type data, quantizing the sample data to obtain quantized sample data; sending the quantized sample data to the storage and computing integrated chip, so that the storage and computing integrated chip processes the quantized sample data according to the target network model to obtain a model output result; receiving the model output result sent by the storage and computing integrated chip, dequantizing the model output result, and obtaining the predicted value corresponding to the sample data.

[0012] In some embodiments, the target network model deployed in the storage-computing integrated chip is updated according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, including: when the difference is greater than or equal to a preset value, updating the floating-point model according to the difference to obtain an updated floating-point model; quantizing the updated floating-point model to obtain an updated target network model; and sending the updated target network model to the storage-computing integrated chip, so that the storage-computing integrated chip updates the deployed target network model.

[0013] In some embodiments, the training data set includes multiple sample data; updating the target network model deployed in the storage-computing integrated chip according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data includes: acquiring each sample data in the training data set in sequence by traversing; for each acquired sample data, updating the target network model deployed in the storage-computing integrated chip according to the difference between the true value corresponding to each sample data and the predicted value corresponding to each sample data; after traversing each sample data of the training data set once, adding 1 to the value of a preset number of loops variable, and when the value of the preset number of loops variable is less than a preset maximum number of loops, updating the target network model deployed in the storage-computing integrated chip, and returning to the step of acquiring the sample data in the training data set and the true value corresponding to the sample data.

[0014] In some embodiments, the method further includes: when the value of the preset number of loops variable is equal to a preset maximum number of loops, determining the target network model deployed in the storage-computing integrated chip as a trained target network model.

[0015] In some embodiments, deploying the target network model to the storage-computing integrated chip includes: determining weight data and control flow in the target network model, wherein the control flow is used to characterize the calculation method for the weight data in the storage-computing integrated chip; and sending the weight data and the control flow to the storage-computing integrated chip.

[0016] The embodiment of the present application also provides another model collaborative training method, which is applied to a storage-computing integrated chip, and the method includes:

[0017] Deploy the target network model;

[0018] The deployed target network model is updated by interacting with an electronic device; wherein the electronic device is used to obtain sample data in a training data set and true values ​​corresponding to the sample data; based on the sample data and the target network model deployed in the storage-computing integrated chip, a predicted value corresponding to the sample data is obtained; based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, the target network model deployed in the storage-computing integrated chip is updated.

[0019] In some embodiments, the deploying the target network model includes: receiving weight data and control flow in the target network model sent by the electronic device, the control flow being used to characterize the calculation method for the weight data in the storage and computing integrated chip; and deploying the weight data and the control flow into the storage and computing integrated chip.

[0020] In some embodiments, deploying the weight data and the control flow into the integrated storage and computing chip includes: deploying the weight data and the control flow to a preset fixed position of the integrated storage and computing chip.

[0021] The embodiment of the present application also provides a collaborative training device for a model, which is applied to an electronic device, and the device includes:

[0022] The first deployment module is used to deploy the target network model into the storage and computing integrated chip;

[0023] An acquisition module is used to acquire sample data in a training data set and true values ​​corresponding to the sample data;

[0024] The first processing module is used to obtain the predicted value corresponding to the sample data based on the sample data and the target network model deployed in the storage and computing integrated chip; and update the target network model deployed in the storage and computing integrated chip based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0025] The embodiment of the present application also provides another model of collaborative training device, which is applied to a storage-computing integrated chip, and the device includes:

[0026] The second deployment module is used to deploy the target network model;

[0027] The second processing module is used to update the deployed target network model by interacting with an electronic device; wherein the electronic device is used to obtain sample data in a training data set and true values ​​corresponding to the sample data; obtain predicted values ​​corresponding to the sample data based on the sample data and the target network model deployed in the storage-computing integrated chip; and update the target network model deployed in the storage-computing integrated chip based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0028] An embodiment of the present application also provides an electronic device, comprising a processor and a memory for storing a computer program that can be run on the processor; wherein the processor is used to run the computer program to execute any one of the above methods applied to the electronic device.

[0029] An embodiment of the present application also provides a storage-computing integrated chip, which includes a processor and a memory for storing a computer program that can be run on the processor; wherein the processor is used to run the computer program to execute any one of the above-mentioned methods applied to the storage-computing integrated chip.

[0030] An embodiment of the present application also provides a computer storage medium on which a computer program is stored. When the computer program is executed by a processor, a collaborative training method for any of the above-mentioned models is implemented.

[0031] An embodiment of the present application also provides a computer program product, including a computer program, which implements the collaborative training method of any of the above-mentioned models when executed by a processor.

[0032] It can be seen that in the embodiment of the present application, there is no need to analyze the error source of the storage and computing chip. Instead, the target network model can be collaboratively trained through electronic equipment and the storage and computing chip, thereby improving the data processing accuracy of the target network model, which is beneficial for making the output result of the target network model closer to the true value, and further, it is beneficial to learn the calculation error of the target network model in the storage and computing chip, reducing the complexity of the error compensation process in the storage and computing chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a von Neumann architecture in related technology;

[0034] Figure 2 It is a schematic diagram of the architecture of a storage-computing integrated chip in the related technology;

[0035] Figure 3 A schematic diagram of error sources that need to be compensated for analog storage-computing integrated chips in the related art;

[0036] Figure 4 A flowchart of a collaborative training method for a model applied to an electronic device according to an embodiment of the present application;

[0037] Figure 5 A schematic diagram of the connection relationship between the electronic device and the storage-computing integrated chip proposed in the embodiment of the present application;

[0038] Figure 6 A schematic diagram of a framework for collaborative training between an electronic device and a storage-computing integrated chip is provided for an embodiment of the present application;

[0039] Figure 7 A flowchart of a collaborative training method for a model applied to a storage-computing integrated chip according to an embodiment of the present application;

[0040] Figure 8 A schematic diagram of deploying weight data and control flow at a fixed position in an embodiment of the present application;

[0041] Fig. 9 A schematic diagram of the structure of a collaborative training device for a model of an electronic device according to an embodiment of the present application;

[0042] Fig.10 A schematic diagram of the structure of a collaborative training device for a model of a storage-computing integrated chip according to an embodiment of the present application;

[0043] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] See also Figure 1In the von Neumann architecture, the controller, calculator, and memory are separated, which has the problem of high energy consumption for memory access. With the development and application of deep learning technology, in order to solve the problems of frequent data movement between computing units and storage units, slow data transfer, and high energy consumption, storage and computing integrated chips came into being. Figure 2 The integrated storage and computing chip transforms the computing-centric architecture into a data-centric architecture, uses the integrated storage and computing array to organically integrate storage and computing functions, and directly uses storage units for data processing. The integrated storage and computing chip fundamentally solves the "storage wall" and "power consumption wall" problems of traditional von Neumann architecture chips.

[0045] In the technology development route of storage and computing integrated chips, since analog storage and computing integrated chips have significant advantages over digital storage and computing integrated chips in terms of energy efficiency, area efficiency, computing accuracy, design flexibility, computing speed, sparsity support, manufacturing cost and adaptability, the development of chips based on analog computing technology is booming. However, the biggest problem with analog storage and computing chips is that their calculation process is analog calculation, which will inevitably introduce the process of analog-to-digital conversion and inevitably bring about calculation errors.

[0046] In the related technology, the error compensation methods used for storage and computing integrated chips include calibration algorithms, adaptive filter design, redundant calculations, and error detection and correction mechanisms. For AI inference chips, calculation errors are often inevitably introduced due to hardware physical limitations and imperfections in the manufacturing process. In order to ensure the accuracy of the calculation results, error compensation technology has become an indispensable component. This technology accurately measures and analyzes the deviations that occur in the calculation process, and then applies algorithms or hardware mechanisms to correct these errors.

[0047] In a technical solution of the related art, the error compensation method for AI reasoning chips is mostly to obtain the compensation value by measuring the actual value and the theoretical value, and then record it. The compensation value is added as an offset to compensate for the error during the reasoning process. This method requires special analysis and processing of the errors generated during the reasoning process. Figure 3 As for the inference error compensation of analog storage and computing integrated chips, it is necessary to analyze the sources of errors in the calculation process, including errors generated by the model quantization process, DA conversion errors, array calculation errors, AD conversion errors, and current accumulation errors. For these errors, it is necessary to measure the errors process by process and record the error values. In the inference process, the recorded error values ​​are subtracted to correct the results. This method is relatively complex, and the errors are analyzed and recorded according to the process. The error values ​​of each layer are recorded separately. Small errors in the early stages may be magnified in the subsequent stages, resulting in significant deviations in the final results.

[0048] Furthermore, since different models of analog storage and computing integrated chips have different array size areas, minimum control units, and A / D converters, etc. When a neural network model is deployed on a storage and computing integrated chip, the error compensation method can be used to correct the current deployment position, but the recorded error compensation value is only applicable to the current deployment position. When the deployed array position changes, the A / D converter, current accumulator, and calculation area used are changed, and they need to be analyzed and recorded one by one again according to the error measurement method. Similarly, when the model structure on the chip changes, it causes a change in the deployment position, which also needs to be analyzed and recorded one by one again according to the error measurement method, so there is a problem of low efficiency.

[0049] In view of the above technical problems, a technical solution of the embodiment of the present application is proposed. The embodiment of the present application proposes an error compensation method for analog storage and computing integrated chips, which belongs to the field of machine intelligence in the field of the Internet of Things. The method can realize end-to-end training and deployment of storage and computing integrated chips, without analyzing and compensating the error sources of the storage and computing integrated chips, and compensates the calculation errors of the chips through collaborative training technology, and has a certain degree of universality.

[0050] The following is a further detailed description of the embodiments of the present application in conjunction with the accompanying drawings and examples. It should be understood that the embodiments provided herein are only used to explain the embodiments of the present application and are not intended to limit the embodiments of the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than providing all embodiments for implementing the present application. In the absence of conflict, the technical solutions recorded in the embodiments of the present application can be implemented in any combination.

[0051] It should be noted that, in the embodiments of the present application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or device including a series of elements includes not only the elements explicitly recorded, but also includes other elements not explicitly listed, or also includes elements inherent to the implementation of the method or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other related elements (such as steps in a method or units in a device, for example, a unit may be a part of a circuit, a part of a processor, a part of a program or software, etc.) in the method or device including the element.

[0052] The collaborative training method of the model provided in the embodiment of the present application includes a series of steps, but the collaborative training method of the model provided in the embodiment of the present application is not limited to the recorded steps. Similarly, the collaborative training device of the model provided in the embodiment of the present application includes a series of modules, but the device provided in the embodiment of the present application is not limited to including the modules explicitly recorded, and can also include modules required to obtain relevant information or perform processing based on information.

[0053] The embodiment of the present application provides a collaborative training method for a model applied to an electronic device. For example, the electronic device may be a terminal device such as a personal computer (PC). When the electronic device is a PC, the PC may support model weight updates and back propagation with 32-bit floating point (FP32) precision. A computing device such as a central processing unit (CPU) and a graphics processing unit (GPU) may be provided in the electronic device.

[0054] Figure 4 Flow chart of a collaborative training method for a model of an electronic device according to an embodiment of the present application, such as Figure 4 As shown, the process may include:

[0055] Step 401: Deploy the target network model into the storage and computing integrated chip.

[0056] In the embodiment of the present application, the storage-computing integrated chip can be an analog storage-computing integrated chip, and the electronic device can form a communication connection with the storage-computing integrated chip. The communication interface between the electronic device and the storage-computing integrated chip includes but is not limited to a serial peripheral interface (Serial Peripheral Interface, SPI), an integrated circuit bus (Inter-Integrated Circuit, I2C), and a universal asynchronous receiver / transmitter (UART). After the electronic device and the storage-computing integrated chip are connected by hardware, a data debugging assistant can be used to perform a data transmission and reception test to ensure that normal data communication can be performed between the two.

[0057] For example, refer to Figure 5 , the electronic device and the storage-computing integrated chip can be connected through the UART interface to realize data transmission. The storage-computing integrated chip can support integer (INT) reasoning calculation. The reasoning result can be transmitted through the UART interface to a PC with FP32 computing capability for back propagation and updating of iterative weights, so as to learn the calculation error of the storage-computing integrated chip.

[0058] For example, refer to Figure 5 The electronic device can also be connected to the storage and computing integrated chip through the J-Link interface, and the electronic device can download weights and data streams, thereby ensuring that the storage and computing integrated chip can normally receive the weights and control streams sent by the electronic device and update them.

[0059] In some embodiments of the present application, before this step, the electronic device may receive a floating-point model, and then quantize the floating-point model to obtain a target network model. Exemplarily, the floating-point model may be a pre-trained network model, for example, the floating-point model is an FP32 model M1, and the model M1 is deployed in a training project on an electronic device, where the deployment location may be a CPU or a GPU, as long as the computing device supports FP32 precision; when deploying the floating-point model on the electronic device, the loss function, learning rate and other information of the floating-point model may be set.

[0060] After the electronic device receives the floating point model, the floating point model can be quantized to obtain a target network model, which can be recorded as model M2. Weight data arrangement (remaining unchanged after recording) and control flow generation can be performed for model M2.

[0061] In some embodiments of the present application, the process of deploying the target network model to the storage-computing integrated chip includes: determining the weight data and control flow in the target network model, the control flow is used to characterize the calculation method for the weight data in the storage-computing integrated chip; sending the weight data and control flow to the storage-computing integrated chip. Exemplarily, the weight data and control flow can be downloaded to the storage-computing integrated chip via J-Link.

[0062] It can be seen that by sending the weight data and control flow to the storage and computing integrated chip, the storage and computing integrated chip can accurately perform calculations according to the weight data and control flow.

[0063] Step 402: Obtain sample data in the training data set and the true value corresponding to the sample data.

[0064] In an embodiment of the present application, a collaborative training data set can be selected, the data in the data set can be numbered, and the source data with the corresponding serial number in the data set can be taken out. The source data in the collaborative training data set is the above-mentioned sample data, and the collaborative training data set also includes the true value corresponding to each sample data.

[0065] Step 403: Obtain the prediction value corresponding to the sample data according to the sample data and the target network model deployed in the storage and computing integrated chip.

[0066] Step 404: Update the target network model deployed in the storage-computing integrated chip according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0067] In some embodiments of the present application, this step is implemented as follows: when the above-mentioned difference is greater than or equal to a preset value, the target network model deployed in the storage and computing integrated chip is updated, and the step of obtaining the sample data in the training data set and the true value corresponding to the sample data is returned.

[0068] It can be seen that by updating the target network model deployed in the storage and computing integrated chip and returning to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data, the iterative update of the target network model can be achieved, which is beneficial to improve the data processing accuracy of the target network model.

[0069] In some embodiments of the present application, when the above difference is less than a preset value, the target network model deployed in the storage-computing integrated chip is stopped from being updated, and the target network model deployed in the storage-computing integrated chip is determined as the trained target network model. It can be understood that when the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data is small, it can be considered that the data processing accuracy of the target network model is high, that is, the trained target network model has a high data processing accuracy.

[0070] In practical applications, steps 401 to 404 can be implemented based on a processor, and the processor can be at least one of an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a CPU, a controller, a microcontroller, and a microprocessor.

[0071] It can be seen that in the embodiment of the present application, there is no need to analyze the error source of the storage and computing chip. Instead, the target network model can be collaboratively trained through electronic equipment and the storage and computing chip, thereby improving the data processing accuracy of the target network model, which is beneficial for making the output result of the target network model closer to the true value, and further, it is beneficial to learn the calculation error of the target network model in the storage and computing chip, reducing the complexity of the error compensation process in the storage and computing chip.

[0072] In some embodiments of the present application, when the sample data is floating point data, the sample data is quantized to obtain quantized sample data. Figure 6The electronic device can obtain the sample data and the true value corresponding to the sample data, and can also send the quantized sample data to the storage and computing integrated chip. After the storage and computing integrated chip processes the quantized sample data, it can obtain the model output result; after the storage and computing integrated chip sends the model output result to the electronic device, the electronic device can perform dequantization processing on the model output result to obtain the predicted value corresponding to the sample data.

[0073] Exemplarily, after receiving the quantized sample data (integer data), the storage-computing integrated chip can participate in the simulation calculation in order according to the control flow scheduling, A / D converter and computing array, and obtain the model output result D1 (integer data) through each layer of calculation of the storage-computing chip. The storage-computing integrated chip can transmit the model output result D1 to the electronic device through the UART interface, and the electronic device can perform dequantization processing on the model output result D1 to obtain FP32 precision data D2. At the same time, the electronic device needs to find the true value of the corresponding serial number.

[0074] It can be seen that the electronic device can obtain the predicted value corresponding to the sample data by dequantizing the model output result, and the model output result is obtained after the storage and computing integrated chip processes the quantized sample data. Therefore, the predicted value corresponding to the sample data can accurately reflect the calculation accuracy of the storage and computing integrated chip to a certain extent, which is conducive to further training the target network model deployed in the storage and computing integrated chip according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0075] In some embodiments of the present application, when the above-mentioned difference is greater than or equal to a preset value, the floating-point model is updated according to the difference to obtain an updated floating-point model; the updated floating-point model is quantized to obtain an updated target network model; the updated target network model is sent to the storage and computing integrated chip, so that the storage and computing integrated chip updates the deployed target network model.

[0076] Here, the preset value can be recorded as L1, and the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data can be represented by the loss function of the target network model. The learning rate of the target network model can be adjusted according to the loss value of the loss function of the target network model. At the same time, it is determined whether the above loss value is less than the preset value L1. When the above loss value is less than the preset value L1, the training process of the target network model can be ended, and the FP32 model M1 and the quantized model M2 currently existing in the electronic device can be saved. When the above loss value is greater than or equal to the preset value L1, back propagation can be performed according to the above difference, so as to update the weight of the FP32 precision model M1 and obtain the updated model M1. Then, the updated model M1 can be quantized to obtain the updated model M2, and the weight data and control flow of the updated model M2 can be resent to the storage-computing integrated chip, so as to update the model M2 deployed in the storage-computing integrated chip.

[0077] It can be seen that by updating the target network model deployed in the storage and computing integrated chip and returning to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data, the iterative update of the target network model can be achieved, which is beneficial to improve the data processing accuracy of the target network model.

[0078] In some embodiments of the present application, the training data set may include multiple sample data. Accordingly, according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, the process of updating the target network model deployed in the storage and computing integrated chip includes:

[0079] Obtain each sample data in the training data set in turn by traversing;

[0080] For each sample data obtained, according to the difference between the true value corresponding to each sample data and the predicted value corresponding to each sample data, the target network model deployed in the storage-computing integrated chip is updated;

[0081] After traversing each sample data in the training data set each time, the value of the preset number of loops variable is increased by 1. When the value of the preset number of loops variable is less than the preset maximum number of loops, the target network model deployed in the storage and computing integrated chip is updated, and the process returns to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data.

[0082] In some embodiments, a maximum number of cycles N may also be preset. maxand the batch size of the data set to specify the number of data cycles for collaborative training and the batch size of each cycle. The preset number of cycles variable is recorded as N, and the initial value of N is 0. After updating the target network model deployed in the storage and computing integrated chip for each sample data in the training data set, the value of N can be increased by 1. If N is less than the preset maximum number of cycles N max , then it is possible to return to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data, thereby re-traversing and sequentially obtaining each sample data in the training data set.

[0083] In some embodiments, when the value of the preset number of loops variable is equal to the preset maximum number of loops, the target network model deployed in the storage-computing integrated chip can be determined as the trained target network model. At this time, the training process of the target network model can be terminated, and the FP32 model M1 and the quantized model M2 currently existing in the electronic device can be saved.

[0084] Figure 7 Flow chart of a collaborative training method for a model applied to a storage-computing integrated chip according to an embodiment of the present application, such as Figure 7 As shown, the process may include:

[0085] Step 701: Deploy the target network model.

[0086] Step 702: Update the deployed target network model by interacting with the electronic device.

[0087] Here, the electronic device is used to obtain sample data in a training data set and the true value corresponding to the sample data; obtain the predicted value corresponding to the sample data based on the sample data and the target network model deployed in the storage and computing integrated chip; and update the target network model deployed in the storage and computing integrated chip based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0088] The implementation of step 701 and step 702 has been described in the above embodiments.

[0089] It can be seen that in the embodiment of the present application, there is no need to analyze the error source of the storage and computing chip. Instead, the target network model can be collaboratively trained through electronic equipment and the storage and computing chip, thereby improving the data processing accuracy of the target network model, which is beneficial for making the output result of the target network model closer to the true value, and further, it is beneficial to learn the calculation error of the target network model in the storage and computing chip, reducing the complexity of the error compensation process in the storage and computing chip.

[0090] In some embodiments of the present application, the process of deploying a target network model by a storage-computing integrated chip includes: receiving weight data and a control flow in the target network model sent by an electronic device, wherein the control flow is used to characterize the calculation method for the weight data in the storage-computing integrated chip; and deploying the weight data and the control flow into the storage-computing integrated chip.

[0091] Exemplarily, the weight data and the control flow may be deployed to a preset fixed position of the storage-computing integrated chip. For example, the preset fixed position is Figure 8 The pattern-filled area 1 and area 2 are shown in FIG. It can be seen that by deploying the weight data and the control flow to the preset fixed position of the storage-computing integrated chip, the arrangement position of the weight data and the control flow can be kept unchanged, so that the AD converter involved in the calculation can be kept unchanged.

[0092] In summary, the embodiments of the present application propose a collaborative training scheme between electronic devices and analog storage and computing terminals, so that error compensation can be performed on analog storage and computing chips. In the embodiments of the present application, the A / D converter, computing array and current accumulator involved in the calculation can be determined by fixed arrangement positions, and the errors can be learned using the learning ability of deep learning, and the information can be stored in the weights of the model.

[0093] The embodiment of the present application can use the learning ability of deep learning to perform collaborative training on electronic devices and storage-computing integrated chips, so as to learn the errors of analog storage-computing integrated chips. The error compensation scheme of the embodiment of the present application is a collaborative compensation scheme integrating software and hardware. It does not need to analyze and record the source of the error. It only needs to determine the hardware and then hand it over to collaborative training to achieve end-to-end error learning. The error compensation scheme of the embodiment of the present application is a semi-automatic error compensation method. Compared with the original error compensation method of the storage-computing integrated chip, it has the advantages of shorter development cycle and easier algorithm deployment, which can greatly shorten the algorithm model adaptation development cycle of the storage-computing integrated chip.

[0094] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0095] Fig. 9 Schematic diagram of the structure of the collaborative training device for the model of the electronic device according to the embodiment of the present application, such as Fig. 9 As shown, the device comprises:

[0096] The first deployment module 901 is used to deploy the target network model to the storage and computing integrated chip;

[0097] An acquisition module 902 is used to acquire sample data in a training data set and true values ​​corresponding to the sample data;

[0098] The first processing module 903 is used to obtain the predicted value corresponding to the sample data according to the sample data and the target network model deployed in the storage and computing integrated chip; and update the target network model deployed in the storage and computing integrated chip according to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0099] In some embodiments, the first processing module 903 is used to update the target network model deployed in the storage-computing integrated chip according to the difference between the real value corresponding to the sample data and the predicted value corresponding to the sample data, including:

[0100] When the difference is greater than or equal to the preset value, the target network model deployed in the integrated storage and computing chip is updated, and the process returns to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data.

[0101] In some embodiments, the first processing module 903 is also used to stop updating the target network model deployed in the storage and computing integrated chip when the difference is less than a preset value, and determine the target network model deployed in the storage and computing integrated chip as the trained target network model.

[0102] In some embodiments, the first deployment module 901 is further used to deploy a floating-point model before deploying the target network model into the storage-computing integrated chip, and quantize the floating-point model to obtain the target network model;

[0103] The first processing module 903 is used to obtain a prediction value corresponding to the sample data according to the sample data and the target network model deployed in the storage-computing integrated chip, including:

[0104] When the sample data is floating point data, quantizing the sample data to obtain quantized sample data;

[0105] Sending the quantized sample data to the storage-computing integrated chip, so that the storage-computing integrated chip processes the quantized sample data according to the target network model to obtain a model output result;

[0106] Receive the model output result sent by the storage and computing integrated chip, perform inverse quantization on the model output result, and obtain the predicted value corresponding to the sample data.

[0107] In some embodiments, the first processing module 903 is used to update the target network model deployed in the storage-computing integrated chip according to the difference between the real value corresponding to the sample data and the predicted value corresponding to the sample data, including:

[0108] When the difference is greater than or equal to a preset value, updating the floating-point model according to the difference to obtain an updated floating-point model;

[0109] Quantizing the updated floating-point model to obtain an updated target network model;

[0110] The updated target network model is sent to the integrated storage and computing chip, so that the integrated storage and computing chip updates the deployed target network model.

[0111] In some embodiments, the training data set includes a plurality of sample data; the first processing module 903 is used to update the target network model deployed in the storage-computing integrated chip according to the difference between the real value corresponding to the sample data and the predicted value corresponding to the sample data, including:

[0112] Acquire each sample data in the training data set in sequence by traversing;

[0113] For each acquired sample data, according to the difference between the real value corresponding to each sample data and the predicted value corresponding to each sample data, updating the target network model deployed in the storage-computing integrated chip;

[0114] After traversing each sample data in the training data set each time, the value of the preset number of loops variable is increased by 1. When the value of the preset number of loops variable is less than the preset maximum number of loops, the target network model deployed in the storage and computing integrated chip is updated, and the process returns to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data.

[0115] In some embodiments, the first processing module 903 is also used to determine the target network model deployed in the storage and computing integrated chip as a trained target network model when the value of the preset number of loops variable is equal to a preset maximum number of loops.

[0116] In some embodiments, the first deployment module 901 is used to deploy the target network model to the storage and computing integrated chip, including: determining the weight data and control flow in the target network model, the control flow is used to characterize the calculation method for the weight data in the storage and computing integrated chip; sending the weight data and the control flow to the storage and computing integrated chip.

[0117] In practical applications, the first deployment module 901, the acquisition module 902 and the first processing module 903 can be implemented based on a processor and a communication device.

[0118] Fig.10 Schematic diagram of the structure of the collaborative training device of the model applied to the storage and computing integrated chip in the embodiment of the present application, such as Fig.10 As shown, the device comprises:

[0119] The second deployment module 1001 is used to deploy the target network model;

[0120] The second processing module 1002 is used to update the deployed target network model by interacting with an electronic device; wherein the electronic device is used to obtain sample data in a training data set and true values ​​corresponding to the sample data; obtain predicted values ​​corresponding to the sample data based on the sample data and the target network model deployed in the storage-computing integrated chip; and update the target network model deployed in the storage-computing integrated chip based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

[0121] In some embodiments, the second deployment module 1001 is specifically used to receive the weight data and control flow in the target network model sent by the electronic device, and deploy the weight data and the control flow to the storage and computing integrated chip; wherein the control flow is used to characterize the calculation method for the weight data in the storage and computing integrated chip.

[0122] In some embodiments, the second deployment module 1001 is used to deploy the weight data and the control flow into the storage and computing integrated chip, including: deploying the weight data and the control flow to a preset fixed position of the storage and computing integrated chip.

[0123] In practical applications, the second deployment module 1001 and the second processing module 1002 can be implemented based on a processor and a communication device.

[0124] It should be noted that the description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0125] It should be noted that in the embodiments of the present application, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium, including a number of instructions to enable a computer device (which can be a terminal, a server, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0126] Correspondingly, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and the computer executable instructions are used to implement the collaborative training method of any model provided in the embodiment of the present application.

[0127] Correspondingly, an embodiment of the present application further provides a computer storage medium, on which computer executable instructions are stored, and the computer executable instructions are used to implement the collaborative training method of any one of the models provided in the above embodiments.

[0128] An embodiment of the present application also provides an electronic device. Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig.11 As shown, the electronic device 110 may include:

[0129] A memory 111, used for storing executable instructions;

[0130] The processor 112 is used to implement any of the above-mentioned collaborative training methods for models applied to electronic devices when executing executable instructions stored in the memory 111.

[0131] The processor 112 may be at least one of an ASIC, a DSP, a DSPD, a PLD, a FPGA, a CPU, a controller, a microcontroller, and a microprocessor.

[0132] The above-mentioned computer-readable storage medium and memory 112 can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory (Flash Memory), a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and other memories; it can also be various terminals including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0133] An embodiment of the present application also provides a storage-computing integrated chip, which is used to execute any of the above-mentioned collaborative training methods of the model applied to the storage-computing integrated chip by running a computer program.

[0134] In some embodiments, the functions or modules included in the device provided in the embodiments of the present application can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0135] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

[0136] The methods disclosed in the various method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0137] The features disclosed in the various product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0138] The features disclosed in the various method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0139] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0140] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A collaborative training method for a model, characterized in that: Applied in an electronic device, the method comprises: Deploy the target network model to the storage-computing integrated chip; Obtaining sample data in a training data set and true values ​​corresponding to the sample data; Obtaining a prediction value corresponding to the sample data according to the sample data and the target network model deployed in the storage-computing integrated chip; According to the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, the target network model deployed in the storage and computing integrated chip is updated.

2. The method according to claim 1, characterized in that The updating of the target network model deployed in the storage-computing integrated chip according to the difference between the real value corresponding to the sample data and the predicted value corresponding to the sample data includes: When the difference is greater than or equal to the preset value, the target network model deployed in the integrated storage and computing chip is updated, and the process returns to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data.

3. The method according to claim 1, characterized in that The method further comprises: When the difference is smaller than a preset value, the updating of the target network model deployed in the storage-computing integrated chip is stopped, and the target network model deployed in the storage-computing integrated chip is determined as the trained target network model.

4. The method according to claim 1, characterized in that: Before deploying the target network model into the storage-computing integrated chip, the method further includes: deploying a floating-point model, and quantizing the floating-point model to obtain the target network model; The obtaining, according to the sample data and the target network model deployed in the storage-computing integrated chip, a predicted value corresponding to the sample data includes: When the sample data is floating point data, quantizing the sample data to obtain quantized sample data; Sending the quantized sample data to the storage-computing integrated chip, so that the storage-computing integrated chip processes the quantized sample data according to the target network model to obtain a model output result; Receive the model output result sent by the storage and computing integrated chip, perform inverse quantization on the model output result, and obtain the predicted value corresponding to the sample data.

5. The method according to claim 4, characterized in that The updating of the target network model deployed in the storage-computing integrated chip according to the difference between the real value corresponding to the sample data and the predicted value corresponding to the sample data includes: When the difference is greater than or equal to a preset value, updating the floating-point model according to the difference to obtain an updated floating-point model; Quantizing the updated floating-point model to obtain an updated target network model; The updated target network model is sent to the integrated storage and computing chip, so that the integrated storage and computing chip updates the deployed target network model.

6. The method according to claim 1, characterized in that The training data set includes a plurality of sample data; The updating of the target network model deployed in the storage-computing integrated chip according to the difference between the real value corresponding to the sample data and the predicted value corresponding to the sample data includes: Acquire each sample data in the training data set in sequence by traversing; For each acquired sample data, according to the difference between the real value corresponding to each sample data and the predicted value corresponding to each sample data, updating the target network model deployed in the storage-computing integrated chip; After traversing each sample data in the training data set each time, the value of the preset number of loops variable is increased by 1. When the value of the preset number of loops variable is less than the preset maximum number of loops, the target network model deployed in the storage and computing integrated chip is updated, and the process returns to the step of obtaining the sample data in the training data set and the true value corresponding to the sample data.

7. The method according to claim 6, characterized in that The method further comprises: When the value of the preset number of loops variable is equal to the preset maximum number of loops, the target network model deployed in the storage-computing integrated chip is determined as the trained target network model.

8. The method according to any one of claims 1 to 7, characterized in that: The step of deploying the target network model to the storage-computing integrated chip includes: Determine weight data and control flow in the target network model, wherein the control flow is used to characterize a calculation method for the weight data in the storage-computing integrated chip; The weight data and the control flow are sent to the storage-computing integrated chip.

9. A collaborative training method for a model, characterized in that: Applied to a storage-computing integrated chip, the method includes: Deploy the target network model; The deployed target network model is updated by interacting with an electronic device; wherein the electronic device is used to obtain sample data in a training data set and true values ​​corresponding to the sample data; based on the sample data and the target network model deployed in the storage-computing integrated chip, a predicted value corresponding to the sample data is obtained; based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data, the target network model deployed in the storage-computing integrated chip is updated.

10. The method according to claim 9, characterized in that The deployment target network model includes: Receiving weight data and a control flow in the target network model sent by the electronic device, wherein the control flow is used to characterize a calculation method for the weight data in the storage-computing integrated chip; The weight data and the control flow are deployed into the storage-computing integrated chip.

11. The method according to claim 10, characterized in that Deploying the weight data and the control flow into the integrated storage and computing chip includes: deploying the weight data and the control flow to a preset fixed position of the integrated storage and computing chip.

12. A collaborative training device for a model, characterized in that: Applied in electronic equipment, the device comprises: The first deployment module is used to deploy the target network model into the storage and computing integrated chip; An acquisition module is used to acquire sample data in a training data set and true values ​​corresponding to the sample data; The first processing module is used to obtain the predicted value corresponding to the sample data based on the sample data and the target network model deployed in the storage and computing integrated chip; and update the target network model deployed in the storage and computing integrated chip based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

13. A collaborative training device for a model, characterized in that: Applied to a storage-computing integrated chip, the device comprises: The second deployment module is used to deploy the target network model; The second processing module is used to update the deployed target network model by interacting with an electronic device; wherein the electronic device is used to obtain sample data in a training data set and true values ​​corresponding to the sample data; obtain predicted values ​​corresponding to the sample data based on the sample data and the target network model deployed in the storage-computing integrated chip; and update the target network model deployed in the storage-computing integrated chip based on the difference between the true value corresponding to the sample data and the predicted value corresponding to the sample data.

14. An electronic device, characterized in that: The electronic device comprises a processor and a memory for storing a computer program that can be run on the processor; wherein, The processor is configured to run the computer program to perform the method according to any one of claims 1 to 8.

15. A storage and computing integrated chip, characterized in that: The integrated storage and computing chip is used to execute the method described in any one of claims 9 to 11 by running a computer program.

16. A computer storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

17. A computer program product comprising a computer program, characterized in that The computer program implements the method according to any one of claims 1 to 11 when executed by a processor.

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