Shift register unit and display panel

Abstract

The invention relates to the technical field of display, and provides a shift register unit and a display panel. In the shift register unit, an input module is used for pulling up a first control node by using a signal of a first voltage end in response to a signal of an input end; the control module is coupled with a second voltage end, the first node, the first control node and the second control node and receives a second level signal; the control module is used for pulling down the second control node by using a second level signal in response to the signal of the first control node or pulling up the second control node by using the signal of the second voltage end in response to the signal of the second voltage end, so that the signal of the second control node is opposite to the signal of the first control node; the input protection module is coupled to the first node and the second node, and the input protection module can switch on in response to a voltage difference between the first node and the second node to switch off a switch-on path between the first control node and the first voltage end. The invention provides a novel input protection module and control module architecture which can reduce leakage current.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit and a display panel. Background Art

[0002] In some display products, light-emitting devices are required to emit light. The light-emitting current required by the light-emitting devices is provided by driving transistors. In order to ensure the uniformity of product light emission, it is necessary to increase the consistency of device characteristics. Usually, external compensation is performed through a GOA (GateDriver On Array, array substrate row drive) circuit to increase the consistency of the device. The existing GOA circuit is not conducive to reducing the product border. Summary of the invention

[0003] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a shift register unit and a display panel.

[0004] According to one aspect of the present disclosure, a shift register unit is provided, including: an input module, coupled to a first voltage terminal, an input terminal, a first control node, and a second node, the input module being configured to write a signal at the first voltage terminal to the first control node in response to a signal at the input terminal; a control module, coupled to a second voltage terminal, a first node, the first control node, the second control node and receiving a second level signal, the control module being configured to write the second level signal to the second control node in response to a signal at the first control node or to write a signal at the second voltage terminal to the second control node in response to a signal at the second voltage terminal; an input protection module, coupled to the first node and the second node, the input protection module being configured to be turned on in response to a voltage difference between the first node and the second node.

[0005] In an exemplary embodiment of the present disclosure, the amplitude of the voltage signal at the first voltage terminal is greater than the amplitude of the voltage signal at the second voltage terminal.

[0006] In an exemplary embodiment of the present disclosure, the input module includes: a first input transistor, a first pole coupled to a first voltage terminal, a second pole coupled to a second node, and a third pole coupled to an input terminal, the first input transistor being configured to write a signal of the first voltage terminal to the second node in response to a signal of the input terminal; a second input transistor, a first pole coupled to the second node, a second pole coupled to the first control node, and a third pole coupled to the input terminal, the second input transistor being configured to write a signal of the second node to the first control node in response to a signal of the input terminal; wherein the first input transistor has the same polarity as the second input transistor.

[0007] In an exemplary embodiment of the present disclosure, the input protection module includes: a first protection transistor, a first electrode and a third electrode are both coupled to the first node, a second electrode is coupled to the second node, and the first protection transistor is configured to be turned on in response to a voltage difference between the first node and the second node; wherein the first protection transistor has the same polarity as the first input transistor and the second input transistor.

[0008] In an exemplary embodiment of the present disclosure, the input protection module includes: a first protection transistor, a first pole and a third pole coupled to the first node; a second protection transistor, a first pole and a third pole coupled to the second pole of the first protection transistor, and the second pole coupled to the second node; wherein the first protection transistor and the second protection transistor have the same polarity as the first input transistor and the second input transistor.

[0009] In an exemplary embodiment of the present disclosure, the control module includes: a first control unit, coupled to the second voltage terminal, the first node and the third node, the first control unit being configured to write the signal of the second voltage terminal into the first node and the third node in response to the signal of the second voltage terminal; a second control unit, coupled to the third node, the second voltage terminal, the second control node and the first control node and receiving a second level signal and a third level signal respectively, the second control unit being configured to write the third level signal into the third node in response to the signal of the first control node or being configured to write the signal of the second voltage terminal into the second control node in response to the signal of the third node so that the polarity of the second control node is opposite to that of the first control node.

[0010] In an exemplary embodiment of the present disclosure, the first control unit includes: a first control transistor, a first electrode and a third electrode are both coupled to the second voltage terminal, and the second electrode is coupled to the first node; a second control transistor, a first electrode is coupled to the first node, a second electrode is coupled to the third node, and the third electrode is coupled to the first node or the second voltage terminal; the second control unit includes: a third control transistor, a first electrode is coupled to the third node, a second electrode receives a third level signal, and a third electrode is coupled to the first control node; a sixth transistor, a first electrode is coupled to the second voltage terminal, a second electrode is coupled to the second control node, and a third electrode is coupled to the third node; a seventh transistor, a first electrode is coupled to the second control node, a second electrode receives the second level signal, and a third electrode is coupled to the first control node; wherein the polarities of the first control transistor, the second control transistor, the third control transistor, the sixth transistor and the seventh transistor are the same.

[0011] In an exemplary embodiment of the present disclosure, the first control unit includes: a first control transistor, a first electrode and a third electrode are both coupled to the second voltage terminal, and the second electrode is coupled to the first node; a second control transistor, a first electrode is coupled to the first node, a second electrode is coupled to the third node, and the third electrode is coupled to the first node or the second voltage terminal; the second control unit includes: a third control transistor, a first electrode is coupled to the third node, a second electrode is coupled to the second control node, and a third electrode is coupled to the first control node; a fourth control transistor, a first electrode is coupled to the second control node, a second electrode receives the third level signal, and a third electrode is coupled to the first control node; a sixth transistor, a first electrode is coupled to the second voltage terminal, a second electrode is coupled to the second control node, and a third electrode is coupled to the third node; wherein the polarities of the first control transistor, the second control transistor, the third control transistor, the fourth control transistor and the sixth transistor are the same.

[0012] In an exemplary embodiment of the present disclosure, the shift register unit further includes: a first reset module, coupled to the first control node, the first reset signal terminal, the fourth node and receiving the second level signal, the first reset module being configured to write the second level signal to the first control node in response to the signal of the first reset signal terminal; a reset protection module, coupled to the first voltage terminal, the first control node and the fourth node, the reset protection module being configured to write the signal of the first voltage terminal to the fourth node in response to the signal of the first control node; a pull-down module, coupled to the first control node, the second control node and the fourth node and receiving the second level signal, the pull-down module being configured to write the second level signal to the first control node and the fourth node in response to the signal of the second control node to pull down the first control node and the fourth node; a second reset module, coupled to the first control node, the fourth node, the second reset signal terminal and receiving the second level signal, the second reset module being configured to write the second level signal to the first control node and the fourth node in response to the signal of the second reset signal terminal to reset the first control node and the fourth node.

[0013] In an exemplary embodiment of the present disclosure, the first reset module includes: a first reset transistor, a first electrode coupled to the first control node, a second electrode coupled to the fourth node, and a third electrode coupled to the first reset signal terminal; a second reset transistor, a first electrode coupled to the fourth node, a second electrode receiving the second level signal, and a third electrode coupled to the first reset signal terminal; the reset protection module includes: a first reset protection transistor, a first electrode coupled to the first voltage terminal, and a third electrode coupled to the first control node; a second reset protection transistor, a first electrode coupled to the second electrode of the first reset protection transistor, a second electrode coupled to the fourth node, and a third electrode coupled to the first control node; wherein the first reset transistor, the second reset transistor The transistor, the first reset protection transistor and the second reset protection transistor have the same polarity; the pull-down module includes: a first pull-down transistor, a first pole coupled to the first control node, a second pole coupled to the fourth node, and a third pole coupled to the second control node; a second pull-down transistor, a first pole coupled to the fourth node, a second pole receiving the second level signal, and a third pole coupled to the second control node; the second reset module includes: a third reset transistor, a first pole coupled to the first control node, a second pole coupled to the fourth node, and a third pole coupled to the second reset signal terminal; a fourth reset transistor, a first pole coupled to the fourth node, a second pole receiving the second level signal, and a third pole coupled to the second reset signal terminal.

[0014] In an exemplary embodiment of the present disclosure, the shift register unit also includes: an initial control module, coupled to the second control node, the input end and receiving the second level signal, the initial control module being configured to write the second level signal to the second control node in response to the signal at the input end to pull down the second control node using the second level signal.

[0015] In an exemplary embodiment of the present disclosure, the initial control module includes: a tenth transistor, a first electrode coupled to the second control node, a second electrode receiving the second level signal, and a third electrode coupled to the input terminal.

[0016] In an exemplary embodiment of the present disclosure, during the first control node setting phase and the first control node coupling phase of the shift register unit, the input protection module is turned off; during other phases of the shift register unit, the input module protection module is turned on.

[0017] In an exemplary embodiment of the present disclosure, the input protection module includes an N-type transistor; when the first control node is at a high level, the potential difference between the first node and the first control node is less than the threshold voltage of the transistor in the input protection module; when the first control node is at a low level, the voltage difference between the first node and the first control node is greater than the threshold voltage of the transistor in the input protection module.

[0018] In an exemplary embodiment of the present disclosure, the shift register unit also includes: a cascade control module, which is coupled to a first clock signal line, a cascade signal output terminal, the first control node, the second control node and receives the second level signal, and the cascade control module is configured to write the signal of the first clock signal line into the cascade signal output terminal in response to the signal of the first control node to output a cascade control signal; a plurality of gate control modules, wherein one gate control module is coupled to a gate signal output terminal, a second clock signal line and the first control node, the second control node and receives the first level signal, and the output module is configured to write the signal on the corresponding second clock signal line into the corresponding gate signal output terminal in response to the signal of the first control node to output a gate control signal.

[0019] In an exemplary embodiment of the present disclosure, the cascade control module includes: an eleventh transistor, a first pole coupled to the first clock signal line, a second pole coupled to the cascade signal output terminal, and a third pole coupled to the first control node; a twelfth transistor, a first pole coupled to the cascade signal output terminal, a second pole receiving the second level signal, and a third pole coupled to the second control node; a first capacitor, a first pole coupled to the first control node, and a second pole coupled to the cascade signal output terminal; the gate control module includes: a first output transistor, a first pole coupled to the second clock signal line, a second pole coupled to the corresponding gate signal output terminal, and a third pole coupled to the first control node; a second output transistor, a first pole coupled to the corresponding gate signal output terminal, a second pole receiving the first level signal, and a third pole coupled to the second control node; an output capacitor, a first pole coupled to the first control node, and a second pole coupled to the corresponding gate signal output terminal.

[0020] According to a second aspect of the present disclosure, there is further provided a display panel, comprising a gate driving circuit, wherein the gate driving circuit comprises the shift register unit described in any embodiment of the present disclosure.

[0021] The shift register unit provided by the present disclosure has an input protection module coupled between a first node and a second node, so that in the first control node coupling stage of the shift register unit, the input protection module is turned on under the action of the voltage difference between the first node and the second node, thereby blocking the leakage of the first voltage end through the input module. Compared with the prior art, the leakage current of the shift register unit in the first control node coupling stage can be significantly reduced.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are configured to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0024] Figure 1 Schematic diagram of driving signals for the first three rows of pixels in the related art;

[0025] Figure 2 A GOA circuit diagram for realizing random frame shifting adopted in the related art;

[0026] Figure 3 is a structural block diagram of a shift register unit according to an embodiment of the present disclosure;

[0027] Figure 4 Based on Figure 2 The timing diagram of each node in the GOA circuit shown;

[0028] Figure 5 is a structural schematic diagram of a shift register unit according to another embodiment of the present disclosure;

[0029] Figure 6 is a structural schematic diagram of a shift register unit according to another embodiment of the present disclosure;

[0030] Figure 7 is a structural schematic diagram of a shift register unit according to another embodiment of the present disclosure;

[0031] Figure 8 Schematic diagram of the structure of a shift register unit according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0033] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0034] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0035] Active matrix organic light emitting diode (AMOLED) is expected to replace LCD and become the mainstream choice for the next generation of displays due to its high contrast, wide viewing angle and fast response speed. In the pixel circuit design of OLED products, generally, considering the process limitations, all pixel circuits are designed using N-channel transistors. For example, in the design of the 54.5-inch AMOLED panel, a 3T1C circuit is used. However, OLED products themselves require EL devices to emit light, and the required light-emitting current needs to be provided by the driving transistor. Therefore, in order to ensure the uniformity of the product's light emission, the consistency of the device characteristics must be increased. Generally, an external compensation method is used. The external compensation Gate signal is composed of a combination of "row shift" + "frame shift" signals, such as Figure 1 As shown, Figure 1 1 shows the driving signals of the first row of pixels, the second row of pixels and the third row of pixels, Figure 1In the compensation method of sequential frame shift, the signal of the blanking time of a frame is a frame shift signal. The frame shift is divided into sequential frame shift and random frame shift. In the compensation method of sequential frame shift, the gate drive circuit can output drive signals to pixels row by row to compensate the drive transistors of the pixels. In the compensation method of random frame shift, the gate drive circuit can output compensation drive signals to any row of pixels in any frame to compensate the drive transistors of the pixels. Among them, the compensation method of sequential frame shift is prone to produce compensation horizontal stripes, resulting in poor display.

[0036] Figure 2 This is a GOA circuit diagram for realizing random frame shifting used in the related art. As shown in the dotted box in the figure, the circuit needs to add the twenty-fifth transistor and the twenty-sixth transistor to protect the twenty-first transistor and the twenty-second transistor to reduce leakage current and power consumption, and improve the reliability of the circuit. However, this design requires additional high voltage and two transistors. The circuit structure is not simple enough, and the additional high voltage wiring and transistors will take up more space, which is not conducive to the realization of a narrow frame of the product.

[0037] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0038] Figure 3 : is a structural block diagram of a shift register unit according to an embodiment of the present disclosure, the shift register unit GOA can be configured in a display panel, for example, the display panel can include a gate drive circuit, the gate drive circuit can include a plurality of cascaded shift register units, the gate drive circuit outputs a gate control signal to a pixel drive circuit of a display area through each shift register unit to control the sub-pixels of the display area to perform row scanning. Figure 3As shown, the shift register unit GOA may include an input module 100, a control module 200 and an input protection module 120, wherein the input module 100 is coupled to a first voltage terminal VDD1, an input terminal Input, a first control node Q1 and a second node N2, and the input module 100 may be configured to write a signal of the first voltage terminal VDD1 to the first control node Q1 in response to a signal of the input terminal Input; the control module 200 is coupled to a second voltage terminal VDD2, a first node N1, a first control node Q1 and a second control node Q2 and receives a second level signal VGL2, and the control module 200 may be configured to write a second level signal VGL2 to the second control node Q2 in response to a signal of the first control node Q1 Or in response to the signal of the second voltage terminal VDD2, the signal of the second voltage terminal VDD2 is written into the second control node Q2 so that the signal of the second control node Q2 is inverted with the signal of the first control node Q1; the input protection module 120 is coupled to the first node N1 and the second node N2, and the input protection module 120 can be configured to be turned on in response to the voltage difference between the first node N1 and the second node N2 and to disconnect the conduction path between the first control node Q1 and the first voltage terminal VDD1; wherein the level signal of the first voltage terminal VDD1 has the same polarity as the level signal of the second voltage terminal VDD2 and is opposite in polarity to the second level signal VGL2, and the amplitude of the level signal of the first voltage terminal VDD1 is greater than the amplitude of the level signal of the second voltage terminal VDD2. The shift register unit GOA provided in the present disclosure has an input protection module 120 coupled between the first node N1 and the second node N2, so that in the first control node holding stage after the shift register unit GOA outputs, the input protection module 120 is turned on under the action of the voltage difference between the first node N1 and the second node N2, thereby blocking the first voltage terminal VDD1 from leaking through the input module 100. Compared with the prior art, the leakage current of the shift register unit GOA in the first control node holding stage can be significantly reduced.

[0039] In the shift register unit GOA disclosed in the present invention, the control module 200 can use the second level signal VGL2 or the signal of the second voltage terminal VDD2 to control the potential of the second control node Q2 to be opposite to the potential polarity of the first control node Q1. For example, when the first control node Q1 is at a high level, the control module 200 can control the second control node Q2 to be at a low level; when the first control node Q1 is at a low level, the control module 200 can control the second control node Q2 to be at a high level.

[0040] The first voltage terminal VDD1 and the second voltage terminal VDD2 of the present disclosure can both output high level, and the second level signal VGL2 can be low level, so that the high level signal of the first voltage terminal VDD1 has the same polarity as the high level signal of the second voltage terminal VDD2 and is opposite to the second level signal VGL2.

[0041] The signal of the first voltage terminal VDD1 is used as the input signal of the shift register unit GOA, and its signal amplitude is greater than the signal amplitude of the second voltage terminal VDD2. It can be known that in a frame of data, after the shift register unit GOA outputs the gate control signal Gate and the cascade control signal CR, it will enter the first control node holding stage. In the first control node holding stage, the input protection module 120 is turned on under the voltage difference between the first node N1 and the second node N2. The input protection module 120 is turned on to disconnect the leakage path between the first voltage terminal VDD1 and the input module 100, that is, the first voltage terminal VDD1 cannot leak through the input module 100, thereby reducing the leakage current of the shift register unit GOA in the first control node holding stage. At the same time, in the first control node setting stage and the first control node coupling stage of the shift register unit GOA, the voltage difference between the first node N1 and the second node N2 cannot turn on the input protection module 120, that is, the input protection module 120 is turned off, so the input protection module 120 will not affect the normal operation of the input module 100.

[0042] The first control node Q1 described in the present disclosure may be a pull-up node, and the second control node Q2 may be a pull-down node. It should be understood that the "pull-up" described in the present disclosure refers to pulling the potential at the corresponding circuit node to a high level, and the "pull-down" described refers to pulling the potential at the corresponding circuit node to a low level. It is understandable that the above-mentioned "pull-up" and "pull-down" can both be achieved through the directional movement of charges, and therefore can be specifically achieved by electronic components or combinations thereof with corresponding functions, and the present disclosure does not limit this.

[0043] Figure 4 Based on Figure 2 The timing diagram of each node in the GOA circuit is shown in FIG. Figure 4As shown, the operation phase of the shift register unit GOA disclosed in the present invention may include a first control node setting phase T1, a first control node coupling phase T2 and a first control node holding phase T3. In the first control node setting phase T1, the input terminal Input of the shift register unit GOA receives a conduction level signal, the first control node Q1 is set to a high level, and the second control node Q2 is set to a low level; in the first control node coupling phase T2, the shift register unit GOA uses the conduction level signal of the clock signal line to output a conduction level gate control signal Gate and a cascade control signal CR, that is, to perform shift output, at which time the voltage at the output terminal is coupled to the first control node Q1, thereby further raising the potential of the first control node Q1; in the first control node holding phase T3, the shift register unit GOA outputs a non-conduction level signal, that is, no longer outputs the gate control signal Gate and the cascade control signal CR, and the first control node Q1 maintains a non-conduction level. It should be understood that a certain signal terminal A described in the present disclosure receiving or outputting a conduction level signal can be understood as the level signal being able to conduct a functional module coupled to the signal terminal A. Similarly, a certain signal terminal A receiving or outputting a non-conduction level can be understood as the level signal being able to shut down a functional module coupled to the signal terminal A.

[0044] In the first control node setting phase T1 and the first control node coupling phase T2 of the shift register unit GOA disclosed in the present invention, the input protection module 120 is turned off; and in the first control node holding phase T3, the input protection module 120 is turned on. Specifically, in the first control node setting phase T1 and the first control node coupling phase T2, the input protection module 120 is turned off under the control of the voltage difference between the first node N1 and the second node N2, which will not affect the input module 100, that is, will not affect the normal operation of the input module 100. In the first control node holding phase T3, the input protection module 120 is turned on under the control of the voltage difference between the first node N1 and the second node N2 to block the first voltage terminal VDD1 from leaking through the input module 100, thereby reducing the overall leakage current of the shift register unit GOA.

[0045] The conduction levels of the input module 100 and the input protection module 120 in the shift register unit GOA of the present disclosure can be the same. For example, the conduction levels of the two can be high, that is, the input module 100 and the input protection module 120 can both be turned on under the control of the high level. Of course, the conduction levels of the input module 100 and the input protection module 120 can also be low, and the present disclosure does not make special limitations here.

[0046] It should be noted that the high level and low level described in the present disclosure refer to two logical states represented by the potential range of the circuit node. For example, the first control node being at a high level may specifically refer to a level higher than the common terminal voltage, and the first control node being at a low level may specifically refer to a level lower than the common terminal voltage. The specific potential range may be set as required in a specific application scenario, and the present disclosure does not limit this.

[0047] In addition, it is worth noting that the conduction level of a certain module B described in the present disclosure can be understood as follows: the module B has a control terminal, and when a certain level signal C is applied to the control terminal of the module B, if the module B can be in a conductive state, then the level signal C is the conduction level of the module B. For example, when a high level is applied to the control terminal of the module B, the module B is turned on, and the conduction level of the module B is a high level.

[0048] The gate drive circuit disclosed in the present invention may include multiple cascaded shift register units GOA. The cascade relationship of the shift register units GOA can be, for example, that the cascade signal output terminal CR(N) of the previous stage shift register unit GOA is coupled to the input terminal Input of the next stage shift register unit GOA, the cascade signal output terminal CR(N) of the next stage shift register unit GOA is coupled to the reset signal terminal of the previous stage shift register unit GOA, and the input terminal Input of the first stage shift register unit GOA is coupled to the initial signal terminal STU.

[0049] The structure of the shift register unit GOA disclosed in the present invention is further introduced below in conjunction with the accompanying drawings.

[0050] Figure 5 FIG. 1 is a structural diagram of a shift register unit according to another embodiment of the present disclosure, Figure 5 As shown, in an exemplary embodiment, the input module 100, the input protection module 120 and the control module 200 may all include transistors, and the transistors in the input module 100, the input protection module 120 and the control module 200 are of the same type. For example, the input module 100, the input protection module 120 and the control module 200 all include N-type transistors, and the N-type transistors may be, for example, N-type oxide transistors. Of course, in other embodiments, the above modules may also have other circuit structures, and this disclosure only uses the circuit structure of FIG. Figure 5 The circuit structure shown is an exemplary description of the shift register unit.

[0051] like Figure 5As shown, in this exemplary embodiment, the transistors in the input protection module 120 are N-type transistors. On this basis, when the first control node Q1 is at a high level, the second node N2 is at a high level and its potential is close to the potential of the first control node Q1, so the potential difference between the first node N1 and the first control node Q1 (that is, the potential difference between the first node N1 and the second node N2) is less than the threshold voltage of the transistors in the input protection module 120; thereby controlling the transistors in the input protection module 120 to be turned off, that is, in the first control node setting phase T1 and the first control node coupling phase T2 of the shift register unit GOA, the input protection module 120 is turned off, so that the input protection module 120 does not affect the normal operation of the input module 100. On the contrary, when the first control node Q1 is at a low level, the voltage difference between the first node N1 and the first control node Q1 (that is, the potential difference between the first node N1 and the second node N2) is greater than the threshold voltage of the transistors in the input protection module 120. At this time, the transistor in the input module 100 is turned on, that is, in the first control node holding stage T3 after the signal shift output of the shift register unit GOA, the input protection module 120 is turned on to block the first voltage terminal VDD1 from leaking through the input module 100, thereby reducing the overall leakage current of the shift register unit GOA.

[0052] Continue to refer Figure 5 In this exemplary embodiment, the input module 100 may include a first input transistor T1 and a second input transistor T1', the first electrode of the first input transistor T1 is coupled to the first voltage terminal VDD1, the second electrode is coupled to the second node N2, and the third electrode is coupled to the input terminal Input, and the first input transistor T1 can be configured to write the signal of the first voltage terminal VDD1 to the second node N2 in response to the signal of the input terminal Input; the first electrode of the second input transistor T1' is coupled to the second node N2, the second electrode is coupled to the first control node Q1, and the third electrode is coupled to the input terminal Input, and the second input transistor T1' can be configured to write the signal of the second node N2 to the first control node Q1 in response to the signal of the input terminal Input. Among them, the first input transistor T1 and the second input transistor T1' are both N-type transistors, and the third electrodes of the first input transistor T1 and the second input transistor T1' are both coupled to the input terminal Input. When the input terminal Input is at a conduction level, the conduction level can be, for example, a high level, then the first input transistor T1 and the second input transistor T1' are turned on, so that the high level signal of the first voltage terminal VDD1 is written into the first control node Q1 via the first input transistor T1 and the second input transistor T1', and the first control node Q1 is pulled up to a high level.

[0053] Continue to refer Figure 5In this exemplary embodiment, the input protection module 120 may include a first protection transistor T3, wherein the first electrode and the third electrode of the first protection transistor T3 are both coupled to the first node N1, and the second electrode is coupled to the second node N2, and the first protection transistor T3 may be configured to be turned on in response to the voltage difference between the first node N1 and the second node N2. The first protection transistor T3 has the same polarity as the first input transistor T1 and the second input transistor T1', for example, both may be N-type transistors. The first protection transistor T3 is mainly used to protect the input module 100, specifically, the first control node of the shift register unit GOA is kept turned on in the stage T3 to reduce the leakage of the input module 100.

[0054] Specifically, in the first control node holding stage T3 of the shift register unit GOA, the first protection transistor T3 is turned on. At the same time, in this stage, the second control node Q2 is pulled up to a high level, and the first control node Q1 is pulled down to a low level. The second input transistor T1' cannot be completely turned off due to the negative drift of the threshold voltage, that is, the second input transistor T1' will leak, and the gate-source voltage Vgs of the first protection transistor T3 is VN1-VN2. The Vgs is greater than the threshold voltage Vth of the first protection transistor T3, so that the first protection transistor T3 is turned off. When the transistor T3 is turned on, the turned-on first protection transistor T3 will pull up the potential of the second node N2, so that the first input transistor T1 is turned off and cannot leak electricity, thereby shutting off the leakage path of the first voltage terminal VDD1 leaking electricity through the input module 100, so that in the first control node holding stage T3, only the second input transistor T1' in the input module 100 leaks electricity. Obviously, compared with the situation that both transistors in the input module 100 leak electricity in the related art, only the leakage of the second input transistor T1' will reduce the leakage current in the first control node holding stage T3. In addition, because the first voltage terminal VDD1 cannot leak electricity through the input module 100, and the first protection transistor T3 is coupled to the second voltage terminal VDD2, that is, it leaks electricity through the second voltage terminal VDD2, and the signal amplitude of the second voltage terminal VDD2 is smaller than the signal amplitude of the first voltage terminal VDD1, so the leakage current of the second voltage terminal VDD2 through the first protection transistor T3 and the second input transistor T1' is smaller than the leakage current leaking through the first voltage terminal VDD1. In summary, the exemplary embodiment can significantly reduce the leakage current of the shift register unit GOA in the first control node holding phase T3 through the input protection module 120 provided.

[0055] In addition, in the first control node setting stage T1 and the first control node coupling stage T2 of the shift register unit GOA, because the first control node Q1 is at a high level, the gate-source voltage Vgs=VN1-VN2 of the first protection transistor T3 is less than the threshold voltage of the first protection transistor T3, so that the first protection transistor T3 is turned off, that is, in the first control node setting stage T1 and the first control node coupling stage T2 of the shift register unit GOA, the first protection transistor T3 is turned off and will not affect the input module 100, thereby ensuring the normal operation of the input module 100.

[0056] contrast Figure 2 and Figure 5 It can be seen that the circuit structure of the input protection module 120 in the shift register unit disclosed in the present invention is significantly simplified, and a high-voltage line of VDD3 is saved, thereby reducing the occupied space of the shift register unit, which is beneficial to reducing the border size, and reducing the number of devices and high-voltage lines, which can obviously reduce the overall power consumption of the product and improve product competitiveness.

[0057] The transistor described in the present disclosure refers to an element including three terminals: a first pole, a second pole and a third pole. The first pole can be a source electrode, the second pole can be a drain electrode, and the third pole can be a gate electrode. Of course, the first pole can also be a drain electrode, and the second pole can be a source electrode. The transistor has a channel region between the first pole and the second pole, and current can flow through the first pole, the channel region and the second pole. The channel region refers to the region where the current mainly flows.

[0058] Figure 6 FIG. 1 is a schematic diagram of a structure of a shift register unit according to another embodiment of the present disclosure. Figure 6 As shown, in an exemplary embodiment, the input protection module 120 may include a first protection transistor T3 and a second protection transistor T3', the first electrode and the third electrode of the first protection transistor T3 are both coupled to the first node N1, the first electrode and the third electrode of the second protection transistor T3' are both coupled to the second electrode of the first protection transistor T3, and the second electrode of the second protection transistor T3' is coupled to the second node N2, wherein the first protection transistor T3 and the second protection transistor T3' have the same polarity as the first input transistor T1 and the second input transistor T1', for example, the first protection transistor T3 and the second protection transistor T3' are both N-type transistors.

[0059] In the first control node holding phase T3 of the shift register unit GOA, the first control node Q1 is at a low level. As described in the above embodiment, the second input transistor T1' cannot be completely turned off due to the negative drift of the threshold voltage and leaks electricity, so that the voltage difference between the first node N1 and the second node N2 is greater than the threshold voltage of the first protection transistor T3 and the threshold voltage of the second protection transistor T3', so that the first protection transistor T3 and the second protection transistor T3' are both turned on. At this time, the first input transistor T1 can be bypassed, that is, the first input transistor T1 is turned off so that the first voltage terminal VDD1 cannot leak through the input module 100, and the second voltage terminal VDD2 forms a leakage path by the first protection transistor T3, the second protection transistor T3' and the second input transistor T1'. Because of the voltage dividing effect of the second protection transistor T3', the leakage current of the shift register unit GOA in this exemplary embodiment in the first control node holding phase T3 is lower than that of Figure 5 The circuit structure in the first control node maintains the leakage current in the phase T3 further reduced.

[0060] The structure and working principle of the control module 200 are further described below in conjunction with the accompanying drawings. Figure 5 As shown, in an exemplary embodiment, the control module 200 may include a first control unit 201 and a second control unit 202, the first control unit 201 is coupled to the second voltage terminal VDD2, the first node N1 and the third node N3, and the first control unit 201 may be configured to write the signal of the second voltage terminal VDD2 into the first node N1 and the third node N3 in response to the signal of the second voltage terminal VDD2; the second control unit 202 is coupled to the third node N3, the second voltage terminal VDD2, the second control node Q2, and the first control node Q1 and receives the second level signal VGL2 and the third level signal VGL3 respectively, and the second control unit 202 may be configured to write the third level signal VGL3 into the third node N3 in response to the signal of the first control node Q1 or be configured to write the signal of the second voltage terminal VDD2 into the second control node Q2 in response to the signal of the third node N3 so that the polarity of the second control node Q2 is opposite to that of the first control node Q1.

[0061] like Figure 5As shown, in an exemplary embodiment, the first control unit 201 may include a first control transistor T4 and a second control transistor T4', the first electrode and the third electrode of the first control transistor T4 are both coupled to the second voltage terminal VDD2, and the second electrode is coupled to the first node N1; the first electrode of the second control transistor T4' is coupled to the first node N1, the second electrode is coupled to the third node N3, and the third electrode is coupled to the first node N1 or the second voltage terminal VDD2. The second control unit 202 may include a third control transistor T5, a sixth transistor T6 and a seventh transistor T7, wherein the first electrode of the third control transistor T5 is coupled to the third node N3, the second electrode receives the third level signal VGL3, and the third electrode is coupled to the first control node Q1; the first electrode of the sixth transistor T6 is coupled to the second voltage terminal VDD2, the second electrode is coupled to the second control node Q2, and the third electrode is coupled to the third node N3; the first electrode of the seventh transistor T7 is coupled to the second control node Q2, the second electrode receives the second level signal VGL2, and the third electrode is coupled to the first control node Q1; wherein the first control transistor T4, the second control transistor T4', the third control transistor T5, the sixth transistor T6 and the seventh transistor T7 have the same polarity, for example, they can all be N-type transistors.

[0062] Specifically, when the first control node Q1 is at a high level, the seventh transistor T7 is turned on under the control of the first control node Q1 and writes the second level signal VGL2 into the second control node Q2, so that the second control node Q2 outputs a low level; when the first control node Q1 is at a low level, the third control transistor T5 and the seventh transistor T7 are turned off, the first control transistor T4 and the second control transistor T4' are turned on to write the signal of the second voltage terminal VDD2 into the third node N3, so that the third node N3 is at a high level, and the sixth transistor T6 is turned on under the control of the third node N3 and writes the high level signal of the second voltage terminal VDD2 into the second control node Q2, so that the second control node Q2 outputs a high level. In this way, the control module 200 can make the polarity of the level signal of the second control node Q2 opposite to the polarity of the level signal of the first control node Q1.

[0063] Figure 7 FIG. 1 is a structural diagram of a shift register unit according to another embodiment of the present disclosure, Figure 7 In the exemplary embodiment, the third electrode of the second control transistor T4' in the first control unit 201 can also be directly coupled to the second voltage terminal VDD2, and the coupling relationship of other transistors is the same as Figure 5 In this structure, the second control transistor T4' can also be turned on under the control of the high level signal of the second voltage terminal VDD2, so as to pull up the third node N3 using the high level signal of the second voltage terminal VDD2. It should be understood that Figure 7 The control module 200 shown may have Figure 5The entire functions of the control module 200 are not described in detail here.

[0064] Figure 8 FIG. 1 is a schematic diagram of a structure of a shift register unit according to another embodiment of the present disclosure. Figure 8 In this exemplary embodiment, the structure of the first control unit 201 can be Figure 5 The structure of the first control unit 201 is the same, and will not be repeated here. The second control unit 202 may include a third control transistor T5, a fourth control transistor T5' and a sixth transistor T6, wherein the first electrode of the third control transistor T5 is coupled to the third node N3, the second electrode is coupled to the second control node Q2, and the third electrode is coupled to the first control node Q1; the first electrode of the fourth control transistor T5' is coupled to the second control node Q2, the second electrode receives the third level signal VGL3, and the third electrode is coupled to the first control node Q1; the first electrode of the sixth transistor T6 is coupled to the second voltage terminal VDD2, the second electrode is coupled to the second control node Q2, and the third electrode is coupled to the third node N3; wherein the polarity of the first control transistor T4, the second control transistor T4', the third control transistor T5, the fourth control transistor T5' and the sixth transistor T6 are the same.

[0065] Specifically, the structure and working principle of the first control unit 201 are similar to Figure 5 The control unit is the same as in the above, and will not be repeated here.

[0066] When the first control node Q1 is at a high level, the third control transistor T5 and the fourth control transistor T5' are turned on under the control of the first control node Q1, and the third level signal VGL3 is written into the third node N3, that is, the third node N3 is pulled down by the third level signal VGL3, so that the sixth transistor T6 is turned off, and the third control transistor T5 writes the third level signal VGL3 into the second control node Q2, so that the second control node Q2 outputs a low level. When the first control node Q1 is at a low level, the fourth control transistor T5' and the third control transistor T5 are turned off, and the first control unit 201 writes the high level signal of the second voltage terminal VDD2 into the third node N3, and pulls the third node N3 up to a high level, so that the sixth transistor T6 is turned on under the control of the third node N3 and writes the high level signal of the second voltage terminal VDD2 into the second control node Q2, and pulls the second control node Q2 up to a high level. In this way, the control module 200 can control the potential of the second control node Q2 to be opposite to the potential polarity of the first control node Q1.

[0067] Other structures of the shift register unit GOA disclosed in the present invention are introduced below in conjunction with the accompanying drawings.

[0068] like Figure 3As shown, the shift register unit GOA of the present disclosure may further include a first reset module 300, a reset protection module 310, a pull-down module 400, and a second reset module 500. The first reset module 300 is coupled to the first control node Q1, the first reset signal terminal STD, and the fourth node N4 and receives the second level signal VGL2. The first reset module 300 may be configured to write the second level signal VGL2 to the first control node Q1 in response to the signal of the first reset signal terminal STD to pull down the first control node Q1. The reset protection module 310 is coupled to the first voltage terminal VDD1, the first control node Q1, and the fourth node N4. The reset protection module 310 may be configured to write the signal of the first voltage terminal VDD1 to the fourth node N4 in response to the signal of the first control node Q1. The pull-down module 400 is coupled to the first control node Q1, the second control node Q2, and the fourth node N4 and receives the second level signal VGL2. The pull-down module 400 can be configured to write the second level signal VGL2 into the first control node Q1 and the fourth node N4 in response to the signal of the second control node Q2 to pull down the first control node Q1 and the fourth node N4. The second reset module 500 is coupled to the first control node Q1, the fourth node N4, and the second reset signal terminal TRS and receives the second level signal VGL2. The second reset module 500 can be configured to write the second level signal VGL2 into the first control node Q1 and the fourth node N4 in response to the signal of the second reset signal terminal TRS to reset the first control node Q1 and the fourth node N4.

[0069] The first reset module 300 can be turned on at the beginning of a frame of data to reset the shift register unit GOA. The second reset module 500 is coupled to the second reset signal terminal TRS, which is a global reset signal terminal, that is, when the second reset signal terminal TRS outputs a conduction level, all shift register units GOA in the gate drive circuit can be controlled to be reset once through their respective second reset modules 500. The pull-down module 400 can pull down the first control node Q1 under the control of the second control node Q2.

[0070] The reset protection module 310 can perform leakage protection on the first reset module 300. The specific working principle of the reset protection module 310 can be found in the introduction of the subsequent embodiments, which will not be expanded here.

[0071] In the shift register unit GOA of the present disclosure, the first reset module 300, the second reset module 500, the pull-down module 400 and the reset protection module 310 can all be implemented by transistors. Figure 5As shown, in an exemplary embodiment, the first reset module 300 may include a first reset transistor T2 and a second reset transistor T2', wherein a first electrode of the first reset transistor T2 is coupled to the first control node Q1, a second electrode is coupled to the fourth node N4, and a third electrode is coupled to the first reset signal terminal STD; a first electrode of the second reset transistor T2' is coupled to the fourth node N4, a second electrode receives the second level signal VGL2, and a third electrode is coupled to the first reset signal terminal STD. Both the first reset transistor T2 and the second reset transistor T2' may be N-type transistors.

[0072] When the first reset signal terminal STD is at a high level, the first reset transistor T2 and the second reset transistor T2 ′ are turned on, so that the second level signal VGL2 is written into the first control node Q1 to reset the first control node Q1.

[0073] When the first reset signal terminal STD is at a low level, the first reset transistor T2 and the second reset transistor T2' are both turned off, but similar to the above-mentioned input module 100, it is affected by the negative drift of the threshold voltage, and the threshold voltages of the first reset transistor T2 and the second reset transistor T2' are negative. At this time, because the first reset signal terminal STD is at a low level, its amplitude is equivalent to the second level signal VGL2, so that the gate-source voltage Vgs of the second reset transistor T2' is greater than its threshold voltage Vth. In this way, if the first reset module 300 is not protected, the first reset module 300 will not be completely turned off due to the negative drift of the threshold voltage, that is, the first reset transistor T2 and the second reset transistor T2' have leakage current. In this exemplary embodiment, the reset protection module 310 provided can reduce the leakage current of the first reset module 300, thereby playing a role in protecting the first reset module 300.

[0074] Specifically, Figure 5As shown, the reset protection module 310 may include a first reset protection transistor T21' and a second reset protection transistor T21, wherein the first electrode of the first reset protection transistor T21' is coupled to the first voltage terminal VDD1, and the third electrode is coupled to the first control node Q1; the first electrode of the second reset protection transistor T21 is coupled to the second electrode of the first reset protection transistor T21', the second electrode is coupled to the fourth node N4, and the third electrode is coupled to the first control node Q1; the first reset protection transistor T21' and the second reset protection transistor T21 may both be N-type transistors. Wherein, when the shift register unit GOA is in the first control node setting stage T1 and the first control node coupling stage T2, the first control node Q1 is at a high level, at which time, the first reset protection transistor T21' and the second reset protection transistor T21 are both turned on, and the high level signal of the first voltage terminal VDD1 is written into the fourth node N4, thereby pulling up the fourth node N4. In this way, when the first reset signal terminal STD is at a low level, the gate-source voltage Vgs of the first reset transistor T2 and the gate-source voltage Vgs of the second reset transistor T2' are both less than their threshold voltage Vth, so that the first reset transistor T2 and the second reset transistor T2' can be completely turned off, that is, the reset module will not leak electricity in the first control node setting stage T1 and the first control node coupling stage T2 of the shift register unit GOA, thereby reducing the leakage current of the shift register unit GOA.

[0075] like Figure 5 As shown, in an exemplary embodiment, the pull-down module 400 may include a first pull-down transistor T8' and a second pull-down transistor T8, wherein the first electrode of the first pull-down transistor T8' is coupled to the first control node Q1, the second electrode is coupled to the fourth node N4, and the third electrode is coupled to the second control node Q2; the first electrode of the second pull-down transistor T8 is coupled to the fourth node N4, the second electrode receives the second level signal VGL2, and the third electrode is coupled to the second control node Q2. The first pull-down transistor T8' and the second pull-down transistor T8 may both be N-type transistors. When the second control node Q2 is at a high level, the first pull-down transistor T8' and the second pull-down transistor T8 are both turned on, thereby writing the second level signal VGL2 into the first control node Q1, and pulling the first control node Q1 down to a low level.

[0076] like Figure 5As shown, in an exemplary embodiment, the second reset module 500 may include a third reset transistor T9' and a fourth reset transistor T9, wherein the first electrode of the third reset transistor T9' is coupled to the first control node Q1, the second electrode is coupled to the fourth node N4, and the third electrode is coupled to the second reset signal terminal TRS; the first electrode of the fourth reset transistor T9 is coupled to the fourth node N4, the second electrode receives the second level signal VGL2, and the third electrode is coupled to the second reset signal terminal TRS. Specifically, the third reset transistor T9' and the fourth reset transistor T9 can both be N-type transistors. When the second reset signal terminal TRS is at a high level, the third reset transistor T9' and the fourth reset transistor T9 are both turned on, so that the second level signal VGL2 is written into the first control node Q1, that is, the first control node Q1 is reset once using the second level signal VGL2. The second reset signal terminal TRS can be a global reset signal terminal, that is, when the second reset signal terminal TRS is at a high level, the second reset module 500 of each shift register unit GOA in the gate drive circuit can be controlled to be turned on, thereby resetting the first control node Q1 of each shift register unit GOA.

[0077] like Figure 3 As shown, the shift register unit GOA of the present disclosure may further include an initial control module 600, the initial control module 600 is coupled to the second control node Q2, the input terminal Input and receives the second level signal VGL2, and the initial control module 600 may be configured to write the second level signal VGL2 to the second control node Q2 in response to the signal of the input terminal Input so as to pull down the second control node Q2 using the second level signal VGL2. Because the initial control module 600 is directly coupled to the second control node Q2, when the input terminal Input is at the on level, the second control node Q2 may be quickly pulled down using the second level signal VGL2, so that the potential of the second control node Q2 is opposite to the potential polarity of the first control node Q1.

[0078] Similarly, the initial control module 600 can also be implemented by transistors. Figure 5 As shown, in an exemplary embodiment, the initial control module 600 may include a tenth transistor T10, a first electrode of the tenth transistor T10 is coupled to the second control node Q2, a second electrode receives the second level signal VGL2, and a third electrode is coupled to the input terminal Input. The tenth transistor T10 may be an N-type transistor. When the input terminal Input is at a high level, the tenth transistor T10 is turned on and the second level signal VGL2 is written into the second control node Q2, thereby using the second level signal VGL2 to quickly pull down the potential of the second control node Q2.

[0079] like Figure 3As shown, the shift register unit GOA disclosed in the present invention may further include a cascade control module 700 and a plurality of gate control modules 800. The cascade control module 700 is coupled to the first clock signal line CLKD1, the cascade signal output terminal CR(N), the first control node Q1, the second control node Q2 and receives the second level signal VGL2. The cascade control module 700 may be configured to write the signal of the first clock signal line CLKD1 into the cascade signal output terminal CR(N) in response to the signal of the first control node Q1 to output the cascade control signal CR. A gate control module 800 is coupled to a gate signal output terminal OUT, a clock signal line CLK and the first control node Q1, the second control node Q2 and receives the first level signal VGL1. The output module may be configured to write the signal of the corresponding clock signal line CLK into the corresponding gate signal output terminal OUT in response to the signal of the first control node Q1. A gate signal output terminal OUT outputs a gate control signal Gate. The gate control module 800 is configured to output a gate control signal Gate to the pixel driving circuit of the display area, and the cascade control module 700 is configured to output a cascade control signal CR, so that the gate control signal Gate and the cascade control signal CR are output by two different modules.

[0080] The shift register unit GOA disclosed in the present invention includes multiple gate control modules 800, each gate control module 800 outputs a gate control signal Gate, and a gate control signal Gate is used to control a row of pixel driving circuits in the display area, that is, a shift register unit GOA disclosed in the present invention can output multiple gate control signals Gate to control multiple rows of pixel driving circuits.

[0081] Exemplarily, the plurality of gate control modules 800 may include a first gate control module 801 to a fourth gate control module 804 , each of which outputs a gate control signal Gate. Accordingly, a shift register unit GOA of the present disclosure may output four gate control signals Gate.

[0082] like Figure 5As shown, in an exemplary embodiment, the cascade control module 700 may include an eleventh transistor T11, a twelfth transistor T12 and a first capacitor C1, wherein the first electrode of the eleventh transistor T11 is coupled to the first clock signal line CLKD1, the second electrode is coupled to the cascade signal output terminal CR(N), and the third electrode is coupled to the first control node Q1; the first electrode of the twelfth transistor T12 is coupled to the cascade signal output terminal CR(N), the second electrode receives the second level signal VGL2, and the third electrode is coupled to the second control node Q2; the first electrode of the first capacitor C1 is coupled to the first control node Q1, and the second electrode is coupled to the cascade signal output terminal CR(N). Wherein, the eleventh transistor T11 and the twelfth transistor T12 can both be N-type transistors, and when the first control node Q1 is at a high level, the eleventh transistor T11 is turned on, and the signal of the first clock signal line CLKD1 is written into the cascade signal output terminal CR(N), so that the cascade signal output terminal CR(N) outputs the cascade control signal CR. When the second control node Q2 is at a high level, the twelfth transistor T12 is turned on to write the second level signal VGL2 into the cascade signal output terminal CR(N), so that the cascade signal output terminal CR(N) outputs a low level.

[0083] like Figure 3 As shown, in this exemplary embodiment, the gate control module 800 may include a first output transistor TO1, a second output transistor TO2 and an output capacitor C0, wherein the first electrode of the first output transistor TO1 is coupled to a second clock signal line CLK, the second electrode is coupled to the corresponding gate signal output terminal OUT, and the third electrode is coupled to the first control node Q1; the first electrode of the second output transistor TO2 is coupled to the corresponding gate signal output terminal OUT, the second electrode receives the first level signal VGL1, and the third electrode is coupled to the second control node Q2. The first electrode of the output capacitor C0 is coupled to the first control node Q1, and the second electrode is coupled to the corresponding gate signal output terminal OUT.

[0084] Taking the shift register unit GOA including four gate control modules 800 as an example, refer to Figure 5, the four gate control modules 800 are the first gate control module 801 to the fourth gate control module 804, the first gate control module 801 may include a thirteenth transistor T13, a fourteenth transistor T14 and a second capacitor C2, the first electrode of the thirteenth transistor T13 is coupled to the first sub-clock signal line CLK1, the second electrode is coupled to the first gate signal output terminal OUT1, and the third electrode is coupled to the first control node Q1, so that when the first control node Q1 is at a high level, the thirteenth transistor T13 is turned on to write the signal of the first sub-clock signal line CLK1 into the first gate signal output terminal OUT1, so that the first gate signal output terminal OUT1 outputs a high-level gate control signal Gate. The first electrode of the fourteenth transistor T14 is coupled to the first gate signal output terminal OUT1, the second electrode receives the first level signal VGL1, and the third electrode is coupled to the second control node Q2, so that when the second control node Q2 is at a high level, the fourteenth transistor T14 is turned on to write the first level signal VGL1 into the first gate signal output terminal OUT1, so that the first gate signal output terminal OUT1 outputs a low level. A first electrode of the second capacitor C2 is coupled to the first control node Q1 , and a second electrode is coupled to the first gate signal output terminal OUT1 . The second capacitor C2 can be bootstrapped when both the first control node Q1 and the first sub-clock signal line CLK1 are at high levels.

[0085] The second gate control module 802 may include a fifteenth transistor T15, a sixteenth transistor T16 and a third capacitor C3. The first electrode of the fifteenth transistor T15 is coupled to the second sub-clock signal line CLK2, the second electrode is coupled to the second gate signal output terminal OUT2, and the third electrode is coupled to the first control node Q1. When the first control node Q1 is at a high level, the fifteenth transistor T15 is turned on to write the signal of the second sub-clock signal line CLK2 into the second gate signal output terminal OUT2, so that the second gate signal output terminal OUT2 outputs a high level. The first electrode of the sixteenth transistor T16 is coupled to the second gate signal output terminal OUT2, the second electrode receives the first level signal VGL1, and the third electrode is coupled to the second control node Q2. When the second control node Q2 is at a high level, the sixteenth transistor T16 is turned on, so that the second gate signal output terminal OUT2 outputs a low level. The first electrode of the third capacitor C3 is coupled to the first control node Q1, the second electrode is coupled to the second gate signal output terminal OUT2, and the third capacitor C3 can be bootstrapped using the signal of the second sub-clock signal line CLK2.

[0086] The third gate control module 803 may include a seventeenth transistor T17, an eighteenth transistor T18 and a fourth capacitor C4, wherein the first electrode of the seventeenth transistor T17 is coupled to the third sub-clock signal line CLK3, the second electrode is coupled to the third gate signal output terminal OUT3, and the third electrode is coupled to the first control node Q1. When the first control node Q1 is at a high level, the seventeenth transistor T17 is turned on to write the signal of the third sub-clock signal line CLK3 into the third gate signal output terminal OUT3, so that the third gate signal output terminal OUT3 outputs a high level. The first electrode of the fourth capacitor C4 is coupled to the first control node Q1, and the second electrode is coupled to the third gate signal output terminal OUT3. Similarly, the fourth capacitor C4 may be bootstrapped when both the first control node Q1 and the third sub-clock signal line CLK3 are at a high level.

[0087] The fourth gate control module 804 may include a nineteenth transistor T19, a twentieth transistor T20 and a fifth capacitor C5. The first electrode of the nineteenth transistor T19 is coupled to the fourth sub-clock signal line CLK4, the second electrode is coupled to the fourth gate signal output terminal OUT4, and the third electrode is coupled to the first control node Q1. When the first control node Q1 is at a high level, the nineteenth transistor T19 is turned on and writes the level signal of the fourth sub-clock signal line CLK4 to the fourth gate signal output terminal OUT4, so that the fourth gate signal output terminal OUT4 outputs a high level. The first electrode of the twentieth transistor T20 is coupled to the fourth gate signal output terminal OUT4, the second electrode receives the first level signal VGL1, and the third electrode is coupled to the second control node Q2. When the second control node Q2 is at a high level, the twentieth transistor T20 is turned on and writes the second level signal VGL2 to the fourth gate signal output terminal OUT4, so that the fourth gate signal output terminal OUT4 outputs a low level. The first electrode of the fifth capacitor C5 is coupled to the first control node Q1, and the second electrode is coupled to the fourth gate signal output terminal OUT4.

[0088] In this exemplary embodiment, the first to fourth sub-clock signal lines CLK1 to CLK4 sequentially output high levels, and the first to fourth gate signal output terminals OUT1 to OUT4 may be controlled to sequentially output high levels.

[0089] The present disclosure further provides a display panel, which may include a gate driving circuit. The gate driving circuit may include the shift register unit described in any embodiment of the present disclosure, so that row scanning is performed by gate control signals output by each shift register unit.

[0090] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A shift register unit, characterized in that: include: an input module coupled to a first voltage terminal, an input terminal, a first control node, and a second node, wherein the input module is configured to write a signal of the first voltage terminal into the first control node in response to a signal of the input terminal; a control module coupled to the second voltage terminal, the first node, the first control node, and the second control node and receiving a second level signal, wherein the control module is configured to write the second level signal to the second control node in response to the signal of the first control node or write the signal of the second voltage terminal to the second control node in response to the signal of the second voltage terminal; The input protection module is coupled to the first node and the second node, and is configured to be turned on in response to a voltage difference between the first node and the second node.

2. The shift register unit according to claim 1, characterized in that: The voltage signal amplitude of the first voltage terminal is greater than the voltage signal amplitude of the second voltage terminal.

3. The shift register unit according to claim 1, characterized in that: The input module comprises: A first input transistor, having a first electrode coupled to the first voltage terminal, a second electrode coupled to the second node, and a third electrode coupled to the input terminal, wherein the first input transistor is configured to write the signal of the first voltage terminal into the second node in response to the signal of the input terminal; a second input transistor, having a first electrode coupled to the second node, a second electrode coupled to the first control node, and a third electrode coupled to the input terminal, wherein the second input transistor is configured to write a signal of the second node into the first control node in response to a signal of the input terminal; The polarity of the first input transistor is the same as that of the second input transistor.

4. The shift register unit according to claim 3, characterized in that: The input protection module comprises: a first protection transistor, wherein a first electrode and a third electrode are both coupled to the first node, a second electrode is coupled to the second node, and the first protection transistor is configured to be turned on in response to a voltage difference between the first node and the second node; The first protection transistor has the same polarity as the first input transistor and the second input transistor.

5. The shift register unit according to claim 3, characterized in that: The input protection module comprises: A first protection transistor, a first electrode and a third electrode coupled to the first node; A second protection transistor, wherein a first electrode and a third electrode are coupled to the second electrode of the first protection transistor, and a second electrode is coupled to the second node; The first protection transistor and the second protection transistor have the same polarity as the first input transistor and the second input transistor.

6. The shift register unit according to claim 1, characterized in that: The control module comprises: a first control unit coupled to the second voltage terminal, the first node and the third node, wherein the first control unit is configured to write the signal of the second voltage terminal into the first node and the third node in response to the signal of the second voltage terminal; A second control unit is coupled to the third node, the second voltage terminal, the second control node, and the first control node and receives a second level signal and a third level signal respectively. The second control unit is configured to write the third level signal to the third node in response to a signal from the first control node or is configured to write the signal from the second voltage terminal to the second control node in response to a signal from the third node so that the polarity of the second control node is opposite to that of the first control node.

7. The shift register unit according to claim 6, characterized in that: The first control unit comprises: A first control transistor, wherein a first electrode and a third electrode are both coupled to the second voltage terminal, and a second electrode is coupled to the first node; a second control transistor, a first electrode coupled to the first node, a second electrode coupled to the third node, and a third electrode coupled to the first node or the second voltage terminal; The second control unit comprises: a third control transistor, a first electrode coupled to the third node, a second electrode receiving a third level signal, and a third electrode coupled to the first control node; a sixth transistor, having a first electrode coupled to the second voltage terminal, a second electrode coupled to the second control node, and a third electrode coupled to the third node; a seventh transistor, having a first electrode coupled to the second control node, a second electrode receiving the second level signal, and a third electrode coupled to the first control node; The first control transistor, the second control transistor, the third control transistor, the sixth transistor and the seventh transistor have the same polarity.

8. The shift register unit according to claim 7, characterized in that: The first control unit comprises: A first control transistor, wherein a first electrode and a third electrode are both coupled to the second voltage terminal, and a second electrode is coupled to the first node; a second control transistor, a first electrode coupled to the first node, a second electrode coupled to the third node, and a third electrode coupled to the first node or the second voltage terminal; The second control unit comprises: a third control transistor, a first electrode coupled to the third node, a second electrode coupled to the second control node, and a third electrode coupled to the first control node; a fourth control transistor, having a first electrode coupled to the second control node, a second electrode receiving the third level signal, and a third electrode coupled to the first control node; a sixth transistor, having a first electrode coupled to the second voltage terminal, a second electrode coupled to the second control node, and a third electrode coupled to the third node; The first control transistor, the second control transistor, the third control transistor, the fourth control transistor and the sixth transistor have the same polarity.

9. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: a first reset module coupled to the first control node, the first reset signal terminal, and the fourth node and receiving a second level signal, wherein the first reset module is configured to write the second level signal into the first control node in response to a signal at the first reset signal terminal; a reset protection module coupled to the first voltage terminal, the first control node and the fourth node, the reset protection module being configured to write a signal of the first voltage terminal into the fourth node in response to a signal of the first control node; a pull-down module, coupled to the first control node, the second control node, and the fourth node and receiving the second level signal, the pull-down module being configured to write the second level signal into the first control node and the fourth node in response to the signal of the second control node to pull the first control node and the fourth node; A second reset module is coupled to the first control node, the fourth node, and a second reset signal terminal and receives the second level signal. The second reset module is configured to write the second level signal into the first control node and the fourth node in response to the signal at the second reset signal terminal to reset the first control node and the fourth node.

10. The shift register unit according to claim 9, characterized in that: The first reset module includes: A first reset transistor, having a first electrode coupled to the first control node, a second electrode coupled to the fourth node, and a third electrode coupled to the first reset signal terminal; a second reset transistor, a first electrode coupled to the fourth node, a second electrode receiving the second level signal, and a third electrode coupled to the first reset signal terminal; The reset protection module comprises: A first reset protection transistor, a first electrode coupled to the first voltage terminal, and a third electrode coupled to the first control node; a second reset protection transistor, a first electrode coupled to the second electrode of the first reset protection transistor, a second electrode coupled to the fourth node, and a third electrode coupled to the first control node; Wherein, the first reset transistor, the second reset transistor, the first reset protection transistor and the second reset protection transistor have the same polarity; The pull-down module comprises: a first pull-down transistor, having a first electrode coupled to the first control node, a second electrode coupled to the fourth node, and a third electrode coupled to the second control node; a second pull-down transistor, having a first electrode coupled to the fourth node, a second electrode receiving the second level signal, and a third electrode coupled to the second control node; The second reset module includes: a third reset transistor, a first electrode coupled to the first control node, a second electrode coupled to the fourth node, and a third electrode coupled to the second reset signal terminal; A fourth reset transistor has a first electrode coupled to the fourth node, a second electrode receiving the second level signal, and a third electrode coupled to the second reset signal terminal.

11. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: An initial control module is coupled to the second control node and the input terminal and receives the second level signal. The initial control module is configured to write the second level signal into the second control node in response to the signal at the input terminal to pull down the second control node using the second level signal.

12. The shift register unit according to claim 11, characterized in that: The initial control module comprises: A tenth transistor has a first electrode coupled to the second control node, a second electrode receiving the second level signal, and a third electrode coupled to the input terminal.

13. The shift register unit according to claim 1, characterized in that: During the first control node setting phase and the first control node coupling phase of the shift register unit, the input protection module is turned off; In other stages of the shift register unit, the input module protection module is turned on.

14. The shift register unit according to claim 1, characterized in that: The input protection module includes an N-type transistor; When the first control node is at a high level, a potential difference between the first node and the first control node is less than a threshold voltage of a transistor in the input protection module; When the first control node is at a low level, a voltage difference between the first node and the first control node is greater than a threshold voltage of a transistor in the input protection module.

15. The shift register unit according to claim 1, characterized in that: The shift register unit also includes: a cascade control module, coupled to the first clock signal line, the cascade signal output terminal, the first control node, and the second control node, and receiving the second level signal, wherein the cascade control module is configured to write the signal of the first clock signal line to the cascade signal output terminal in response to the signal of the first control node to output a cascade control signal; Multiple gate control modules, one gate control module is coupled to a gate signal output terminal, a second clock signal line and is coupled to the first control node, the second control node and receives a first level signal, and the output module is configured to write a signal corresponding to the second clock signal line into a corresponding gate signal output terminal in response to a signal of the first control node to output a gate control signal.

16. The shift register unit according to claim 15, characterized in that: The cascade control module comprises: an eleventh transistor, a first electrode coupled to the first clock signal line, a second electrode coupled to the cascade signal output terminal, and a third electrode coupled to the first control node; a twelfth transistor, having a first electrode coupled to the cascade signal output terminal, a second electrode receiving the second level signal, and a third electrode coupled to the second control node; A first capacitor, a first electrode coupled to the first control node, and a second electrode coupled to the cascade signal output terminal; The gate control module comprises: a first output transistor, a first electrode coupled to the second clock signal line, a second electrode coupled to the corresponding gate signal output terminal, and a third electrode coupled to the first control node; a second output transistor, having a first electrode coupled to the corresponding gate signal output terminal, a second electrode receiving the first level signal, and a third electrode coupled to the second control node; The output capacitor has a first electrode coupled to the first control node and a second electrode coupled to the corresponding gate signal output terminal.

17. A display panel, characterized in that: It comprises a gate driving circuit, wherein the gate driving circuit comprises the shift register unit according to any one of claims 1 to 16.

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