Semiconductor structure, forming method of semiconductor structure and memory

Abstract

The invention provides a semiconductor structure, a semiconductor structure forming method and a memory, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate, wherein a first groove is formed in the substrate; the dielectric layer covers the inner surface of the first groove, and the dielectric layer at least comprises a side wall dielectric layer located on the side wall of the first groove and a bottom dielectric layer located at the bottom of the first groove; a word line groove is defined by the side wall dielectric layer and the bottom dielectric layer which are located in the same first groove, and the word line groove comprises edge areas close to the side wall dielectric layer and a middle area located between the edge areas; the word line structure is located in the word line groove, and the word line structure comprises an edge word line layer located in the edge area and a middle word line layer located in the middle area; and the upper surface of the middle word line layer is not lower than the upper surface of the edge word line layer. According to the invention, the GIDL problem of the semiconductor device can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for forming the semiconductor structure, and a memory. Background Art

[0002] Field effect transistor (MOS) is a commonly used component in semiconductor devices such as DRAM (Dynamic Random Access Memory). By controlling the gate potential of the field effect transistor, the conduction or cutoff between the source and the drain can be controlled.

[0003] GIDL (Gate-Induced Drain Leakage) is a major defect in field-effect transistors. With the development of semiconductor manufacturing technology, the size of field-effect transistors has been continuously reduced, and the GIDL problem has become increasingly serious, resulting in increased power consumption and reduced performance of semiconductor devices. Summary of the invention

[0004] The present disclosure provides a semiconductor structure, a method for forming the semiconductor structure, and a memory, so as to improve the GIDL problem of the semiconductor device at least to a certain extent.

[0005] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising: a substrate, in which a first trench is formed; a dielectric layer, covering an inner surface of the first trench, the dielectric layer at least comprising a sidewall dielectric layer located on a sidewall of the first trench and a bottom dielectric layer located at a bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer located in the same first trench form a word line trench, the word line trench comprising an edge region close to the sidewall dielectric layer and a middle region between the edge regions; a word line structure, located in the word line trench, the word line structure comprising an edge word line layer located in the edge region and a middle word line layer located in the middle region; an upper surface of the middle word line layer is not lower than an upper surface of the edge word line layer.

[0006] Optionally, the upper surface of the middle word line layer is arc-shaped or triangular, and the lowest point of the arc or triangle is not lower than the upper surface of the edge word line layer.

[0007] Optionally, the edge word line layer is a work function layer, and the middle word line layer is a metal layer.

[0008] According to a second aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0009] A substrate is provided, wherein a first trench is formed in the substrate, wherein the inner surface of the first trench is covered with a dielectric layer; wherein the dielectric layer at least comprises a sidewall dielectric layer located on the sidewall of the first trench and a bottom dielectric layer located at the bottom of the first trench; wherein the sidewall dielectric layer and the bottom dielectric layer located in the same first trench enclose a wordline trench, wherein the wordline trench comprises an edge region close to the sidewall dielectric layer and an intermediate region between the edge regions; wherein one or more wordline materials are filled in the wordline trench; wherein a first mask layer is formed above the substrate, wherein a missing portion in the first mask layer is located directly above the edge region; wherein the wordline material located directly above the edge region is etched using the first mask layer; wherein the first mask layer is removed, and the remaining wordline material is etched back, wherein the wordline material after the back etching forms a wordline structure; wherein the wordline structure comprises an edge wordline layer located in the edge region and an intermediate wordline layer located in the intermediate region, wherein the upper surface of the intermediate wordline layer is not lower than the upper surface of the edge wordline layer.

[0010] Optionally, forming the first mask layer above the substrate includes: coating a photoresist material above the substrate, and removing the photoresist material directly above the edge region by exposure and development, and the remaining photoresist material forms the first mask layer.

[0011] Optionally, the forming of a first mask layer above the substrate includes: forming a second mask layer above the substrate; opening a second trench in the second mask layer, the second trench being located directly above the word line trench; forming a sidewall spacer covering the sidewall of the second trench, the sidewall spacer being located directly above the edge region; forming a third mask layer to at least fill the second trench; forming a third trench in the second mask layer and the third mask layer by removing the sidewall spacer, the third trench being located directly above the edge region and having a bottom located on the upper surface of the word line material; using a composite layer formed by the remaining second mask layer and the third mask layer as the first mask layer; or etching back the second mask layer and the third mask layer to remove the third mask layer and using the remaining second mask layer as the first mask layer.

[0012] Optionally, the third trench is formed in the second mask layer and the third mask layer by removing the sidewall spacer layer, comprising: removing the sidewall spacer layer, and using the word line material as an etch stop layer, etching the second mask layer along the space formed by removing the sidewall spacer layer to form the third trench.

[0013] Optionally, the second mask layer is a stacked structure, in which the bottom layer is a first hard mask layer; the back-etching of the second mask layer and the third mask layer to remove the third mask layer includes: using the first hard mask layer as an etching stop layer, back-etching the second mask layer and the third mask layer to remove the third mask layer, and removing the portion of the first mask layer above the first hard mask layer.

[0014] Optionally, the second mask layer is a stacked structure, in which the topmost layer is a second hard mask layer; the formation of the third mask layer to at least fill the second trench includes: depositing or coating a third mask material to at least fill the second trench; using the second hard mask layer as an etch stop layer, back-etching the third mask material or the third mask material and a spacer layer located on the second mask layer to expose the sidewall spacer layer, and the remaining third mask material forms the third mask layer.

[0015] Optionally, when one or more word line materials are filled in the word line groove, the word line material also covers the top of the substrate; etching the word line material above the edge position using the first mask layer includes: etching the word line material directly above the edge area using the first mask layer, and controlling the etching end point to be no lower than the top of the word line groove.

[0016] Optionally, the word line material includes a metal material and a work function material; and filling one or more word line materials in the word line groove includes: filling the work function material in the edge area of ​​the word line groove, and filling the metal material in the middle area of ​​the word line groove.

[0017] According to a third aspect of the present disclosure, a memory is provided, comprising the semiconductor structure of the first aspect.

[0018] The technical solution disclosed in this disclosure has the following beneficial effects:

[0019] The word line structure is divided into two parts, an edge word line layer and an intermediate word line layer, and the upper surface of the intermediate word line layer is controlled not to be lower than the upper surface of the edge word line layer, so that the upper surface of the word line structure forms a flat structure or an Ω-shaped structure, etc., reducing its contact surface with the dielectric layer of the side wall, which is beneficial to improving the GIDL problem, reducing leakage current and power consumption, and improving the performance of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a semiconductor structure is shown.

[0021] Figure 2 A top view of a semiconductor structure in this exemplary embodiment is shown.

[0022] Figure 3 A cross-sectional view of a semiconductor structure in this exemplary embodiment is shown.

[0023] Figure 4 A cross-sectional view of another semiconductor structure in this exemplary embodiment is shown.

[0024] Figure 5A A cross-sectional view of a semiconductor structure showing an upper surface of a planar structure in this exemplary embodiment.

[0025] Figure 5B A cross-sectional view of a semiconductor structure showing an upper surface of an Ω-shaped structure in this exemplary embodiment is shown.

[0026] Fig. 6A A cross-sectional view of a semiconductor structure showing another planar structure upper surface in this exemplary embodiment.

[0027] Figure 6B A cross-sectional view of a semiconductor structure on the upper surface of another Ω-shaped structure in this exemplary embodiment is shown.

[0028] Figure 7 A flow chart of a method for forming a semiconductor structure in this exemplary embodiment is shown.

[0029] Figure 8 A schematic diagram showing a filling word line material in this exemplary embodiment is shown.

[0030] Fig.9A A schematic diagram showing a filling work function material and a metal material in this exemplary embodiment is shown.

[0031] Fig. 9B A schematic diagram showing another filling work function material and a metal material in this exemplary embodiment is shown.

[0032] Fig.10 A schematic diagram showing coating of a photoresist material over a substrate in this exemplary embodiment is shown.

[0033] Fig.11 A schematic diagram showing a method of forming a first mask layer from a photoresist material in this exemplary embodiment is shown.

[0034] Fig.12 A flow chart of forming a first mask layer in this exemplary embodiment is shown.

[0035] Fig.13 A schematic diagram showing the formation of a second mask layer in this exemplary embodiment is shown.

[0036] Fig.14A schematic diagram showing coating of a photoresist material on the second mask layer in this exemplary embodiment is shown.

[0037] Fig.15 A schematic diagram showing formation of a photoresist layer in this exemplary embodiment is shown.

[0038] Fig.16 A schematic diagram showing the formation of the second trench in this exemplary embodiment is shown.

[0039] Fig.17 A schematic diagram showing formation of a spacer layer in this exemplary embodiment is shown.

[0040] Fig.18 A schematic diagram showing filling of the third mask material in this exemplary embodiment is shown.

[0041] Fig.19 A schematic diagram showing the formation of a third mask layer in this exemplary embodiment is shown.

[0042] Fig. 20 A schematic diagram of forming a third trench in this exemplary embodiment is shown.

[0043] Fig.21 Another schematic diagram of forming the third trench in this exemplary embodiment is shown.

[0044] Fig. 22 A schematic diagram showing the formation of a first mask layer from a first hard mask layer in this exemplary embodiment is shown.

[0045] Fig.23A A schematic diagram showing word line material just above the first etch edge region in this exemplary embodiment is shown.

[0046] Fig. 23B A schematic diagram showing the word line material just above the second etch edge region in this exemplary embodiment is shown.

[0047] Fig.23C A schematic diagram showing a word line material directly above a third etch edge region in this exemplary embodiment is shown.

[0048] Fig.23D A schematic diagram showing a word line material directly above a fourth etch edge region in this exemplary embodiment is shown.

[0049] Fig.24A A schematic diagram after removing the first mask layer in this exemplary embodiment is shown.

[0050] Fig. 24B Another schematic diagram after removing the first mask layer in this exemplary embodiment is shown.

[0051] The reference numerals are as follows:

[0052] 101: substrate; 102: first trench; 103: dielectric layer; 1031: sidewall dielectric layer; 1032: bottom dielectric layer; 1033: dielectric layer on substrate; 104: word line trench; 1041: edge region; 1042: middle region; 105: isolation structure; 106: first mask layer; 107: word line structure; 1071: edge word line layer; 1072: middle word line layer; 108: second mask layer; 1081: first hard mask layer; 1 082: second hard mask layer; 1083: intermediate mask layer; 109: photoresist layer; 110: second trench; 111: spacer layer; 1111: sidewall spacer layer; 1112: bottom spacer layer; 1113: second mask upper spacer layer; 112: third mask layer; 113: third trench; 114: active area; 115: word line material; 1151: metal material; 1152: work function material; 116: photoresist material; 117: third mask material. DETAILED DESCRIPTION

[0053] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

[0054] The accompanying drawings are schematic diagrams of the present disclosure and are not necessarily drawn to scale. The technical solution of the present disclosure can be implemented in various forms and should not be construed as being limited to the examples set forth herein. The features, structures or characteristics described in the present disclosure may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full description of the embodiments of the present disclosure. However, it will be understood by those skilled in the art that one or more specific details may be omitted when implementing the technical solution of the present disclosure, or one or more specific details may be replaced by other methods, components, structures, etc.

[0055] Figure 1 A schematic diagram of a semiconductor structure is shown. A trench is formed in the substrate, and a gate oxide layer and a word line structure are formed in the trench. In the process of etching the word line structure, ion bombardment is directional. The word line material located at the two sides of the deeper trench is blocked by the side walls of the trench and can be exposed to less etchant. In this way, the etching rate at the two sides is lower than the etching rate at the middle position, resulting in the middle position of the word line structure after etching being lower than the two sides, forming a V-shaped (or concave) upper surface morphology. The increase in the contact area between the word line structure and the gate oxide layer of the side wall will increase the GIDL.

[0056] In view of the above problems, an exemplary embodiment of the present disclosure first provides a semiconductor structure, which may be a partial structure of a semiconductor device such as DRAM, SRAM (Static Random Access Memory), or Flash. The semiconductor structure may include: a substrate 101, in which a first trench 102 is formed; a dielectric layer 103, covering the inner surface of the first trench 102, the dielectric layer 103 at least including a sidewall dielectric layer 1031 located on the sidewall of the first trench 102 and a bottom dielectric layer 1032 located at the bottom of the first trench 102; the sidewall dielectric layer 1031 and the bottom dielectric layer 1032 located in the same first trench 102 surround a word line trench 104, the word line trench 104 includes an edge region 1041 close to the sidewall dielectric layer 1031 and a middle region 1042 located between the edge regions 1041; a word line structure 107, located in the word line trench 104, the word line structure 107 includes an edge word line layer 1071 located in the edge region 1041 and a middle word line layer 1072 located in the middle region 1042; the upper surface of the middle word line layer 1072 is not lower than the upper surface of the edge word line layer 1071.

[0057] Figure 2 A top view of a semiconductor structure is shown. An active region 114 and an isolation structure 105 are formed in a substrate 101. The substrate 101 is usually located at the bottom of a wafer, providing a base for forming a semiconductor device. The substrate 101 may be formed of materials such as silicon (such as single crystal silicon, polycrystalline silicon, amorphous silicon), germanium, silicon-germanium compounds, III-V compounds (such as gallium arsenide), etc. The substrate 101 may have an epitaxial layer, or may be a silicon substrate on an insulator (i.e., an SOI substrate). The present disclosure does not limit the specific structure in the substrate 101. The isolation structure 105 is used to separate different active regions, such as the isolation structure 105 may be a shallow trench isolation (STI) structure.

[0058] In this exemplary embodiment, four directions may be defined. The first direction may be the direction in which the word line (WordLine, WL) extends, the second direction may be the direction in which the bit line (BitLine, BL) extends, and the first direction may be perpendicular to the second direction. The third direction may be the direction in which the active area extends, and the fourth direction may be a perpendicular direction to the third direction.

[0059] refer to Figure 2 As shown, the word line structure 107 may pass through the active area 114 along the first direction, and each active area 114 may intersect with two word lines. Of course, the present disclosure does not limit this, and each active area 114 may intersect with only one word line, or with three or more word lines. Figure 2The first trench 102, the dielectric layer 103, and the word line trench 104 are not shown. The word line trench 104 is located at the same position as the word line structure 107. Figure 3 As shown, the dielectric layer 103 may be located on both sides and the bottom of the entire word line structure 107, or only on both sides and the bottom of the intersection of the word line structure 107 and the active area 114. The first trench 102 is located at the same position as the "dielectric layer 103+word line trench 104".

[0060] Figure 3 , Figure 4 , Figure 5A and Figure 5B is a cross-sectional view of the semiconductor structure along the third direction. Figure 3 and Figure 4 The semiconductor structure without the word line structure 107 is shown for explaining the first trench 102 and the word line trench 104 . Figure 5A and Figure 5B The semiconductor structure in which the word line structure 107 has been formed is shown, that is, the semiconductor structure in this exemplary embodiment.

[0061] The first trench 102 is a space in the substrate 101 for accommodating the dielectric layer 103 and the word line structure 107. The size of the first trench 102 may be determined by the size of the semiconductor device product, the critical size that can be achieved in the process, etc. Exemplarily, the depth of the first trench 102 may be 50 to 300 nm, and the width along the second direction may be 20 to 100 nm.

[0062] The dielectric layer 103 covers the inner surface of the first trench 102 and constitutes a dielectric between the gate and the channel region in the field effect transistor. The present disclosure does not limit the size of the dielectric layer 103. Exemplarily, the thickness of the dielectric layer 103 can be 1 to 20 nm. The dielectric layer 103 can be made of insulating materials such as silicon oxide (SiO2). In one embodiment, the dielectric layer 103 can be made of a high dielectric constant (High-K) material, such as hafnium oxide (HfO2), hafnium silicate oxynitride (HfSiO4), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium zirconate (HfZrO4), yttrium oxide (Y2O3), strontium titanate (SrTiO3) or lead zirconate titanate (PbZr x Ti 1-x O3), etc. Using high dielectric constant materials can effectively reduce leakage current and power consumption.

[0063] refer to Figure 3 As shown, the dielectric layer 103 may include a sidewall dielectric layer 1031 located on the sidewall of the first trench 102 and a bottom dielectric layer 1032 located at the bottom of the first trench 102. Figure 4As shown, the dielectric layer 103 may also cover the substrate 101 , and this portion of the dielectric layer 103 may be referred to as a dielectric layer 1033 on the substrate.

[0064] The word line trench 104 is a space in the first trench 102 except for the dielectric layer 103, and is a space for accommodating the word line structure 107, and can be regarded as a subspace of the first trench 102. Figure 3 or Figure 4 As shown, the word line trench 104 may be composed of an edge region 1041 and a middle region 1042. The edge region 1041 is close to the sidewall dielectric layer 1031 on both sides of the word line trench 104, and the middle region 1042 is located between the edge regions 1041. The size of the edge region 1041 and the middle region 1042, or the division ratio of the two, may be determined according to the depth of the word line trench 104 or the first trench 102, the height of the word line structure 107, etc. In general, the greater the depth of the word line trench 104 or the first trench 102, the smaller the height of the word line structure 107, and the greater the proportion of the edge region 1041 in the word line trench 104. Exemplarily, the width of the edge regions 1041 on both sides of the word line trench 104 may be 25%, and the width of the edge regions 1041 on both sides may add up to 50%. Alternatively, the width of the edge region 1041 on one side may not exceed 20 nm.

[0065] The word line structure 107 is located in the word line trench 104, which can partially fill the word line trench 104, so that a certain space is left above the word line trench 104, which can be used to form a barrier layer later to isolate the word line structure 107 from the upper structure. In this exemplary embodiment, since the word line trench 104 or the first trench 102 is located in the substrate 101, the word line structure 107 is a buried word line (Buried WordLine, BWL) structure.

[0066] The word line structure 107 may include an edge word line layer 1071 and an intermediate word line layer 1072, wherein the edge word line layer 1071 is located in the edge region 1041, and the intermediate word line layer 1072 is located in the intermediate region 1042. The upper surface of the intermediate word line layer 1072 is not lower than the upper surface of the edge word line layer 1071, which may be understood as that the lowest point of the upper surface of the intermediate word line layer 1072 is not lower than the highest point of the upper surface of the edge word line layer 1071, or the average height of the upper surface of the intermediate word line layer 1072 is not lower than the average height of the upper surface of the edge word line layer 1071.

[0067] In one embodiment, reference Figure 5A As shown, the upper surface of the middle word line layer 1072 and the upper surface of the edge word line layer 1071 are both planes, and the two are flush, which means that the height of the upper surface of the middle word line layer 1072 is equal to the height of the upper surface of the edge word line layer 1071, and the upper surface of the entire word line structure 107 is a flat structure;

[0068] In another embodiment, the upper surface of the middle word line layer 1072 is arc-shaped or triangular, and the lowest point of the arc or triangle is not lower than the upper surface of the edge word line layer 1071. Figure 5B As shown, the upper surface of the edge word line layer 1071 is a plane, the upper surface of the middle word line layer 1072 is an arc convex upward, and the upper surface of the entire word line structure 107 is an Ω-shaped (or convex) structure.

[0069] Based on the semiconductor structure in this exemplary embodiment, the word line structure 107 is divided into two parts: an edge word line layer 1071 and an intermediate word line layer 1072, and the upper surface of the intermediate word line layer 1072 is controlled not to be lower than the upper surface of the edge word line layer 1071, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, etc., reducing its contact area with the dielectric layer 103 of the side wall, which is beneficial to improving the GIDL problem, reducing leakage current and power consumption, and improving the performance of semiconductor devices.

[0070] In one embodiment, the edge word line layer 1071 and the middle word line layer 1072 may be made of the same material, such as polysilicon or titanium nitride. Fig. 6A and Figure 6B As shown, the materials of the edge word line layer 1071 and the middle word line layer 1072 may also be different. For example, the edge word line layer 1071 may be a work function layer, using a work function material such as titanium nitride (TiN), and the middle word line layer 1072 may be a metal layer, using a metal material such as tungsten (W) or an alloy material of multiple metals. The existence of the work function layer can improve the adhesion between the metal layer and the dielectric layer 103, and further reduce the leakage current.

[0071] The exemplary embodiments of the present disclosure also provide a method for forming a semiconductor structure. Figure 7 As shown, the method for forming the semiconductor structure may include the following steps S710 to S750:

[0072] Step S710, providing a substrate, in which a first trench is formed, and the inner surface of the first trench is covered with a dielectric layer; the dielectric layer at least includes a sidewall dielectric layer located on the sidewall of the first trench and a bottom dielectric layer located at the bottom of the first trench; the sidewall dielectric layer and the bottom dielectric layer located in the same first trench surround a word line trench, and the word line trench includes an edge area close to the sidewall dielectric layer and an intermediate area between the edge areas.

[0073] Before forming the first trench 102, an active area 114 and an isolation structure 105 are formed in the substrate 101. A source area, a drain area, and a channel area can be formed in the active area 114 by ion implantation or the like. Alternatively, a source area, a drain area, and a channel area can be formed in the active area 114 after forming the word line structure 107. The first trench 102 can be opened along a first direction and pass through the active area 114. The first trench 102 can be formed by photolithography and etching processes or the like.

[0074] After forming the first trench 102, a dielectric layer 103 can be formed on the inner surface of the first trench 102 by chemical vapor deposition (CVD), atomic layer deposition (ALD) and other processes, including a sidewall dielectric layer 1031 and a bottom dielectric layer 1032. The dielectric layer 103 can also cover the upper surface of the substrate 101 to form a dielectric layer 1033 on the substrate.

[0075] The structures of the first trench 102, the dielectric layer 103, and the word line trench 104 may refer to the above Figure 3 or Figure 4 shown.

[0076] Step S720: filling the word line trench with one or more word line materials.

[0077] The word line material 115 may fill the word line trench 104 in whole or in part. If the word line trench 104 is partially filled, it is necessary to ensure that the height of the word line material 115 exceeds the required height of the word line structure 107. Figure 8 As shown, the word line material 115 not only completely fills the word line trench 104, but also covers the top of the substrate 101, so that sufficient margin is reserved for the subsequent two etchings of the word line material 115, making the etching process easier to control. The upper surface of the word line material 115 can be flattened by chemical mechanical polishing or other processes to facilitate the subsequent formation of the first mask layer 106.

[0078] It should be understood that if only one word line material 115 is filled in the word line trench 104, the subsequently formed word line structure 107 is a single material film layer, and if multiple word line materials 115 are filled in the word line trench 104, the subsequently formed word line structure 107 is a composite material film layer.

[0079] In one embodiment, the word line material 115 may include a metal material 1151 and a work function material 1152. The above-mentioned filling of one or more word line materials 115 in the word line trench 104 may include the following steps:

[0080] The edge region 1041 in the word line trench 104 is filled with a work function material 1152 , and the middle region 1042 in the word line trench 104 is filled with a metal material 1151 .

[0081] refer to Figure 4 and Fig.9A As shown, the work function material 1152 can be formed by chemical vapor deposition, diffusion and other processes, completely filling the word line trench 104 and covering the top of the substrate 101. The work function material 1152 can be planarized by chemical mechanical polishing (CMP) and other processes. Then, the work function material 1152 is etched using a mask having an inverse pattern of the middle region 1042 to leave the middle region 1042. Next, the metal material 1151 can be formed by physical vapor deposition (PVD) and other processes, completely filling the middle region 1042 and covering the top of the work function material 1152. Finally, the metal material 1151 can be planarized by chemical mechanical polishing and other processes, and the metal material 1151 above the work function material 1152 can even be completely polished off to simplify the subsequent etching process.

[0082] refer to Fig. 9B As shown, the metal material 1151 can be formed by physical vapor deposition and other processes, completely filling the word line groove 104 and covering the top of the substrate 101, and the surface of the metal material 1151 can be flattened by chemical mechanical polishing and other processes. Then, the metal material 1151 is etched using a mask with an inverse pattern of the edge region 1041 to leave the edge region 1041. Next, the work function material 1152 can be formed by chemical vapor deposition, diffusion, atomic layer deposition and other processes, completely filling the edge region 1041, and can also cover the top of the metal material 1151. Finally, the work function material 1152 can be flattened by chemical mechanical polishing and other processes, and the work function material 1152 above the metal material 1151 can even be completely ground off to simplify the subsequent etching process.

[0083] Step S730, forming a first mask layer above the substrate, wherein the missing portion in the first mask layer is located directly above the edge region, such as Figure 4 and Fig.11 shown.

[0084] The first mask layer 106 may be made of a photoresist material 116 or an inorganic material, and the missing portion thereof is located directly above the edge region 1041 , that is, the first mask layer 106 has an inverse pattern of the edge region 1041 .

[0085] The first mask layer 106 is formed on the substrate 101. It should be understood that if no other film layers exist on the substrate 101, the first mask layer 106 is located on the substrate 101 and in contact with the substrate 101. If other film layers exist on the substrate 101 (such as the dielectric layer 1033 on the substrate, the word line material 115 located above the substrate 101, etc.), the first mask layer 106 may be located on the other film layers and not in contact with the substrate 101.

[0086] In one embodiment, the step of forming the first mask layer 106 above the substrate 101 may include the following steps:

[0087] A photoresist material 116 is coated on the substrate 101 , and the photoresist material 116 directly above the edge region 1041 is removed by exposure and development, and the remaining photoresist material 116 forms a first mask layer 106 .

[0088] refer to Fig.10 As shown, a photoresist material 116 is applied, which completely covers the substrate 101, such as the word line material 115 that may be located above the substrate 101. Fig.11 As shown, a photomask having a pattern of the edge region 1041 can be used to remove the photoresist material 116 directly above the edge region 1041 through exposure and development, so that the remaining photoresist material 116 has an inverse pattern of the edge region 1041, thereby forming the first mask layer 106. Considering that the width of the edge region 1041 is small, an EUV (Extreme Ultra-Violet) photolithography process can be used to expose and develop the photoresist material 116, which can accurately form a small-sized pattern in the photoresist material 116, so that the missing portion in the first mask layer 106 is accurately aligned with the edge region 1041.

[0089] In one embodiment, reference Fig.12 As shown, the above-mentioned forming of the first mask layer 106 above the substrate 101 may include the following steps S1210 to S1260:

[0090] Step S1210, forming a second mask layer above the substrate.

[0091] The second mask layer 108 may be made of an inorganic mask material, such as a hard mask layer. The second mask layer 108 may be a single-layer structure or a multi-layer structure. In one embodiment, the second mask layer may be a stacked structure, wherein the bottom layer is the first hard mask layer 1081, or the top layer is the second hard mask layer 1082. Fig.13As shown, the bottom layer of the second mask layer 108 is the first hard mask layer 1081, the top layer is the second hard mask layer 1082, and there between them are one or more intermediate mask layers 1083. Exemplarily, both the first hard mask layer 1081 and the second hard mask layer 1082 may be silicon oxynitride (SiON) layers, and the intermediate mask layer 1083 may be a spin-on hard mask (SOH) layer.

[0092] The second mask layer 108 is formed on the substrate 101. It should be understood that if no other film layers exist on the substrate 101, the second mask layer 108 is located on the substrate 101 and in contact with the substrate 101. If other film layers exist on the substrate 101 (such as the dielectric layer 1033 on the substrate, the word line material 115 located above the substrate 101, etc.), the second mask layer 108 may be located on the other film layers and not in contact with the substrate 101.

[0093] In one embodiment, silicon oxynitride can be deposited by chemical vapor deposition or other processes to form a first hard mask layer 1081, and then a spin-coated hard mask layer is formed by spin coating or other processes to serve as an intermediate mask layer 1083. Finally, silicon oxynitride is deposited by chemical vapor deposition or other processes to form a second hard mask layer 1082, thereby obtaining a complete second mask layer 108.

[0094] Step S1220, opening a second trench in the second mask layer, the second trench being located directly above the word line trench.

[0095] The second trench 110 and the word line trench 104 may be aligned in a vertical direction (ie, a direction perpendicular to the plane of the substrate 101). The second trench 110 may be formed by photolithography and etching processes. Fig.14 As shown, a photoresist material 116 is coated on the second mask layer 108 (which may be the same as or different from the photoresist material 116 coated to form the first mask layer 106). Fig.15 As shown, a photomask having a word line groove 104 pattern can be used to remove the photoresist material 116 directly above the word line groove 104 through exposure and development to form a photoresist layer 109, which has an inverse pattern of the word line groove 104. Fig.16 As shown, the second mask layer 108 is etched through the photoresist layer 109 to form a second trench 110 directly above the word line trench 104 .

[0096] The present disclosure does not limit the depth of the second trench 110. In one embodiment, the first hard mask layer 1081 can be used as an etch stop layer, and the second mask layer 108 can be etched through the photoresist layer 109 to form the second trench 110, and the bottom of the second trench 110 is located on the upper surface of the first hard mask layer 1081.

[0097] Step S1230, forming a sidewall spacer covering the sidewall of the second trench, wherein the sidewall spacer is located directly above the edge region.

[0098] Among them, the sidewall spacer 1111 can be used to determine the pattern of the edge region 1041. The sidewall spacer 1111 is located directly above the edge region 1041, and the two are aligned in the vertical direction. Usually, the width of the edge region 1041 is small, which means that the sidewall spacer 1111 needs to have a smaller thickness. Therefore, the sidewall spacer 1111 can be prepared by an atomic layer deposition process, and an ultra-thin sidewall spacer 1111 can be formed, such as a thickness of no more than 20nm. Of course, if the thickness requirement for the sidewall spacer 1111 is not high, the sidewall spacer 1111 can also be prepared by a process such as chemical vapor deposition.

[0099] In one embodiment, reference Fig.17 As shown, in the process of forming the sidewall spacer 1111, a film layer may also be formed at the bottom of the second trench 110, which is called the bottom spacer 1112. Alternatively, a film layer may also be formed on the upper surface of the second mask layer 108, which is called the second mask upper spacer 1113. One or more of the sidewall spacer 1111, the bottom spacer 1112, and the second mask upper spacer 1113 constitute the spacer 111.

[0100] Step S1240, forming a third mask layer to at least fill the second trench.

[0101] The third mask layer 112 may fill the space in the second trench 110 outside the spacer layer 111. The third mask layer 112 may be made of an inorganic mask material, such as a spin-on hard mask layer. Of course, the third mask layer 112 may also be a multilayer structure formed of multiple mask materials.

[0102] In one embodiment, the second mask layer 108 is a stacked structure, wherein the uppermost layer is the second hard mask layer 1082. The above-mentioned formation of the third mask layer 112, at least filling the second trench 110, may include the following steps:

[0103] Depositing or coating a third mask material 117 to at least fill the second trench 110;

[0104] The second hard mask layer 1082 is used as an etch stop layer to etch back the third mask material 117 or the third mask material 117 and the spacer layer 111 on the second mask layer 108 to expose the sidewall spacer layer 111 , and the remaining third mask material 117 forms the third mask layer 112 .

[0105] The third mask material 117 refers to the material of the third mask layer 112, which may be the same as or different from the material of the second mask layer 108. For example, the second mask layer 108 may include multiple mask materials, and the third mask material 117 may be one of them, such as the third mask material 117 is the same as the material of the intermediate mask layer 1083.

[0106] The third mask material 117 may be deposited by a process such as chemical vapor deposition, or may be coated by a process such as spin coating. Fig.18 As shown, the third mask material 117 can fill the second trench 110 and cover the second mask layer 108. If there is a second mask upper spacer 1113 on the second mask layer 108, the third mask material 117 covers the upper surface of the second mask upper spacer 1113.

[0107] refer to Fig.19 As shown, the second hard mask layer 1082 can then be used as an etching stop layer to back-etch the third mask material 117. If there is a spacer layer 111 (i.e., the second mask upper spacer layer 1113) on the second mask layer 108, the second mask upper spacer layer 1113 can be etched at the same time. After back-etching, the third mask material 117 outside the second trench 110 is removed, and the second mask upper spacer layer 1113 can also be removed to expose the sidewall spacer layer 111. The remaining third mask material 117 forms the third mask layer 112. Since the etching time is short, the production efficiency can be improved, and a relatively flat upper surface structure can be obtained through a suitable etching stop layer, which is conducive to the subsequent etching process.

[0108] Of course, after depositing or coating the third mask material 117, the surface of the third mask material 117 can also be flattened by processes such as chemical mechanical polishing, and the third mask material 117 and the second mask upper spacer layer 1113 located above the second mask layer 108 can be polished off, and the remaining third mask material 117 forms the third mask layer 112.

[0109] Step S1250, forming a third trench in the second mask layer and the third mask layer by removing the sidewall spacer, wherein the third trench is located directly above the edge region and has a bottom located on the upper surface of the word line material.

[0110] The sidewall spacer 1111 may be removed by etching (including dry etching, wet etching) or other processes. An etching material having a high etching selectivity ratio for the sidewall spacer 1111 compared to the second mask layer 108 and the third mask layer 112 may be selected, so that when the sidewall spacer 1111 is etched, the second mask layer 108 and the third mask layer 112 on both sides are less affected, which is beneficial to improving the position and size accuracy of the third trench 113.

[0111] In one embodiment, if the bottom of the sidewall spacer 1111 is located on the upper surface of the word line material 115 , after removing the sidewall spacer 1111 , the bottom of the space formed is also located on the upper surface of the word line material 115 , and the space can be used as the third trench 113 .

[0112] In another embodiment, if the bottom of the sidewall spacer 1111 does not reach the upper surface of the word line material 115, such as when there is another film layer (such as the first hard mask layer 1081) between the upper surface of the word line material 115 and the sidewall spacer 111, then the above-mentioned process of removing the sidewall spacer to form the third trench in the second mask layer and the third mask layer may include the following steps:

[0113] The sidewall spacer 111 is removed, and the word line material 115 is used as an etching stop layer to etch the second mask layer 108 along the space formed by removing the sidewall spacer 111 to form a third trench 113 .

[0114] That is, two-step etching can be performed, the first step is to etch the sidewall spacer 111. After removing the sidewall spacer 111, the second step is to further etch the second mask layer 108 downward along the formed space until the upper surface of the word line material 115 is reached. In this way, a trench is formed in the second mask layer 108 and the third mask layer 112, namely the third trench 113. Fig. 20 As shown, in the two-step etching process, the second mask layer 108 and the third mask layer 112 on both sides may not be affected. Fig.21 As shown, in the second etching process, a portion of the second mask layer 108 or the third mask layer 112 on both sides can be etched away at the same time. For example, the first hard mask layer 1081 and the second hard mask layer 1082 are made of the same material. When the first hard mask layer 1081 is etched along the space formed by removing the sidewall spacer 111, the second hard mask layer 1082 will also be etched away, and a portion of the third mask layer 112 or the intermediate mask layer 1083 may be etched away.

[0115] Step S1260, using the composite layer formed by the remaining second mask layer and the third mask layer as the first mask layer; or etching back the second mask layer and the third mask layer to remove the third mask layer and using the remaining second mask layer as the first mask layer.

[0116] In one embodiment, after forming the third trench 113 whose bottom reaches the upper surface of the word line material 115, the composite layer formed by all the film layers above the word line material 115 can be used as the first mask layer 106, and the first mask layer 106 has an inverse pattern of the edge region 1041. Exemplarily, the composite layer may include the remaining second mask layer 108 and the third mask layer 112, referring to Fig. 20As shown in FIG. 21 , a bottom spacer layer 1112 may also be included. In other words, Fig. 20 In or 21 , the remaining second mask layer 108 , the third mask layer 112 , and the bottom spacer layer 1112 may together form the first mask layer 106 .

[0117] In one embodiment, the composite layer above the word line material 115 may also be etched back to simplify the composite layer structure, which is beneficial to simplify the subsequent process of etching the word line material 115. Exemplarily, if the composite layer includes the remaining second mask layer 108 and the third mask layer 112, the second mask layer 108 and the third mask layer 112 are etched back, and if the composite layer also includes the bottom spacer layer 1112, the bottom spacer layer 1112 is etched back at the same time. The third mask layer 112 can be completely removed by etching back, or the third mask layer 112 and the bottom spacer layer 1112 can be completely removed, and finally the remaining second mask layer 108 is used as the first mask layer 106.

[0118] In one embodiment, the second mask layer 108 is a stacked structure, wherein the bottom layer is the first hard mask layer 1081. The above-mentioned etching back the second mask layer 108 and the third mask layer 112 to remove the third mask layer 112 may include the following steps:

[0119] The first hard mask layer 1081 is used as an etch stop layer to etch back the second mask layer 108 and the third mask layer 112 to remove the third mask layer 112 and the portion of the first mask layer 106 above the first hard mask layer 1081 .

[0120] When the second mask layer 108 and the third mask layer 112 are etched back, if the bottom spacer layer 1112 still exists in the second mask layer 108, the bottom spacer layer 1112 can be etched back at the same time. The first hard mask layer 1081 is used as an etching stop layer, and the film layers above the first hard mask layer 1081 can be completely removed. Fig. 22 As shown, after etching away the third mask layer 112, the bottom spacer layer 1112, and the portion of the first mask layer 106 above the first hard mask layer 1081, only the first hard mask layer 1081 remains in the second mask layer 108, which can be used as the first mask layer 106. In this way, the material of the first mask layer 106 is relatively simple, which facilitates the selection of a suitable etching material when etching the word line material 115 later.

[0121] exist Fig.12In the method shown, the pattern of the edge region 1041 is determined by forming a sidewall spacer 1111, and a first mask layer 106 having an inverse pattern of the edge region 1041 is formed by etching or other processes. It is not necessary to determine the pattern of the edge region 1041 by a photolithography process, but it is sufficient to determine the pattern of the second groove 110 by a photolithography process. Since the size of the second groove 110 is much larger than the size of the edge region 1041, the accuracy requirement of the photolithography process is greatly reduced, and there is no need to use high-cost photolithography processes such as EUV, which is conducive to reducing production costs.

[0122] Step S740: using the first mask layer to etch the word line material directly above the edge region.

[0123] The first mask layer 106 exposes the word line material 115 located just above the edge region 1041. The first mask layer 106 is used to etch downwards, and the word line material 115 located just above the edge region 1041 can be etched away, so as to form a concave structure just above the edge region 1041. That is, before the word line material 115 is finally etched to form the word line structure 107, the word line material 115 located just above the edge region 1041 is etched in advance to compensate for the situation that the etching rates of the word line material 115 in the edge region 1041 and the middle region 1042 are inconsistent during the final etching process. Therefore, the required depth of the concave structure can be determined according to the etching rate difference of the word line material 115 in the edge region 1041 and the middle region 1042, the structure and size parameters of the word line trench 104, and the requirements of the product. And the concave structure can reach the required depth by controlling the process parameters such as the etching time in step S740.

[0124] In one embodiment, when one or more word line materials 115 are filled in the word line trench 104, the word line material 115 also covers the substrate 101, as shown in FIG. Figure 8 As shown, the word line material 115 extends outside the word line trench 104 and covers the upper surface of the substrate dielectric layer 1033 above the substrate 101. The above-mentioned etching of the word line material 115 located above the edge position using the first mask layer includes:

[0125] The word line material 115 located directly above the edge region 1041 is etched using the first mask layer 106 , and the etching end point is controlled to be no lower than the top of the word line trench 104 .

[0126] That is, the bottom of the concave structure formed by etching the word line material 115 is not lower than the top of the word line trench 104. Exemplarily, the bottom of the concave structure may be flush with the top of the word line trench 104, or may be higher than the top of the word line trench 104. This avoids over-etching of the word line material 115 directly above the edge region 1041, so as to eventually form an unintended word line structure 107.

[0127] refer to Fig.23A As shown, the first mask layer 106 formed of the photoresist material 116 is used as a mask to etch the word line material 115, and the etching end point is controlled to be higher than the top of the word line trench 104 (ie, the top of the sidewall dielectric layer 1031). Fig. 23B As shown, the first mask layer 106 formed of the photoresist material 116 is used as a mask to etch the word line material 115, and the etching end point is controlled to be flush with the top of the word line trench 104. Fig.23C As shown, the first mask layer 106 formed by the first hard mask layer 1081 is used as a mask to etch the word line material 115, and the etching end point is controlled to be higher than the top of the word line trench 104. Fig.23D As shown, the first mask layer 106 formed by the first hard mask layer 1081 is used as a mask to etch the word line material 115 , and the etching end point is controlled to be flush with the top of the word line trench 104 .

[0128] Step S750, remove the first mask layer, etch back the remaining word line material, and form a word line structure with the etched back word line material; the word line structure includes an edge word line layer located in the edge area and an intermediate word line layer located in the middle area, and the upper surface of the intermediate word line layer is not lower than the upper surface of the edge word line layer.

[0129] The first mask layer 106 may be removed by cleaning, wet etching, dry etching or other processes, and a suitable process may be selected according to the material of the first mask layer 106 . Fig.23A and Fig.23C After removing the first mask layer 106 from the semiconductor structure shown in FIG. Fig.24A As shown, Fig. 23B and Fig.23D After removing the first mask layer 106 from the semiconductor structure shown in FIG. Fig. 24B shown.

[0130] After removing the first mask layer 106, the remaining word line material 115 is etched back, and the word line material 115 outside the word line groove 104 can be etched away, and the word line material 115 in the word line groove 104 can be etched to a desired height. The process parameters such as the back etching time can be controlled according to the desired height of the word line structure 107, so that the remaining word line material 115 finally reaches the height. The remaining word line material 115 finally forms the word line structure 107. Exemplarily, Fig.24A The semiconductor structure shown in FIG. 1 can be referred to as Figure 5A As shown, Fig. 24B The semiconductor structure shown in FIG. 1 can be referred to as Figure 5BAs shown. Thus, in the word line structure 107 finally formed, the upper surface of the middle word line layer 1072 located in the middle region 1042 is not lower than the upper surface of the edge word line layer 1071 located in the edge region 1041. Figure 5A The upper surfaces of the two are shown to be flush. Figure 5B It is shown that the upper surface of the middle word line layer 1072 is protruding, so that the upper surface of the word line structure 107 forms a flat structure or an Ω-shaped structure, which is beneficial to reduce the contact surface between it and the dielectric layer 103 of the side wall, improve the GIDL problem, and reduce leakage current and power consumption. In addition, by controlling the back etching process, the cross-sectional area of ​​the word line structure 107 can be kept unchanged or at a suitable level, such as keeping the total amount of the word line material 115 in the word line structure 107 not reduced, thereby not affecting the electrical properties of the word line such as the resistivity.

[0131] In one embodiment, if there are multiple word line materials 115, as described above Fig.9A or Fig. 9B As shown, two word line materials 115, a work function material and a metal material, are filled in the word line trench 104, and the word line structure 107 finally formed can refer to Fig. 6A or Figure 6B As shown, the word line structure 107 may include a work function layer and a metal layer, which is beneficial to improving the adhesion of the word line and further reducing the leakage current.

[0132] In summary, Figure 7 In the method shown, on the one hand, before the word line material 115 is finally etched back to form the word line structure 107, the word line material 115 above the edge region 1041 in the word line trench 104 is etched once more to compensate for the inconsistency in the etching rates of the edge region 1041 and the middle region 1042 in the back-etched word line material 115, so that the upper surface structure of the word line structure 107 can be effectively controlled to avoid the situation that the word line material 115 in the edge region 1041 is higher than the word line material 115 in the middle region 1042 after the back-etching, so that the finally formed word line structure 107 has a flat structure (i.e., the upper surface of the edge word line layer 1071 is flush with the upper surface of the middle word line layer 1072) or an Ω-shaped structure (i.e., the upper surface of the edge word line layer 1071 is lower than the arc-shaped upper surface of the middle word line layer 1072), thereby reducing the contact surface between the word line structure 107 and the dielectric layer 103 on the side wall, improving the GIDL problem, and reducing leakage current and power consumption. On the other hand, the process flow of this solution is relatively simple and easy to control, and the production cost is low.

[0133] The exemplary embodiment of the present disclosure also provides a memory, which may include any semiconductor structure in the exemplary embodiment. The memory may be a volatile memory, such as DRAM, or a non-volatile memory, such as NAND Flash. The memory has a lower GIDL and better performance.

[0134] It should be understood that the present disclosure is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The present application is intended to cover any variation, use or adaptation of the technical solution, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the art that are not disclosed herein. The contents of the specification are to be regarded as exemplary only, and the scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate having a first trench formed therein; A dielectric layer covering the inner surface of the first trench, the dielectric layer at least comprising a sidewall dielectric layer located on the sidewall of the first trench and a bottom dielectric layer located at the bottom of the first trench; The sidewall dielectric layer and the bottom dielectric layer located in the same first trench form a word line trench, and the word line trench includes an edge region close to the sidewall dielectric layer and a middle region between the edge regions; A word line structure located in the word line trench, the word line structure comprising an edge word line layer located in the edge region and a middle word line layer located in the middle region; An upper surface of the middle word line layer is not lower than an upper surface of the edge word line layer.

2. The semiconductor structure according to claim 1, characterized in that: The upper surface of the middle word line layer is arc-shaped or triangular, and the lowest point of the arc or triangle is not lower than the upper surface of the edge word line layer.

3. The semiconductor structure according to claim 1, characterized in that: The edge word line layer is a work function layer, and the middle word line layer is a metal layer.

4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein a first trench is formed in the substrate, wherein the inner surface of the first trench is covered with a dielectric layer; the dielectric layer at least comprises a sidewall dielectric layer located on the sidewall of the first trench and a bottom dielectric layer located at the bottom of the first trench; The sidewall dielectric layer and the bottom dielectric layer located in the same first trench form a word line trench, and the word line trench includes an edge region close to the sidewall dielectric layer and a middle region between the edge regions; filling one or more word line materials in the word line trench; forming a first mask layer above the substrate, wherein the missing portion in the first mask layer is located directly above the edge region; Etching the word line material located directly above the edge region using the first mask layer; Removing the first mask layer, etching back the remaining word line material, and forming a word line structure with the etched back word line material; The word line structure includes an edge word line layer located in the edge region and a middle word line layer located in the middle region, and an upper surface of the middle word line layer is not lower than an upper surface of the edge word line layer.

5. The method according to claim 4, characterized in that The step of forming a first mask layer above the substrate comprises: A photoresist material is coated on the substrate, and the photoresist material directly above the edge region is removed by exposure and development, and the remaining photoresist material forms the first mask layer.

6. The method according to claim 4, characterized in that The step of forming a first mask layer above the substrate comprises: forming a second mask layer above the substrate; Opening a second trench in the second mask layer, wherein the second trench is located directly above the word line trench; forming a sidewall spacer covering the sidewall of the second trench, wherein the sidewall spacer is located directly above the edge region; forming a third mask layer to at least fill the second trench; By removing the sidewall spacer layer, a third trench is formed in the second mask layer and the third mask layer, wherein the third trench is located directly above the edge region and the bottom thereof is located at the upper surface of the word line material; The composite layer formed by the remaining second mask layer and the third mask layer is used as the first mask layer; or the second mask layer and the third mask layer are etched back to remove the third mask layer, and the remaining second mask layer is used as the first mask layer.

7. The method according to claim 6, characterized in that The step of forming a third trench in the second mask layer and the third mask layer by removing the sidewall spacer layer comprises: The sidewall spacer is removed, and the word line material is used as an etching stop layer, and the second mask layer is etched along the space formed by removing the sidewall spacer to form the third trench.

8. The method according to claim 6, characterized in that The second mask layer is a stacked structure, wherein the bottom layer is a first hard mask layer; and the etching back of the second mask layer and the third mask layer to remove the third mask layer includes: The first hard mask layer is used as an etch stop layer, and the second mask layer and the third mask layer are etched back to remove the third mask layer and the portion of the first mask layer above the first hard mask layer.

9. The method according to claim 6, characterized in that The second mask layer is a stacked structure, wherein the uppermost layer is a second hard mask layer; The forming of the third mask layer to at least fill the second trench comprises: depositing or coating a third mask material to at least fill the second trench; The second hard mask layer is used as an etch stop layer, and the third mask material or the third mask material and the spacer layer located on the second mask layer are etched back to expose the sidewall spacer layer, and the remaining third mask material forms the third mask layer.

10. A memory, characterized in that: A semiconductor structure comprising any one of claims 1 to 3.

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