Anti-creeping read-write circuit with telescopic bit width

Abstract

An anti-creeping read-write circuit with a scalable bit width comprises a write circuit, and a pair of switching devices is connected to the power supply end and the grounding end of each of a first CMOS transistor and a second CMOS transistor of the write circuit; a control signal controls the two CMOS transistors to be switched on or switched off through the switching device so as to control the on-off of the writing circuit; and the reading circuit opens the corresponding reading port according to the data bit of the reading data, the latch caches and outputs the reading data read by the reading port, and the reading port of the reading circuit is closed. According to the application, the writing circuit in the writing process path and the reading circuit in the reading process path are respectively subjected to anti-creeping design, so that the problem that the telescopic bit width circuit generates leakage current in the reading and writing process is avoided, and the energy consumption of the circuit is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a leakage-proof read-write circuit with scalable bit width. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a general-purpose programmable logic device with high flexibility and high parallelism. It usually includes programmable logic blocks (CLB), programmable interconnect resources (CR), input and output blocks (IOB) and other IP resources, such as block RAM (BRAM), digital signal processor (DSP), etc. It provides users with system programmable or reconfigurable capabilities.

[0003] As the main block storage resource in FPGA, BRAM is mainly composed of static random access memory (SRAM). It not only provides a large amount of storage space for FPGA, but also has the advantages of flexible storage mode, high compatibility, and no need for periodic refresh, providing internal support for the high flexibility of FPGA. FPGA BRAM has a circuit path structure for read and write operations. At the same time, the data read or written by FPGA BRAM has the option of retractable bit width. The maximum value of the retractable bit width is determined according to the capacity of SRAM. When the bit width during read and write operations is not the maximum bit width, in the respective circuit paths of read and write operations, the unselected bit width circuit path is prone to leakage current. Summary of the invention

[0004] The present application provides a leakage-proof read / write circuit with scalable bit width, and performs leakage-proof design on the write circuit in the write process path and the read circuit in the read process path respectively, so as to avoid leakage current problem in the scalable bit width circuit during the read and write process and reduce the energy consumption of the circuit.

[0005] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0006] To achieve one, part or all of the above purposes or other purposes, the present invention provides a leakage-proof read-write circuit with scalable bit width.

[0007] A leakage-proof read-write circuit with scalable bit width, comprising: A write circuit, for writing data output by the scalable bit width circuit into the SRAM storage array; The write circuit comprises a first CMOS transistor and a second CMOS transistor connected to the output terminal of the first CMOS transistor; a pair of switch devices are connected to the power supply terminal and the ground terminal of the first CMOS transistor and the second CMOS transistor; a control signal controls the two CMOS transistors to be turned on or off through the switch devices, thereby controlling the on and off of the write circuit; and a read circuit, wherein the scalable bit width circuit outputs the read data of the SRAM storage array to the read circuit, and the read circuit reads the read data and performs selection output; The read circuit includes opening a corresponding read port according to a data bit of the read data, a latch caching and outputting the read data read by the read port, and closing the read port of the read circuit.

[0008] The control signal is a write control signal, including a first control signal and a second control signal which is inverted from the first control signal; The first control signal and the second control signal are connected to two switch devices respectively to control the two switch devices to be turned on or off at the same time.

[0009] After the control signal controls the two switch devices to be turned off simultaneously, the first CMOS transistor and the second CMOS transistor cannot be turned on, and the current path of the write circuit is closed.

[0010] The switch device connected to the ground terminal of the CMOS transistor is an NMOS transistor, and the switch device connected to the power terminal of the CMOS transistor is a PMOS transistor.

[0011] The write circuit also includes a pair of NMOS transistors connected to two input terminals of the SRAM storage array. The gates of the NMOS transistors are connected to the control signal and are opened or closed under the control of the control signal to realize the on and off of the write circuit.

[0012] Input data enters the scalable bit width circuit through an input write circuit. The maximum bit width value of the scalable bit width circuit corresponds to the number of columns N of the SRAM storage array. The corresponding data bit width channel is selected for output according to the data bit width of the input data.

[0013] The scalable bit width circuit is composed of N input selector circuits and N output selector circuits, and a corresponding number of input selector circuits are selected for data transmission according to the data bit width of the input data.

[0014] The number of the write circuits is consistent with the number of the input selector circuits; After the scalable bit width circuit determines the data bit width of the input data, the write circuit current path corresponding to the selector circuit that is not selected for use is closed under the action of the control signal.

[0015] The number of the read circuits is consistent with the number of the output selector circuits; After the scalable bit width circuit determines the data bit width of the read data, the read circuit path corresponding to the selector circuit that is not selected for use is closed; The read circuit includes two read ports, the two read ports have the same function and the same number of data bits, and the corresponding read port is opened according to the data bit of the read data.

[0016] The read port is an inverter with a control switch. After the read data is input into the latch, the read control signal controls the two read ports to be closed at the same time, and the read circuit no longer generates a path current, and only outputs the data cached in the latch; The latch is also provided with a clear signal terminal to clear the data cached in the latch.

[0017] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. In the present application, a pair of switch devices are connected to the power supply terminal and the ground terminal of the first CMOS transistor and the second CMOS transistor of the writing circuit; the control signal controls the two CMOS transistors to be turned on or off through the switch devices, thereby controlling the on and off of the writing circuit to avoid leakage current problems in the scalable bit width circuit during the writing process, thereby reducing the energy consumption of the circuit; 2. The present application sets the two read ports of the read circuit as inverters with control switches. After the read data is input into the latch, the read control signal controls the two read ports to be closed at the same time. The read circuit no longer generates a path current and only outputs the data cached in the latch, thereby avoiding leakage current problems in the scalable bit width circuit during the reading process and reducing the energy consumption of the circuit.

[0018] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1The figure shows a flow chart of a scalable bit width anti-leakage reading and writing circuit provided in an embodiment of the present application.

[0021] Figure 2 Shown is a schematic diagram of a selector circuit provided in an embodiment of the present application.

[0022] Figure 3 Shown is a schematic diagram of a write circuit provided in an embodiment of the present application.

[0023] Figure 4 Shown is a schematic diagram of a write circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0025] The present application provides a leakage-proof read / write circuit with scalable bit width, and performs leakage-proof design on the write circuit in the write process path and the read circuit in the read process path respectively, so as to avoid leakage current problem in the scalable bit width circuit during the read and write process and reduce the energy consumption of the circuit.

[0026] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0027] like Figure 1As shown, a leakage-proof read-write circuit with scalable bit width includes: an SRAM storage array, a read-write circuit module, a scalable bit width circuit module, and an input-output circuit module. The entire circuit forms a process path for BRAM reading and writing, wherein the SRAM storage array is connected to the read-write circuit module, the SRAM storage array stores data of the entire BRAM circuit, and the read-write circuit module has the function of writing storage data to the SRAM storage array and reading data stored in the SRAM storage array; the read-write circuit module is also connected to the scalable bit width circuit module, and the scalable bit width circuit module has the function of selecting different data bit width channels, and the storage data of a certain bit width written by the read-write circuit module to the SRAM storage array comes from the scalable bit width circuit module, and the storage data of a certain bit width read out of the SRAM storage array by the read-write circuit module is output to the scalable bit width circuit module; the scalable bit width circuit module is also connected to the input-output circuit module, and the input-output circuit module serves as a channel for the entire BRAM circuit to exchange data with other modules in the FPGA, and the data to be written to the BRAM circuit and the data to be read out of the BRAM circuit are all controlled and selected to flow in the input-output circuit module.

[0028] The input signal BRAM_in is processed by the input-output circuit module and the dwrite signal is output to the scalable bit width circuit module. The scalable bit width circuit module outputs the din signal to the read-write circuit module. The read-write circuit module then outputs the SRAM_in signal to the SRAM storage array to form the BRAM write process path. The SRAM storage array outputs the output signal SRAM_out to the read-write circuit module, the read-write circuit module outputs the dout signal to the scalable bit width circuit module, and the scalable bit width circuit module then outputs the dread signal to the input-output circuit module to generate the BRAM_out signal, thus forming the BRAM read process path.

[0029] The scalable bit width circuit module includes multiple data bit width channels. Its maximum bit width value can be determined according to the capacity of the SRAM storage array, that is, the maximum supported bit width of the scalable bit width circuit module. Different bit widths of data can select different numbers of data bit width channels. When the data bit width of the BRAM for read or write operations does not need to select the maximum bit width, there are data transmission channels in the scalable bit width circuit module that are not selected for use.

[0030] The scalable bit width circuit is composed of N input selector circuits and N output selector circuits, and a corresponding number of input selector circuits are selected for data transmission according to the data bit width of the input data.

[0031] like Figure 2As shown in FIG. 1 , Dwrite and Dwrite_out are the selector circuit parts in the write process path, and Dwrite is the input signal of the scalable bit width circuit module in the write process channel, that is, Figure 1 Dwrite_out is the output signal of the scalable bit width circuit module in the write process channel, that is, Figure 1 The din signal is connected as the input signal of the read-write circuit module; Dread and Dread_out are the selector circuit parts in the read process path, and Dread is the input signal of the scalable bit width circuit module in the read process channel, that is, Figure 1 Dread_out is the output signal of the scalable bit width circuit module in the read process channel, that is, connected to Figure 1 The dread signal is connected as the input signal of the input and output circuit module; In the write process path of BRAM, the input signal BRAM_in is processed by the input write circuit in the input-output circuit module and the dwrite signal is output to the scalable bit width circuit. The maximum bit width value of the scalable bit width circuit corresponds to the number of columns N of the SRAM storage array. The scalable bit width circuit module selects the corresponding data bit width channel according to the data bit width of the dwrite signal and outputs it to the write circuit in the read-write circuit module (when the target data bit width is less than the maximum bit width value of the BRAM, the unselected selector path in the scalable bit width circuit module may appear in the Z state to generate leakage current), and the write circuit in the read-write circuit module writes the SRAM_in signal into the SRAM storage array; In the read process path of the BRAM, the scalable bit width circuit outputs a dread signal to a read circuit in the input-output circuit module, and the read circuit in the input-output circuit module reads the dread signal and outputs a BRAM_out signal.

[0032] Therefore, the present application performs leakage current prevention design on the write circuit in the read-write circuit module in the write process path of the BRAM, and performs leakage current prevention design on the read circuit in the input-output circuit module in the read process path of the BRAM, thereby solving the problem of leakage current generated by the unselected channel circuit in the scalable bit width circuit module when the entire BRAM circuit reads and writes specific bit width data.

[0033] The write circuit in the read / write circuit module writes the data output by the scalable bit width circuit into the SRAM storage array, such as Figure 3As shown, the writing circuit includes a first CMOS transistor and a second CMOS transistor connected to the output end of the first CMOS transistor; the power supply end and the ground end of the first CMOS transistor and the second CMOS transistor are both connected to a pair of switching devices; the control signal controls the two CMOS transistors to be turned on or off through the switching devices, thereby controlling the on and off of the writing circuit; And, a pair of NMOS transistors connected to two input terminals of the SRAM storage array, the gates of the NMOS transistors are connected to the control signal, and are turned on or off under the control of the control signal to realize the on and off of the write circuit.

[0034] The control signal is a write control signal, including a first control signal and a second control signal which is inverted with the first control signal; the first control signal and the second control signal are respectively connected to two switch devices, and control the two switch devices to be turned on or off at the same time. After the control signal controls the two switch devices to be turned off at the same time, the first CMOS transistor and the second CMOS transistor cannot be turned on, and the current path of the write circuit is closed.

[0035] The number of write circuits is consistent with that of input selector circuits. After the scalable bit width circuit determines the data bit width of the input data, the write circuit current paths corresponding to the selector circuits that are not selected for use are closed under the action of the control signal.

[0036] As a preferred embodiment of the present invention, in this embodiment, the switch device connected to the ground terminal of the CMOS transistor is an NMOS transistor, and the switch device connected to the power terminal of the CMOS transistor is a PMOS transistor.

[0037] Among them, Din is the input end for writing data, that is, it is connected to the scalable bit width circuit module Dwrite_out; BN end and B end are the input ends for writing into the SRAM storage array; WE signal is the control signal for the write operation, and WEB is the inverted signal of the WE signal.

[0038] The scalable bit width circuit outputs the read data of the SRAM storage array to the read circuit in the input and output circuit module, and the read circuit selects and outputs the read data; Figure 4 As shown, the read circuit includes opening the corresponding read port according to the data bit of the read data, the latch caches the read data read by the read port and then outputs it, and the read port of the read circuit is closed.

[0039] The read circuit includes two read ports, the two read ports have the same function and the same number of data bits, and the corresponding read port is opened according to the data bit of the read data.

[0040] The read port is an inverter with a control switch. After the read data is input into the latch, the read control signal controls the two read ports to be closed at the same time. The read circuit no longer generates a path current and only outputs the data cached in the latch. The latch is also provided with a clear signal terminal to clear the data cached in the latch.

[0041] The number of the read circuits is consistent with that of the output selector circuits. After the scalable bit width circuit determines the data bit width of the read data, the read circuit paths corresponding to the selector circuits that are not selected for use are closed.

[0042] Specifically, Figure 4 As shown, in the read operation circuit path, the read circuit part in the input-output circuit module is designed, Dread_A and Dread_B are dual-port read ends, the functions and quantities of the two ports are the same, and there is only a difference in left and right end readout.

[0043] Dread_A is connected to Dread_out in the scalable bit width module. When the target bit width data to be written is selected, the selected bit width data path opens the selector at Dread_A to generate read_data and output it to the outside of the entire BRAM circuit. The unselected bit-width data path turns off the selector at Dread_A. At this time, there is no driving force at read_data, and data cannot be transmitted backwards. When Dread_A or Dread_B is turned on, the read data is transferred to the latch. At this time, Dread_A or Dread_B is closed to prevent the generation of path current. However, the read data has been latched in the latch and has been in the latch, so data_out output can be performed all the time.

[0044] The present application provides a leakage-proof read / write circuit with scalable bit width, and performs leakage-proof design on the write circuit in the write process path and the read circuit in the read process path respectively, so as to avoid leakage current problem in the scalable bit width circuit during the read and write process and reduce the energy consumption of the circuit.

[0045] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0046] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A leakage-proof read-write circuit with scalable bit width, characterized in that: include: A write circuit, for writing data output by the scalable bit width circuit into the SRAM storage array; The write circuit comprises a first CMOS transistor and a second CMOS transistor connected to the output terminal of the first CMOS transistor; a pair of switch devices are connected to the power supply terminal and the ground terminal of the first CMOS transistor and the second CMOS transistor; a control signal controls the two CMOS transistors to be turned on or off through the switch devices, thereby controlling the on and off of the write circuit; and a read circuit, wherein the scalable bit width circuit outputs the read data of the SRAM storage array to the read circuit, and the read circuit reads the read data and performs selection output; The read circuit includes opening a corresponding read port according to a data bit of the read data, a latch caching and outputting the read data read by the read port, and closing the read port of the read circuit.

2. The anti-leakage read-write circuit with scalable bit width according to claim 1, characterized in that: The control signal is a write control signal, including a first control signal and a second control signal which is inverted from the first control signal; The first control signal and the second control signal are connected to two switch devices respectively to control the two switch devices to be turned on or off at the same time.

3. The anti-leakage read-write circuit with scalable bit width according to claim 2, characterized in that: After the control signal controls the two switch devices to be turned off simultaneously, the first CMOS transistor and the second CMOS transistor cannot be turned on, and the current path of the write circuit is closed.

4. The anti-leakage read-write circuit with scalable bit width according to claim 3, characterized in that: The switch device connected to the ground terminal of the CMOS transistor is an NMOS transistor, and the switch device connected to the power terminal of the CMOS transistor is a PMOS transistor.

5. The anti-leakage read-write circuit with scalable bit width according to claim 1, characterized in that: The write circuit also includes a pair of NMOS transistors connected to two input terminals of the SRAM storage array. The gates of the NMOS transistors are connected to the control signal and are opened or closed under the control of the control signal to realize the on and off of the write circuit.

6. The anti-leakage read-write circuit with scalable bit width according to claim 1, characterized in that: Input data enters the scalable bit width circuit through an input write circuit. The maximum bit width value of the scalable bit width circuit corresponds to the number of columns N of the SRAM storage array. The corresponding data bit width channel is selected for output according to the data bit width of the input data.

7. The anti-leakage read-write circuit with scalable bit width according to claim 6, characterized in that: The scalable bit width circuit is composed of N input selector circuits and N output selector circuits, and a corresponding number of input selector circuits are selected for data transmission according to the data bit width of the input data.

8. The anti-leakage read-write circuit with scalable bit width according to claim 7, characterized in that: The number of the write circuits is consistent with the number of the input selector circuits; After the scalable bit width circuit determines the data bit width of the input data, the write circuit current path corresponding to the selector circuit that is not selected for use is closed under the action of the control signal.

9. The anti-leakage read-write circuit with scalable bit width according to claim 7, characterized in that: The number of the read circuits is consistent with the number of the output selector circuits; After the scalable bit width circuit determines the data bit width of the read data, the read circuit path corresponding to the selector circuit that is not selected for use is closed; The read circuit includes two read ports, the two read ports have the same function and the same number of data bits, and the corresponding read port is opened according to the data bit of the read data.

10. The anti-leakage read-write circuit with scalable bit width according to claim 9, characterized in that: The read port is an inverter with a control switch. After the read data is input into the latch, the read control signal controls the two read ports to be closed at the same time, and the read circuit no longer generates a path current, and only outputs the data cached in the latch; The latch is also provided with a clear signal terminal to clear the data cached in the latch.

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