Latch, memory, sequential circuit and chip

Abstract

The invention discloses a latch, a memory, a sequential circuit and a chip, and belongs to the technical field of storage. The latch comprises a latch circuit and a blocking circuit, the latch circuit is provided with a first output end, a second output end, a first power supply end and a second power supply end, a high level in an output signal of the first output end is provided by the first power supply end, and a high level in an output signal of the second output end is provided by the second power supply end. And the blocking circuit is used for blocking the conduction between the first power supply end and the power supply after the output signal of the first output end is converted from the high level to the low level, and blocking the conduction between the second power supply end and the power supply after the output signal of the second output end is converted from the high level to the low level. According to the invention, the power consumption of the latch can be reduced.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a latch, a memory, a timing circuit and a chip. Background Art

[0002] A latch is a storage unit circuit that is sensitive to pulse signals. It can change the storage state under the action of a specific pulse signal and maintain the changed storage state until the next specific pulse signal acts. Summary of the invention

[0003] The embodiments of the present application provide a latch, a memory, a timing circuit and a chip, which can reduce the power consumption of the latch. The technical solution is as follows:

[0004] In a first aspect, a latch is provided, comprising a latch circuit and a blocking circuit, wherein the latch circuit has a first output terminal, a second output terminal, a first power supply terminal and a second power supply terminal, a high level in an output signal of the first output terminal is provided by the first power supply terminal, and a high level in an output signal of the second output terminal is provided by the second power supply terminal.

[0005] The blocking circuit is used to: block the conduction between the first power supply terminal and the power supply after the output signal of the first output terminal changes from a high level to a low level; and block the conduction between the second power supply terminal and the power supply after the output signal of the second output terminal changes from a high level to a low level.

[0006] Optionally, the latch circuit has a first input terminal and a second input terminal, and the blocking circuit includes a first switch circuit and a second switch circuit;

[0007] The first switch circuit is respectively connected to the first power supply terminal, the first input terminal, the power supply and the clock signal source, and the second switch circuit is respectively connected to the second power supply terminal, the second input terminal, the power supply and the clock signal source;

[0008] The first switch circuit is used to: after the input signal of the first input terminal and the clock signal source drives the output signal of the first output terminal to be low level, block the conduction between the first power supply terminal and the power supply;

[0009] The second switch circuit is used to block conduction between the second power supply terminal and the power supply after the input signal of the second input terminal and the clock signal source drives the output signal of the second output terminal to a low level.

[0010] Optionally, the first switch circuit includes a first transistor and a second transistor;

[0011] The gate of the first transistor is connected to the first input terminal, and the gate of the second transistor is connected to the clock signal source;

[0012] The first electrode and the second electrode of the first transistor are connected to the first power supply terminal and the power supply respectively, and the first electrode and the second electrode of the second transistor are connected to the first power supply terminal and the power supply respectively.

[0013] Optionally, the second switch circuit includes a third transistor and a fourth transistor;

[0014] The gate of the third transistor is connected to the second input terminal, and the gate of the fourth transistor is connected to the clock signal source;

[0015] The first electrode and the second electrode of the third transistor are connected to the second power supply terminal and the power supply respectively, and the first electrode and the second electrode of the fourth transistor are connected to the second power supply terminal and the power supply respectively.

[0016] Optionally, the latch circuit includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0017] The gate of the fifth transistor is connected to the first input terminal, the first electrode of the fifth transistor is connected to the first output terminal, and the second electrode of the fifth transistor is connected to the first electrode of the seventh transistor;

[0018] The gate of the sixth transistor is connected to the second input terminal, the first electrode of the sixth transistor is connected to the second output terminal, and the second electrode of the sixth transistor is connected to the first electrode of the seventh transistor;

[0019] A gate of the seventh transistor is connected to a clock signal source, and a second electrode of the seventh transistor is grounded.

[0020] Optionally, the latch circuit further includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

[0021] A first electrode of the eighth transistor is connected to the first power supply terminal, a second electrode of the eighth transistor is connected to the first output terminal, and a gate of the eighth transistor is connected to the second output terminal;

[0022] A first electrode of the ninth transistor is connected to the second power supply terminal, a second electrode of the ninth transistor is connected to the second output terminal, and a gate of the ninth transistor is connected to the first output terminal;

[0023] A first electrode of the tenth transistor is connected to the first output terminal, a second electrode of the tenth transistor is grounded, and a gate of the tenth transistor is connected to the second output terminal;

[0024] A first electrode of the eleventh transistor is connected to the second output terminal, a second electrode of the eleventh transistor is grounded, and a gate of the eleventh transistor is connected to the first output terminal.

[0025] Optionally, types of the first transistor, the second transistor, the third transistor and the fourth transistor are different from a type of the seventh transistor, wherein the type includes a P-type MOS transistor or an N-type MOS transistor.

[0026] In a second aspect, a latch is provided, the latch comprising a latch circuit and a blocking circuit, wherein the latch circuit has a third output terminal, a fourth output terminal, a first ground terminal, and a second ground terminal, the third output terminal is grounded through the first ground terminal, and the fourth output terminal is grounded through the second ground terminal;

[0027] The blocking circuit is used to: block the first grounding terminal from being grounded after the output signal of the third output terminal changes from a low level to a high level; and block the second grounding terminal from being grounded after the output signal of the fourth output terminal changes from a low level to a high level.

[0028] Optionally, the latch circuit has a third input terminal and a fourth input terminal, and the blocking circuit includes a third switch circuit and a fourth switch circuit;

[0029] The third switch circuit is connected to the first ground terminal, the third input terminal and the clock signal source respectively, and the fourth switch circuit is connected to the second ground terminal, the fourth input terminal and the clock signal source respectively;

[0030] The third switch circuit is used to: after the input signal of the third input terminal and the clock signal source drives the output signal of the third output terminal to be high level, block the first ground terminal from being grounded;

[0031] The fourth switch circuit is used to block the second ground terminal from being grounded after the input signal of the fourth input terminal and the clock signal source drives the output signal of the fourth output terminal to be high level.

[0032] Optionally, the third switch circuit includes a twelfth transistor and a thirteenth transistor;

[0033] The gate of the twelfth transistor is connected to the third input terminal, and the gate of the thirteenth transistor is connected to the clock signal source;

[0034] A first electrode of the twelfth transistor is connected to the first ground terminal, a second electrode of the twelfth transistor is grounded, a first electrode of the thirteenth transistor is connected to the first ground terminal, and a second electrode of the thirteenth transistor is grounded.

[0035] Optionally, the fourth switch circuit includes a fourteenth transistor and a fifteenth transistor;

[0036] The gate of the fourteenth transistor is connected to the fourth input terminal, and the gate of the fifteenth transistor is connected to the clock signal source;

[0037] A first electrode of the fourteenth transistor is connected to the second ground terminal, a second electrode of the fourteenth transistor is grounded, a first electrode of the fifteenth transistor is connected to the second ground terminal, and a second electrode of the fifteenth transistor is grounded.

[0038] Optionally, the latch circuit includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor;

[0039] The gate of the sixteenth transistor is connected to the third input terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the eighteenth transistor, and the second electrode of the sixteenth transistor is connected to the third output terminal;

[0040] The gate of the seventeenth transistor is connected to the fourth input terminal, the first electrode of the seventeenth transistor is connected to the second electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is connected to the fourth output terminal;

[0041] A gate of the eighteenth transistor is connected to a clock signal source, and a first electrode of the eighteenth transistor is grounded.

[0042] Optionally, the latch circuit further includes a nineteenth transistor, a twentieth transistor, a twenty-first transistor, and a twenty-second transistor;

[0043] The first electrode of the nineteenth transistor is connected to the power supply, the second electrode of the nineteenth transistor is connected to the third output terminal, and the gate of the nineteenth transistor is connected to the fourth output terminal;

[0044] A first electrode of the twentieth transistor is connected to a power supply, a second electrode of the twentieth transistor is connected to the fourth output terminal, and a gate of the twentieth transistor is connected to the third output terminal;

[0045] A first electrode of the twenty-first transistor is connected to the third output terminal, a second electrode of the twenty-first transistor is connected to the first ground terminal, and a gate of the twenty-first transistor is connected to the fourth output terminal;

[0046] A first electrode of the 22nd transistor is connected to the fourth output terminal, a second electrode of the 22nd transistor is connected to the second ground terminal, and a gate of the 22nd transistor is connected to the third output terminal.

[0047] Optionally, types of the twelfth transistor, the thirteenth transistor, the fourteenth transistor and the fifteenth transistor are different from a type of the eighteenth transistor, wherein the types include P-type MOS transistors or N-type MOS transistors.

[0048] In a third aspect, a memory is provided, wherein the memory includes a peripheral circuit, wherein the peripheral circuit includes at least one latch as described in the first aspect and / or the second aspect.

[0049] In a fourth aspect, a sequential circuit is provided, wherein the sequential circuit comprises at least one latch as described in the first aspect and / or the second aspect above.

[0050] In a fifth aspect, a chip is provided, comprising at least one latch as described in the first aspect and / or the second aspect.

[0051] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0052] In the embodiment provided by the present application, a blocking circuit is added to the latch, and after the output signal of the first output terminal of the latch circuit changes from a high level to a low level, the blocking circuit can block the conduction between the first power supply terminal and the power supply. Since the first power supply terminal is blocked, even if the transistor in the latch circuit that is in a series relationship with the first power supply terminal is not turned off in time, there will be no through current flowing through the corresponding transistor, so the power consumption of the latch circuit can be reduced. Similarly, after the output signal of the second output terminal changes from a high level to a low level, the blocking circuit can block the conduction between the second power supply terminal and the power supply. Since the second power supply terminal is blocked, even if the transistor in the latch circuit that is in a series relationship with the second power supply terminal is not turned off in time, there will be no through current flowing through the corresponding transistor, so the power consumption of the latch circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 is a schematic diagram of an exemplary latch circuit provided in an embodiment of the present application;

[0055] Figure 2 is a schematic diagram of an exemplary latch circuit provided in an embodiment of the present application;

[0056] Figure 3 is a circuit diagram of a latch provided in an embodiment of the present application;

[0057] Figure 4 is a circuit diagram of a latch provided in an embodiment of the present application;

[0058] Figure 5 is a circuit diagram of a latch provided in an embodiment of the present application;

[0059] Figure 6 is a circuit diagram of a latch provided in an embodiment of the present application;

[0060] Figure 7 is a circuit diagram of a latch provided in an embodiment of the present application;

[0061] Figure 8 is a circuit diagram of a latch provided in an embodiment of the present application;

[0062] Fig. 9 It is a schematic diagram of a timing circuit provided in an embodiment of the present application;

[0063] Fig.10 It is a schematic diagram of a timing circuit provided in an embodiment of the present application;

[0064] Fig.11 It is a schematic diagram of a timing circuit provided in an embodiment of the present application;

[0065] Fig.12 It is a schematic diagram of a timing circuit provided in an embodiment of the present application;

[0066] Fig.13 is a schematic diagram of a memory including a peripheral circuit provided in an embodiment of the present application;

[0067] Fig.14 It is a schematic diagram of a memory including a memory cell array and a peripheral circuit provided by an embodiment of the present application;

[0068] Fig.15 is a schematic diagram of a system with a memory provided in an embodiment of the present application;

[0069] Fig.16 is a diagram of a memory card having a memory provided in an embodiment of the present application;

[0070] Fig.17 is a schematic diagram of a solid-state drive with a memory device provided in an embodiment of the present application.

[0071] Illustration

[0072] 1. latch circuit; 11. first output terminal; 12. second output terminal; 13. first power supply terminal; 14. second power supply terminal; 15. first input terminal; 16. second input terminal; 17. fifth transistor; 18. sixth transistor; 19. seventh transistor; 110. eighth transistor; 111. ninth transistor; 112. tenth transistor; 113. eleventh transistor;

[0073] 2. Blocking circuit; 21. First switch circuit; 22. Second switch circuit; 211. First transistor; 212. Second transistor; 221. Third transistor; 222. Fourth transistor;

[0074] 3. latch circuit; 31. third output terminal; 32. fourth output terminal; 33. first ground terminal; 34. second ground terminal; 35. third input terminal; 36. fourth input terminal; 37. sixteenth transistor; 38. seventeenth transistor; 39. eighteenth transistor; 310. nineteenth transistor; 311. twentieth transistor; 312. twenty-first transistor; 313. twenty-second transistor;

[0075] 4, blocking circuit; 41, third switch circuit; 42, fourth switch circuit; 411, twelfth transistor; 412, thirteenth transistor; 421, fourteenth transistor; 422, fifteenth transistor;

[0076] 51. First latch; 52. Second latch. DETAILED DESCRIPTION

[0077] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0078] Figure 1 is a schematic diagram of an exemplary latch circuit provided in an embodiment of the present application. Figure 1As shown, the latch circuit includes two P-type MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistor) MP0 and MP1, and five N-type MOS transistors MN0, MN1, MN2, MN3 and MN_CLK. The gates of MN2 and MN3 are the input terminals D and Dn of the latch circuit respectively. The first poles of MP0, MN0, MN2 and the gates of MP1 and MN1 are connected to the output terminal Qn of the latch circuit, and the first poles of MN1, MN3, MP1 and the gates of MP0 and MN0 are connected to the output terminal Q of the latch circuit. The second poles of MP0 and MP1 are connected to VDD (power supply), and the second poles of MN0 and MN1 are grounded. The second poles of MN2 and MN3 are connected to the first pole of MN_CLK, the second pole of MN_CLK is grounded, and the gate of MN_CLK is connected to CLK (clock). In the embodiment of the present application, the first electrode and the second electrode refer to the source or the drain. When the first electrode of a MOS tube is the source, the corresponding second electrode is the drain. When the first electrode of a MOS tube is the drain, the corresponding second electrode is the source.

[0079] exist Figure 1 In the latch circuit shown, D and Dn are input terminals, and the input signals are opposite, Q and Qn are output terminals, and the output signals are opposite. The output signal is the state to be stored, such as the first storage state is Q=1, Qn=0; the second storage state is Q=0, Qn=1. Among them, "1" can represent a high level, and "0" can represent a low level. When CLK is at a high level, MN_CLK is turned on; when CLK is at a low level, MN_CLK is blocked. When CLK is turned on, the output signals of Q and Qn can be changed by changing the input signals of D and Dn.

[0080] In the case of CLK=1, D=1, Dn=0: Q=1, Qn=0. MN_CLK, MN2, MP1, MN0 are turned on. In the case of CLK=1, D=0, Dn=1: Q=0, Qn=1. MN_CLK, MN3, MP0, MN1 are turned on.

[0081] exist Figure 1In the latch circuit shown, after switching from the storage state of Q=1, Qn=0 to the storage state of Q=0, Qn=1, MP1 will not be turned off immediately, but MN3 will be turned on immediately, so that there will be a short conduction between VDD and the ground terminal, and a large direct current will pass through MP1 and MN3, resulting in an increase in the power consumption of the latch circuit. Similarly, after switching from the storage state of Q=0, Qn=1 to the storage state of Q=1, Qn=0, MP0 will not be turned off immediately, but MN2 will be turned on immediately, so that there will be a short conduction between VDD and the ground terminal, and a large direct current will pass through MP0 and MN2, resulting in an increase in the power consumption of the latch circuit.

[0082] Figure 2 is a schematic diagram of an exemplary latch circuit provided in an embodiment of the present application. Figure 2 As shown, the latch circuit includes two N-type MOS transistors MN0 and MN1, and five P-type MOS transistors MP0, MP1, MP2, MP3 and MP_CLK. The gates of MP2 and MP3 are the input terminals D and Dn of the latch circuit respectively. The first poles of MN0, MP0 and MP2 and the gates of MP1 and MN1 are connected to the output terminal Qn of the latch circuit, and the first poles of MP1, MP3 and MN1 and the gates of MP0 and MN0 are connected to the output terminal Q of the latch circuit. The second poles of MP0 and MP1 are connected to VDD, and the second poles of MN0 and MN1 are grounded. The second poles of MP2 and MP3 are connected to the first pole of MP_CLK, the second pole of MP_CLK is connected to VDD, and the gate of MP_CLK is connected to CLK.

[0083] exist Figure 2 In the latch circuit shown, D and Dn are input terminals, and the input signals are opposite, Q and Qn are output terminals, and the output signals are opposite. The output signal is the state to be stored, such as the first storage state is Q=1, Qn=0; the second storage state is Q=0, Qn=1. Among them, "1" can represent a high level, and "0" can represent a low level. When CLK is at a high level, MN_CLK is turned on; when CLK is at a low level, MN_CLK is blocked. When CLK is turned on, the output signals of Q and Qn can be changed by changing the input signals of D and Dn.

[0084] When CLK=0, D=1, Dn=0: Q=1, Qn=0. MP_CLK, MP3, MP1, MN0 are turned on. When CLK=0, D=0, Dn=1: Q=0, Qn=1. MP_CLK, MP2, MP0, MN1 are turned on.

[0085] exist Figure 2In the latch circuit shown, after switching from the storage state of Q=1, Qn=0 to the storage state of Q=0, Qn=1, MN0 will not be turned off immediately, but MP2 will be turned on immediately, so that there will be a short conduction between VDD and the ground terminal, and a large direct current will pass through MP2 and MN0, resulting in an increase in the power consumption of the latch circuit. Similarly, after switching from the storage state of Q=0, Qn=1 to the storage state of Q=1, Qn=0, MN1 will not be turned off immediately, but MP3 will be turned on immediately, so that there will be a short conduction between VDD and the ground terminal, and a large direct current will pass through MN1 and MP3, resulting in an increase in the power consumption of the latch circuit.

[0086] By the above Figure 1 and Figure 2 From the content, we can know that at the moment when the latch changes the storage state, some internal transistors fail to change the conduction state in time, which will cause the power supply to be directly connected to the ground through the transistor, resulting in a through current flowing through the transistor, which will increase the power consumption of the latch.

[0087] Figure 3 is a circuit diagram of a latch provided in an embodiment of the present application. Figure 3 As shown, the latch includes a latch circuit 1 and a blocking circuit 2, wherein the latch circuit 1 has a first output terminal 11, a second output terminal 12, a first power supply terminal 13, and a second power supply terminal 14. The high level in the output signal of the first output terminal 11 is provided by the first power supply terminal 13, and the high level in the output signal of the second output terminal 12 is provided by the second power supply terminal 14. The first power supply terminal 13 and the second power supply terminal 14 in the latch circuit 1 are both connected to the power supply through the blocking circuit 2.

[0088] in, Figure 3 The latch circuit 1 shown can be any latch circuit with dual output terminals, such as the above-mentioned Figure 1 The latch circuit shown. The high and low levels output by the first output terminal 11 and the second output terminal 12 in the latch circuit 1 are opposite, that is, when the first output terminal 11 outputs a high level, the second output terminal 12 outputs a low level, and when the first output terminal 11 outputs a low level, the second output terminal 12 outputs a high level. In an example, the high level output by the first output terminal 11 and the low level output by the second output terminal 12 can constitute a first storage state of the latch circuit 1, such as "10", and the low level output by the first output terminal 11 and the high level output by the second output terminal 12 can constitute a second storage state of the latch circuit 1, such as "01".

[0089] Figure 3The blocking circuit 2 shown is used to block the connection between the first power supply terminal 13 and the power supply and conduct the connection between the second power supply terminal 14 and the power supply after the output signal of the first output terminal 11 changes from a high level to a low level (also the output signal of the second output terminal 12 changes from a low level to a high level). In this way, after the storage state of the latch circuit 1 is switched, even if the transistor in the latch circuit 1 connected in series with the first power supply terminal 13 fails to switch to the disconnected state in time, due to the disconnection of the first power supply terminal 13 from the power supply, no DC current will flow through the corresponding transistor, thereby reducing the power consumption of the latch circuit 1.

[0090] Figure 3 The blocking circuit 2 shown is also used to block the connection between the second power supply terminal 14 and the power supply and conduct the connection between the first power supply terminal 13 and the power supply after the output signal of the second output terminal 12 changes from a high level to a low level (also the output signal of the first output terminal 11 changes from a low level to a high level). In this way, after the storage state of the latch circuit 1 is switched, even if the transistor in the latch circuit 1 connected in series with the second power supply terminal 14 fails to switch to the disconnected state in time, due to the disconnection of the second power supply terminal 14 from the power supply, no DC current will flow through the corresponding transistor, thereby reducing the power consumption of the latch circuit 1.

[0091] Figure 4 is a circuit diagram of a latch provided in an embodiment of the present application. Figure 4 As shown, the latch circuit 1 has a first input terminal 15 and a second input terminal 16. The first input terminal 15 and the second input terminal 16 of the latch circuit 1 can be control terminals of the latch circuit 1, and the switching of the storage state in the latch circuit 1 can be controlled by controlling the input signals of the first input terminal 15 and the second input terminal 16.

[0092] In one example, the high and low levels of the input signals of the first input terminal 15 and the second input terminal 16 can be opposite. For example, when the first input terminal 15 inputs a high level and the second input terminal 16 inputs a low level, the latch circuit 1 is in the first storage state. When the first input terminal 15 switches to input a low level and the second input terminal 16 switches to input a high level, the latch circuit 1 can switch from the first storage state to the second storage state. In addition, the latch circuit 1 can also be connected to a clock signal source ( Figure 4 The signal input by the clock signal source can control whether the signals input by the first input terminal 15 and the second input terminal 16 are valid. For example, when the signal input by the clock signal source is at a high level, the signals input by the first input terminal 15 and the second input terminal 16 can control the switching of the storage state in the latch circuit 1.

[0093] Continue to see Figure 4 , the blocking circuit 2 may include a first switch circuit 21 and a second switch circuit 22 .

[0094] The first switch circuit 21 is connected to the first power supply terminal 13, the first input terminal 15, the power supply and the clock signal source respectively. The first input terminal 15 and the clock signal source can be the control terminals of the first switch circuit 21, and the signals input by the first input terminal 15 and the clock signal source can control the conduction state between the power supply and the first power supply terminal 13. The first switch circuit 21 is used to block the conduction between the first power supply terminal 13 and the power supply after the input signals of the first input terminal 15 and the clock signal source drive the output signal of the first output terminal 11 to a low level.

[0095] By the above Figure 4 As can be seen from the introduction, the first input terminal 15 of the latch circuit 1 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 1. Therefore, the first input terminal 15 and the output signal of the clock signal source can be used as the input signal of the first switch circuit 21. When the output signal of the first input terminal 15 and the clock signal source is used to drive the output signal of the first output terminal 11 of the latch circuit 1 to be low level, after the output signal of the first input terminal 15 and the clock signal source is input to the first switch circuit 21, the first power supply terminal 13 can be blocked from the power supply.

[0096] For example, when the first input terminal 15 and the clock signal source are switched to a high level, the output signal of the first output terminal 11 of the latch circuit 1 can be driven to a low level, and the switch between the first power supply terminal 13 and the power supply in the first switch circuit 21 can be driven to be disconnected. Since the high level of the first output terminal 11 is provided by the first power supply terminal 13, when the output of the first output terminal 11 is at a low level, the conduction between the first power supply terminal 13 and the power supply is blocked, so that the first output terminal 11 can directly output a low level without affecting the storage state of the latch circuit 1. And since the conduction between the first power supply terminal 13 and the power supply is blocked, the transistor in the latch circuit 1 that is connected in series with the first power supply terminal 13 and is grounded will not have a direct current passing through it even if it is not disconnected in time, so the power consumption of the latch circuit 1 can be reduced.

[0097] In one example, the first switch circuit 21 can block the conduction between the first power supply terminal 13 and the power supply only when the signal output by the first input terminal 15 and the clock signal source drives the output signal of the first output terminal 11 of the latch circuit 1 to switch to a low level. When the output signal of the first input terminal 15 or the clock signal source changes, the first switch circuit 21 can restore the conduction between the first power supply terminal 13 and the power supply to ensure the normal operation of the latch circuit 1.

[0098] Continue to see Figure 4The second switch circuit 22 is connected to the second power supply terminal 14, the second input terminal 16 of the latch circuit 1, the power supply and the clock signal source respectively. The second input terminal 16 and the clock signal source can be the control terminals of the second switch circuit 22, and the signals input by the second input terminal 16 and the clock signal source can control the conduction state between the power supply and the second power supply terminal 14. The second switch circuit 22 is used to block the conduction between the second power supply terminal 14 and the power supply after the input signals of the second input terminal 16 and the clock signal source drive the output signal of the second output terminal 12 to a low level.

[0099] By the above Figure 4 As can be seen from the introduction, the second input terminal 16 of the latch circuit 1 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 1. Therefore, the second input terminal 16 and the output signal of the clock signal source can be used as the input signal of the second switch circuit 22. When the second input terminal 16 and the output signal of the clock signal source are used to drive the output signal of the second output terminal 12 of the latch circuit 1 to be low level, after the second input terminal 16 and the output signal of the clock signal source are input to the second switch circuit 22, the second power supply terminal 14 can be blocked from the power supply.

[0100] For example, when the second input terminal 16 and the clock signal source are switched to a high level, the output signal of the second output terminal 12 of the latch circuit 1 can be driven to a low level, and the switch between the second power supply terminal 14 and the power supply in the second switch circuit 22 can be driven to be disconnected. Since the high level of the second output terminal 12 is provided by the second power supply terminal 14, when the output of the second output terminal 12 is at a low level, the conduction between the second power supply terminal 14 and the power supply is blocked, so that the second output terminal 12 can directly output a low level without affecting the storage state of the latch circuit 1. And since the conduction between the second power supply terminal 14 and the power supply is blocked, the transistor in the latch circuit 1 that is connected in series with the second power supply terminal 14 and is grounded will not have a direct current passing through it even if it is not turned off in time, so the power consumption of the latch circuit 1 can be reduced.

[0101] In one example, the second switch circuit 22 can block the conduction between the second power supply terminal 14 and the power supply only when the output signal of the second output terminal 12 of the latch circuit 1 is switched to a low level by the signal outputted by the second input terminal 16 and the clock signal source. When the output signal of the second input terminal 16 or the clock signal source changes, the second switch circuit 22 can restore the conduction between the second power supply terminal 14 and the power supply to ensure the normal operation of the latch circuit 1.

[0102] Figure 5 is a circuit diagram of a latch provided in an embodiment of the present application. Figure 5As shown, the first switch circuit 21 includes a first transistor 211 and a second transistor 212. The gate of the first transistor 211 is connected to the first input terminal 15, and the gate of the second transistor 212 is connected to the clock signal source. The first electrode and the second electrode of the first transistor 211 are respectively connected to the first power supply terminal 13 and the power supply, and the first electrode and the second electrode of the second transistor 212 are respectively connected to the first power supply terminal 13 and the power supply.

[0103] In implementation, the types of the first transistor 211 and the second transistor 212 can be set according to the input signals of the first input terminal 15 and the clock signal source when the output signal of the first output terminal 11 driven by the first input terminal 15 and the clock signal source is low level, so as to realize that when the output signal of the first output terminal 11 driven by the first input terminal 15 and the clock signal source is low level, the first transistor 211 and the second transistor 212 are both in the disconnected state. The type can be a P-type MOS tube or an N-type MOS tube. For example, when the output signal of the first output terminal 11 driven by the first input terminal 15 and the clock signal source is low level, the first input terminal 15 and the clock signal source are both high level, then the first transistor 211 and the second transistor 212 can both be P-type MOS tubes.

[0104] Continue to see Figure 5 The second switch circuit 22 includes a third transistor 221 and a fourth transistor 222. The gate of the third transistor 221 is connected to the second input terminal 16, and the gate of the fourth transistor 222 is connected to the clock signal source. The first and second electrodes of the third transistor 221 are respectively connected to the second power supply terminal 14 and the power supply, and the first and second electrodes of the fourth transistor 222 are respectively connected to the second power supply terminal 14 and the power supply.

[0105] In implementation, the types of the third transistor 221 and the fourth transistor 222 can be set according to the input signals of the first input terminal 15 and the clock signal source when the output signal of the first output terminal 11 driven by the first input terminal 15 and the clock signal source is low level, so as to realize that when the output signal of the first output terminal 11 driven by the first input terminal 15 and the clock signal source is low level, the third transistor 221 and the fourth transistor 222 are both in the disconnected state. The type can be a P-type MOS tube or an N-type MOS tube. For example, when the output signal of the first output terminal 11 driven by the first input terminal 15 and the clock signal source is low level, the first input terminal 15 and the clock signal source are both high level, then the first transistor 211 and the second transistor 212 can both be P-type MOS tubes.

[0106] In an achievable manner, the latch circuit 1 includes a fifth transistor 17, a sixth transistor 18, and a seventh transistor 19. Figure 5As shown, the gate of the fifth transistor 17 is connected to the first input terminal 15, the first electrode of the fifth transistor 17 is connected to the first output terminal 11, and the second electrode of the fifth transistor 17 is connected to the first electrode of the seventh transistor 19. The gate of the sixth transistor 18 is connected to the second input terminal 16, the first electrode of the sixth transistor 18 is connected to the second output terminal 12, and the second electrode of the sixth transistor 18 is connected to the first electrode of the seventh transistor 19. The gate of the seventh transistor 19 is connected to the clock signal source, and the second electrode of the seventh transistor 19 is grounded.

[0107] Continue to see Figure 5 The latch circuit 1 further includes an eighth transistor 110, a ninth transistor 111, a tenth transistor 112, and an eleventh transistor 113. The first electrode of the eighth transistor 110 is connected to the first power supply terminal 13, the second electrode of the eighth transistor 110 is connected to the first output terminal 11, and the gate of the eighth transistor 110 is connected to the second output terminal 12. The first electrode of the ninth transistor 111 is connected to the second power supply terminal 14, the second electrode of the ninth transistor 111 is connected to the second output terminal 12, and the gate of the ninth transistor 111 is connected to the first output terminal 11. The first electrode of the tenth transistor 112 is connected to the first output terminal 11, the second electrode of the tenth transistor 112 is grounded, and the gate of the tenth transistor 112 is connected to the second output terminal 12. The first electrode of the eleventh transistor 113 is connected to the second output terminal 12, the second electrode of the eleventh transistor 113 is grounded, and the gate of the eleventh transistor 113 is connected to the first output terminal 11.

[0108] Among them, the fifth transistor 17, the sixth transistor 18, the seventh transistor 19, the tenth transistor 112 and the eleventh transistor 113 may be of the same type, such as an N-type MOS transistor, and the eighth transistor 110 and the ninth transistor 111 may be of the same type, and different from the type of the fifth transistor 17, such as a P-type MOS transistor. The first transistor 211, the second transistor 212, the third transistor 221 and the fourth transistor 222 may be of the same type, and different from the type of the seventh transistor 19, such as a P-type MOS transistor.

[0109] Taking the fifth transistor 17 as an N-type MOS tube as an example, when the first input terminal 15 inputs a high level, the second input terminal 16 inputs a low level, and CLK outputs a high level, the fifth transistor 17, the seventh transistor 19, the ninth transistor 111, and the tenth transistor 112 in the latch circuit 1 are turned on, and only the third transistor 221 in the second switch circuit 22 in the blocking circuit 2 is turned on. The first output terminal 11 outputs a low level, and the second output terminal 12 outputs a high level. When the first input terminal 15 is switched to a low level, the second input terminal 16 is switched to a high level, and CLK outputs a high level, the sixth transistor 18, the seventh transistor 19, the eighth transistor 110, and the eleventh transistor 113 in the latch circuit 1 are turned on, and only the first transistor 211 in the first switch circuit 21 in the blocking circuit 2 is turned on. The first output terminal 11 outputs a high level, and the second output terminal 12 outputs a low level. Among them, the high level of the second input terminal 16 acts on the gate of the sixth transistor 18 to turn on the sixth transistor 18, but due to the circuit control delay, the high level output by the first output terminal 11 acts on the gate of the ninth transistor 111 to block the conduction of the ninth transistor 111, which is later than the conduction of the sixth transistor 18. Therefore, after the latch circuit 1 switches the storage state, there is a momentary conduction between the ninth transistor 111 and the sixth transistor 18 and the ground terminal. However, the time when the high level of the clock signal source and the high level of the second input terminal 16 block the third transistor 221 and the fourth transistor 222 in the second switch circuit 22 is the same as the time when the high level of the second input terminal 16 turns on the sixth transistor 18. Therefore, even if the ninth transistor 111 fails to turn off in time, the second switch circuit 22 can block the connection between the second power supply terminal 14 and the power supply, and can avoid the current passing between the ninth transistor 111 and the sixth transistor 18 and the ground terminal. In this way, the power consumption of the latch circuit 1 can be reduced. In addition, the fifth transistor 17 is a P-type MOS tube, which is similar to the case where the fifth transistor 17 is an N-type MOS tube, and will not be repeated in the embodiment of the present application.

[0110] Figure 6 is a circuit diagram of a latch provided in an embodiment of the present application. Figure 6 As shown, the latch includes a latch circuit 3 and a blocking circuit 4, wherein the latch circuit 3 has a third output terminal 31, a fourth output terminal 32, a first ground terminal 33 and a second ground terminal 34, the third output terminal 31 is grounded through the first ground terminal 33, and the fourth output terminal 32 is grounded through the second ground terminal 34. The first ground terminal 33 and the second ground terminal 34 in the latch circuit 3 are both grounded through the blocking circuit 4.

[0111] in, Figure 6 The latch circuit 3 shown can be any latch circuit with dual output terminals, such as the above-mentioned Figure 2The latch circuit shown. The third output terminal 31 and the fourth output terminal 32 in the latch circuit 3 output opposite signals, that is, when the third output terminal 31 outputs a high level, the fourth output terminal 32 outputs a low level, and when the third output terminal 31 outputs a low level, the fourth output terminal 32 outputs a high level. In one example, the high level output by the third output terminal 31 and the low level output by the fourth output terminal 32 can constitute the first storage state of the latch circuit 3, such as "10", and the low level output by the third output terminal 31 and the high level output by the fourth output terminal 32 can constitute the second storage state of the latch circuit 1, such as "01".

[0112] Figure 6 The blocking circuit 4 shown is used to block the first grounding terminal 33 from being grounded and ground the second grounding terminal 34 after the output signal of the third output terminal 31 changes from a low level to a high level (also after the output signal of the fourth output terminal 32 changes from a high level to a low level). In this way, after the storage state of the latch circuit 3 is switched, even if the transistor in the latch circuit 1 connected in series with the first grounding terminal 33 fails to be switched to the disconnected state in time, since the first grounding terminal 33 is not grounded, no DC current will flow through the corresponding transistor, thereby reducing the power consumption of the latch circuit 3.

[0113] Figure 6 The blocking circuit 4 shown is also used to block the second grounding terminal 34 from being grounded and ground the first grounding terminal 33 after the output signal of the fourth output terminal 32 changes from a low level to a high level (also the output signal of the third output terminal 31 changes from a high level to a low level). In this way, after the storage state of the latch circuit 3 is switched, even if the transistor in the latch circuit 3 connected in series with the second grounding terminal 34 fails to be switched to the disconnected state in time, since the second grounding terminal 34 is not grounded, no DC current will flow through the corresponding transistor, thereby reducing the power consumption of the latch circuit 3.

[0114] Figure 7 is a circuit diagram of a latch provided in an embodiment of the present application. Figure 7 As shown, the latch circuit 3 has a third input terminal 35 and a fourth input terminal 36. The third input terminal 35 and the fourth input terminal 36 of the latch circuit 3 can be control terminals of the latch circuit 3. By controlling the input signals of the third input terminal 35 and the fourth input terminal 36, the switching of the storage state in the latch circuit 3 can be controlled.

[0115] In one example, the input signals of the third input terminal 35 and the fourth input terminal 36 can be opposite. For example, when the third input terminal 35 inputs a high level and the fourth input terminal 36 inputs a low level, the latch circuit 3 is in the first storage state. When the third input terminal 35 switches to input a low level and the fourth input terminal 36 switches to input a high level, the latch circuit 3 can switch from the first storage state to the second storage state. In addition, the latch circuit 3 can also be connected to a clock signal source ( Figure 7 As shown in FIG. 1 , the signal input by the clock signal source can control whether the signals input by the third input terminal 35 and the fourth input terminal 36 are valid. For example, when the signal input by the clock signal source is at a high level, the signals input by the third input terminal 35 and the fourth input terminal 36 can control the switching of the storage state in the latch circuit 3.

[0116] Continue to see Figure 7 , the blocking circuit 4 may include a third switch circuit 41 and a fourth switch circuit 42 .

[0117] The third switch circuit 41 is connected to the first ground terminal 33, the third input terminal 35, the clock signal source and GND (ground point) respectively. The third input terminal 35 and the clock signal source can be the control terminal of the third switch circuit 41, and the signal input by the third input terminal 35 and the clock signal source can control the conduction state between the first ground terminal 33 and GND. The third switch circuit 41 is used to block the conduction between the first ground terminal 33 and GND after the input signal of the third input terminal 35 and the clock signal source drives the output signal of the third output terminal 31 to a high level, that is, to block the first ground terminal 33 from being grounded.

[0118] By the above Figure 7 As can be seen from the introduction, the third input terminal 35 of the latch circuit 3 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 3. Therefore, the third input terminal 35 and the output signal of the clock signal source can be used as the input signal of the third switch circuit 41. When the output signal of the third input terminal 35 and the clock signal source is used to drive the output signal of the third output terminal 31 of the latch circuit 3 to be high level, the third input terminal 35 and the output signal of the clock signal source are input to the third switch circuit 41, which can block the first ground terminal 33 from being grounded.

[0119] For example, when the third input terminal 35 and the clock signal source are switched to a high level, the output signal of the third output terminal 31 of the latch circuit 3 can be driven to a high level, and the switch between the first ground terminal 33 and GND in the third switch circuit 41 can be driven to be disconnected. Since the output of the third input terminal 35 of the latch circuit 3 is a high level, even if the first ground terminal 33 is blocked from being grounded, it will not affect the storage state of the latch circuit 3. And since the first ground terminal 33 is blocked from being grounded, the transistor in the latch circuit 3 connected in series between the first ground terminal 33 and the power supply will not have a direct current passing through even if it is not turned off in time, so the power consumption of the latch circuit 3 can be reduced.

[0120] In an example, the third switch circuit 41 can only block the first ground terminal 33 from being grounded when the output signal of the third input terminal 35 of the latch circuit 3 is switched to a high level by the signal outputted by the third input terminal 35 and the clock signal source. When the output signal of the third input terminal 35 or the clock signal source is changed, the third switch circuit 41 can restore the first ground terminal 33 to be grounded to ensure the normal operation of the latch circuit 3.

[0121] Continue to see Figure 7 , the fourth switch circuit 42 is connected to the second ground terminal 34, the fourth input terminal 36, the clock signal source and GND respectively. The fourth input terminal 36 and the clock signal source can be the control terminal of the fourth switch circuit 42, and the signal input by the fourth input terminal 36 and the clock signal source can control the conduction state between the second ground terminal 34 and GND. The fourth switch circuit 42 is used to block the second ground terminal 34 from being grounded after the input signal of the fourth input terminal 36 and the clock signal source drives the output signal of the fourth output terminal 32 to a high level.

[0122] By the above Figure 7 As can be seen from the introduction, the fourth input terminal 36 of the latch circuit 3 and the output signal of the clock signal source can drive the storage state switching of the latch circuit 3. Therefore, the fourth input terminal 36 and the output signal of the clock signal source can be used as the input signal of the fourth switch circuit 42. When the fourth input terminal 36 and the output signal of the clock signal source are used to drive the output signal of the fourth output terminal 32 of the latch circuit 3 to be high level, the fourth input terminal 36 and the output signal of the clock signal source are input to the fourth switch circuit 42, which can block the second ground terminal 34 from being grounded.

[0123] For example, when the fourth input terminal 36 and the clock signal source are switched to a high level, the output signal of the fourth output terminal 32 of the latch circuit 3 can be driven to a high level, and the switch between the second ground terminal 34 and GND in the third switch circuit 41 can be driven to be disconnected. Since the output of the fourth input terminal 36 of the latch circuit 3 is a high level, even if the second ground terminal 34 is blocked from being grounded, it will not affect the storage state of the latch circuit 3. And since the second ground terminal 34 is blocked from being grounded, the transistor in the latch circuit 3 connected in series between the second ground terminal 34 and the power supply will not have a direct current passing through it even if it is not turned off in time, so the power consumption of the latch circuit 3 can be reduced.

[0124] In one example, the fourth switch circuit 42 can block the second ground terminal 34 from being grounded only when the output signal of the fourth input terminal 36 and the signal output by the clock signal source drives the fourth input terminal 36 of the latch circuit 3 to switch to a high level. When the output signal of the fourth input terminal 36 or the clock signal source changes, the fourth switch circuit 42 can restore the first ground terminal 33 to be grounded to ensure the normal operation of the latch circuit 3.

[0125] Figure 8 is a circuit diagram of a latch provided in an embodiment of the present application. Figure 8 As shown, the third switch circuit 41 includes a twelfth transistor 411 and a thirteenth transistor 412. The gate of the twelfth transistor 411 is connected to the third input terminal 35, and the gate of the thirteenth transistor 412 is connected to the clock signal source. The first electrode of the twelfth transistor 411 is connected to the first ground terminal 33, the second electrode of the twelfth transistor 411 is grounded, the first electrode of the thirteenth transistor 412 is connected to the first ground terminal 33, and the second electrode of the thirteenth transistor 412 is grounded.

[0126] In implementation, the types of the twelfth transistor 411 and the thirteenth transistor 412 can be set according to the input signals of the third input terminal 35 and the clock signal source when the output signal of the third output terminal 33 driven by the third input terminal 35 and the clock signal source is high, so as to realize that when the output signal of the third output terminal 33 driven by the third input terminal 35 and the clock signal source is high, the twelfth transistor 411 and the thirteenth transistor 412 are both in the disconnected state. Among them, the type can be a P-type MOS tube or an N-type MOS tube. For example, when the output signal of the third output terminal 33 driven by the third input terminal 35 and the clock signal source is high, the third input terminal 35 and the clock signal source are both low, then the twelfth transistor 411 and the thirteenth transistor 412 can both be N-type MOS tubes.

[0127] Continue to see Figure 8 In one achievable manner, the fourth switch circuit 42 includes a fourteenth transistor 421 and a fifteenth transistor 422. The gate of the fourteenth transistor 421 is connected to the fourth input terminal 36, and the gate of the fifteenth transistor 422 is connected to the clock signal source. The first electrode of the fourteenth transistor 421 is connected to the second ground terminal 34, the second electrode of the fourteenth transistor 421 is grounded, the first electrode of the fifteenth transistor 422 is connected to the second ground terminal 34, and the second electrode of the fifteenth transistor 422 is grounded.

[0128] In implementation, the types of the fourteenth transistor 421 and the fifteenth transistor 422 can be set according to the input signals of the fourth input terminal 36 and the clock signal source when the output signal of the fourth output terminal 34 driven by the fourth input terminal 36 and the clock signal source is high, so that when the output signal of the fourth output terminal 34 driven by the fourth input terminal 36 and the clock signal source is high, the fourteenth transistor 421 and the fifteenth transistor 422 are both in a closed state. The type can be a P-type MOS tube or an N-type MOS tube. For example, when the output signal of the fourth output terminal 34 driven by the fourth input terminal 36 and the clock signal source is high, the fourth input terminal 36 and the clock signal source are both low, then the fourteenth transistor 421 and the fifteenth transistor 422 can both be N-type MOS tubes.

[0129] In an implementable manner, the latch circuit 3 includes a sixteenth transistor 37, a seventeenth transistor 38, and an eighteenth transistor 39. Figure 8 As shown, the gate of the sixteenth transistor 37 is connected to the third input terminal 35, the first electrode of the sixteenth transistor 37 is connected to the second electrode of the eighteenth transistor 39, and the second electrode of the sixteenth transistor 37 is connected to the third output terminal 31. The gate of the seventeenth transistor 38 is connected to the fourth input terminal 36, the first electrode of the seventeenth transistor 38 is connected to the second electrode of the eighteenth transistor 39, and the second electrode of the seventeenth transistor 38 is connected to the fourth output terminal 32. The gate of the eighteenth transistor 39 is connected to the clock signal source, and the first electrode of the eighteenth transistor 39 is grounded.

[0130] Continue to see Figure 8 The latch circuit 3 further includes a nineteenth transistor 310, a twentieth transistor 311, a twenty-first transistor 312, and a twenty-second transistor 313. The first electrode of the nineteenth transistor 310 is connected to the power supply, the second electrode of the nineteenth transistor 310 is connected to the third output terminal 31, and the gate of the nineteenth transistor 310 is connected to the fourth output terminal 32. The first electrode of the twentieth transistor 311 is connected to the power supply, the second electrode of the twentieth transistor 311 is connected to the fourth output terminal 32, and the gate of the twentieth transistor 311 is connected to the third output terminal 31. The first electrode of the twenty-first transistor 312 is connected to the third output terminal 31, the second electrode of the twenty-first transistor 312 is connected to the first ground terminal 33, and the gate of the twenty-first transistor 312 is connected to the fourth output terminal 42. The first electrode of the twenty-second transistor 313 is connected to the fourth output terminal 32, the second electrode of the twenty-second transistor 313 is connected to the second ground terminal 34, and the gate of the twenty-second transistor 313 is connected to the third output terminal 31.

[0131] Among them, the types of the sixteenth transistor 37, the seventeenth transistor 38, the eighteenth transistor 39, the nineteenth transistor 310 and the twentieth transistor 311 can be consistent, such as P-type MOS transistors, and the types of the twenty-first transistor 312 and the twenty-second transistor 313 can be consistent and different from the type of the sixteenth transistor 37, such as N-type MOS transistors. The types of the twelfth transistor 411, the thirteenth transistor 412, the fourteenth transistor 421 and the fifteenth transistor 422 can be consistent and different from the type of the eighteenth transistor 39, such as N-type MOS transistors.

[0132] Taking the sixteenth transistor 37 as a P-type MOS tube as an example, when the third input terminal 35 inputs a low level, the fourth input terminal 36 inputs a high level, and CLK outputs a low level, the sixteenth transistor 37, the eighteenth transistor 39, the nineteenth transistor 310, and the twenty-second transistor 313 in the latch circuit 3 are turned on, and only the fourteenth transistor 421 in the third switch circuit 41 in the blocking circuit 4 is turned on. The third output terminal 31 outputs a high level, and the fourth output terminal 32 outputs a low level. When the third input terminal 35 is switched to a high level, the fourth input terminal 36 is switched to a low level, and CLK outputs a low level, the seventeenth transistor 38, the twentieth transistor 311, and the twenty-first transistor 312 in the latch circuit 3 are turned on, and only the twelfth transistor 411 in the fourth switch circuit 42 in the blocking circuit 4 is turned on. The third output terminal 31 outputs a low level, and the fourth output terminal 32 outputs a high level. Among them, the low level of the fourth input terminal 36 acts on the gate of the seventeenth transistor 38 to turn on the seventeenth transistor 38, but due to the circuit control delay, the low level output by the third output terminal 31 acts on the gate of the twenty-second transistor 313 to block the conduction of the twenty-second transistor 313, which is later than the conduction of the seventeenth transistor 38. Therefore, after the latch circuit 3 switches the storage state, there is a momentary conduction between the seventeenth transistor 38 and the twenty-second transistor 313 and the ground terminal. However, the time when the low level of the clock signal source and the low level of the fourth input terminal 36 block the fourteenth transistor 421 and the fifteenth transistor 422 in the fourth switch circuit 42 is the same as the time when the high level of the fourth input terminal 36 turns on the seventeenth transistor 38. Therefore, even if the twenty-second transistor 313 fails to be disconnected in time, the fourth switch circuit 42 can block the second ground terminal 34 from being grounded, which can prevent the current from passing between the seventeenth transistor 38 and the twenty-second transistor 313 and the ground terminal, thereby reducing the power consumption of the latch circuit 3. In addition, the sixteenth transistor 37 is an N-type MOS tube, which is similar to the above-mentioned case where the sixteenth transistor 37 is a P-type MOS tube, and will not be described in detail in the embodiment of the present application.

[0133] Figures 9 to 12 They are schematic diagrams of the structures of exemplary timing circuits provided in the embodiments of the present application.

[0134] in, Figures 9 to 12 The timing circuit shown in FIG. 1 is composed of a first latch 51 and a second latch 52. Figure 9-12 As shown, the input terminals D and Dn of the first latch 51 are the input terminals of the sequential circuit, and the input signals are opposite. The output terminals Q and Qn of the first latch 51 are connected to the input terminals D and Dn of the second latch 52. The signals of the clock signal source (CLK) connected to the first latch 51 and the second latch 52 are opposite, that is, when the clock signal source connected to the first latch 51 is at a high level, the clock signal source connected to the second latch 52 is at a low level, and when the clock signal source connected to the first latch 51 is at a low level, the clock signal source connected to the second latch 52 is at a high level. The output terminal Q or Qn of the second latch 52 is the output terminal of the sequential circuit.

[0135] in, Figures 9 to 12 In the above embodiment, latch_n can be Figures 3 to 5 The latch shown, latch_p can be Figures 6 to 8 In the present application, latch_n or latch_p can be used to form a sequential circuit. Fig. 9 The sequential circuit shown in FIG. 1 may include a first latch 51 and a second latch 52 in the sequential circuit. Fig.10 In the sequential circuit shown in FIG. 1 , the first latch 51 and the second latch 52 in the sequential circuit may both be latch_p. Fig.11 In the sequential circuit shown in FIG. 1 , the first latch 51 in the sequential circuit may be latch_n, and the second latch 52 may be latch_p. Fig.12 In the sequential circuit shown, the first latch 51 in the sequential circuit can be latch_p, and the second latch 52 can be latch_n. Since the latch provided in the embodiment of the present application has lower power consumption than the traditional latch, the sequential circuit composed of the latch provided in the present application also has lower power consumption than the traditional sequential circuit.

[0136] The embodiment of the present application also provides a memory, which may be a memory with a peripheral circuit. Since the latch provided by the embodiment of the present application has lower power consumption than the traditional latch, the memory using the latch provided by the present application also has lower power consumption than the traditional memory.

[0137] Fig.13 1 is a schematic circuit diagram of an exemplary memory 1300 provided in an embodiment of the present application. The memory 1300 may include a memory cell array device 1301 and a peripheral circuit 1302 coupled to the memory cell array device 1301. The peripheral circuit 1302 is provided with at least one Figures 3 to 8 1302a, the memory cell array device 1301 may be a NAND flash memory cell array, wherein the memory cells 1306 are provided in the form of an array of NAND memory strings 1308, each NAND memory string 1308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 1308 includes a plurality of memory cells 1306 coupled in series and stacked vertically. Each memory cell 1306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 1306. Each memory cell 1306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0138] In some embodiments, each memory cell 1306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 1306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for an erased state.

[0139] like Fig.13As shown in , each NAND memory string 1308 may include a source select gate (SSG) 1310 at its source end and a drain select gate (DSG) 1312 at its drain end. The SSG 310 and the DSG 1312 may be configured to activate a selected NAND memory string 1308 (column of the array) during read and program processes. In some embodiments, the sources of the NAND memory strings 1308 in the same block 1304 are coupled by the same source line (SL) 1314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 1308 in the same block 1304 have an array common source (ACS). According to some embodiments, the DSG 1312 of each NAND memory string 308 is coupled to a corresponding bit line 1316, and data can be read from or written to the bit line 1316 via an output bus (not shown). In some embodiments, each NAND memory string 1308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having DSG 1312) or a deselect voltage (e.g., 0 V) ​​to a corresponding DSG 1312 via one or more DSG lines 1313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having SSG 1310) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG 1310 via one or more SSG lines 1315.

[0140] like Fig.13As shown in , the NAND memory string 1308 can be organized into a plurality of blocks 1304, each of which can have a common source line 1314 (e.g., coupled to ground). In some embodiments, each block 1304 is a basic data unit for an erase operation, i.e., all memory cells 1306 on the same block 1304 are erased at the same time. To erase the memory cells 1306 in a selected block 1304a, the source lines 1314 coupled to the selected block 1304a and the unselected blocks 1304b in the same plane as the selected block 1304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-block level, at a quarter-block level, or at a level with any suitable number of blocks or any suitable fraction of a block. The memory cells 1306 of adjacent NAND memory strings 1308 can be coupled by word lines 1318, which select which row of memory cells 1306 is affected by the read and programming process. In some embodiments, each word line 1318 is coupled to a page 1320 of memory cells 1306, which is the basic unit of data for the programming process. The size of a page 1320 in bits can be related to the number of NAND memory strings 1308 coupled by word lines 1318 in a block 1304. Each word line 1318 can include a plurality of control gates (gate electrodes) at each memory cell 1306 in a corresponding page 1320 and a gate line coupling the control gates.

[0141] Continue to refer Fig.13 , the peripheral circuit 1302 may be coupled to the memory cell array 1301 via the bit line 1316, the word line 1318, the source line 1314, the SSG line 1315, and the DSG line 1313. The peripheral circuit 1302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 1301 by applying a voltage signal and / or a current signal to each target memory cell 1306 and sensing a voltage signal and / or a current signal from each target memory cell 1306 via the bit line 1316, the word line 1318, the source line 1314, the SSG line 1315, and the DSG line 1313. The peripheral circuit 1302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Fig.14 Some exemplary peripheral circuits are shown, including page buffers / sense amplifiers 1404, column decoders / bit line drivers 1406, row decoders / word line drivers 1408, voltage generators 1410, control logic units 1412, registers 1414, interfaces 1416, and data buses 1418. Fig.14 The peripheral circuit shown may include at least one Figures 3 to 8The latch shown in FIG. 1 may also include at least one latch as shown in FIG. Figures 9 to 12 It should be understood that in some examples, it may also include Fig.14 Additional peripheral circuits not shown.

[0142] The page buffer / sense amplifier 1404 may be configured to read data from the memory cell array 1301 and program (write) data to the memory cell array 1301 according to a control signal from the control logic unit 1412. In one example, the page buffer / sense amplifier 1304 may store a page of programming data (write data) to be programmed into one page 1320 of the memory cell array 1301. In another example, the page buffer / sense amplifier 1404 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 1306 coupled to the selected word line 1318. In yet another example, the page buffer / sense amplifier 1404 may also sense a low-power signal from the bit line 1316 representing a data bit stored in the memory cell 1306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 1406 may be configured to be controlled by the control logic unit 1412, and select one or more NAND memory strings 1308 by applying a bit line voltage generated from the voltage generator 1410.

[0143] The row decoder / word line driver 1408 may be configured to be controlled by the control logic unit 1412 and select / deselect the block 1304 of the memory cell array 1301 and select / deselect the word line 1318 of the block 1304. The row decoder / word line driver 1408 may also be configured to drive the word line 1318 using the word line voltage generated from the voltage generator 1410. In some embodiments, the row decoder / word line driver 1408 may also select / deselect and drive the SSG line 1315 and the DSG line 1313. As described in detail below, the row decoder / word line driver 1408 is configured to perform an erase operation on the memory cell 1406 coupled to the (one or more) selected word lines 1418. The voltage generator 1410 may be configured to be controlled by the control logic unit 1412 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 1301.

[0144] The control logic unit 1412 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 1414 may be coupled to the control logic unit 1412 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 1416 may be coupled to the control logic unit 1412 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 1412, and to buffer status information received from the control logic unit 1412 and relay them to the host. The interface 1416 may also be coupled to the column decoder / bit line driver 1406 via the data bus 1418 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 1301 or relay or buffer data from the memory cell array 1301.

[0145] Fig.15 A block diagram of an exemplary system 1500 having memory according to some aspects of the present disclosure is shown. System 1500 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Fig.15 As shown in , the system 1500 may include a host 1508 and a storage system 1502, the storage system 1502 having one or more memories 1504 and a memory controller 1506. The host 1508 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 1508 may be configured to send data to the memory 1504 or receive data from the memory 1504.

[0146] The memory 1504 may be any memory disclosed in this application. For example, it may be the above Fig.14 Memory 1300 is shown. Memory 1504 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from driver transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows further size reduction of the driver transistors.

[0147] According to some embodiments, the memory controller 1506 is coupled to the memory 1504 and the host 1508 and is configured to control the memory 1504. The memory controller 1506 can manage data stored in the memory 1504 and communicate with the host 1508. In some embodiments, the memory controller 1506 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1506 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays. The memory controller 1506 can be configured to control the operation of the memory 1504, such as read, erase, and program processes. The memory controller 1506 may also be configured to manage various functions regarding data stored or to be stored in the memory 1504, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 1506 is also configured to process error correction code (ECC) regarding data read from or written to the memory 1504. The memory controller 1506 may also perform any other suitable functions, such as formatting the memory 1504. The memory controller 1506 may communicate with an external device (e.g., a host 1508) according to a specific communication protocol. For example, the memory controller 1506 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0148] The memory controller 1506 and the one or more memories 1504 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1502 can be implemented and packaged into different types of terminal electronic products. Fig.16In one example shown in FIG. 1 , the memory controller 1506 and the single memory 1504 may be integrated into a memory card 1602. The memory card 1602 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1602 may also include a processor that connects the memory card 1602 to a host (e.g., Fig.15 The memory card connector 1604 is coupled to the host 1508 in FIG. Fig.17 In another example shown in , the memory controller 1506 and the plurality of memories 1504 can be integrated into the SSD 306. The SSD 1706 can also include a processor that interfaces the SSD 1706 with a host (e.g., Fig.15 In some embodiments, the storage capacity and / or operating speed of SSD1706 is greater than the storage capacity and / or operating speed of memory card 1602.

[0149] The present application also provides a chip, which may include a processing circuit, such as a central processing unit (CPU), a graphics processing unit (GPU), or a microprocessor (MP). The latch used in the chip processing circuit may be the latch in the above embodiment. Figures 3 to 8 Any latch shown. Since the latch provided by the embodiment of the present application has lower power consumption than the traditional latch, the chip using the latch provided by the present application also has lower power consumption than the traditional chip.

[0150] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.

[0151] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A latch, characterized in that: The latch comprises a latch circuit (1) and a blocking circuit (2), wherein the latch circuit (1) has a first output terminal (11), a second output terminal (12), a first power terminal (13) and a second power terminal (14), a high level in an output signal of the first output terminal (11) is provided by the first power terminal (13), and a high level in an output signal of the second output terminal (12) is provided by the second power terminal (14); The blocking circuit (2) is used for: After the output signal of the first output terminal (11) changes from a high level to a low level, blocking conduction between the first power terminal (13) and the power supply; After the output signal of the second output terminal (12) changes from a high level to a low level, the conduction between the second power supply terminal (14) and the power supply is blocked.

2. The latch according to claim 1, characterized in that: The latch circuit (1) has a first input terminal (15) and a second input terminal (16), and the blocking circuit (2) includes a first switch circuit (21) and a second switch circuit (22); The first switch circuit (21) is respectively connected to the first power supply terminal (13), the first input terminal (15), the power supply and the clock signal source, and the second switch circuit (22) is respectively connected to the second power supply terminal (14), the second input terminal (16), the power supply and the clock signal source; The first switch circuit (21) is used to block conduction between the first power supply terminal (13) and the power supply after the input signal of the first input terminal (15) and the clock signal source drives the output signal of the first output terminal (11) to a low level; The second switch circuit (22) is used to block conduction between the second power supply terminal (14) and the power supply after the input signal of the second input terminal (16) and the clock signal source drives the output signal of the second output terminal (12) to a low level.

3. The latch according to claim 2, characterized in that: The first switch circuit (21) comprises a first transistor (211) and a second transistor (212); The gate of the first transistor (211) is connected to the first input terminal (15), and the gate of the second transistor (212) is connected to the clock signal source; The first electrode and the second electrode of the first transistor (211) are connected to the first power supply terminal (13) and the power supply respectively, and the first electrode and the second electrode of the second transistor (212) are connected to the first power supply terminal (13) and the power supply respectively.

4. The latch according to claim 3, characterized in that: The second switch circuit (22) comprises a third transistor (221) and a fourth transistor (222); The gate of the third transistor (221) is connected to the second input terminal (16), and the gate of the fourth transistor (222) is connected to the clock signal source; The first electrode and the second electrode of the third transistor (221) are connected to the second power supply terminal (14) and the power supply respectively, and the first electrode and the second electrode of the fourth transistor (222) are connected to the second power supply terminal (14) and the power supply respectively.

5. The latch according to any one of claims 2 to 4, characterized in that: The latch circuit (1) comprises a fifth transistor (17), a sixth transistor (18), and a seventh transistor (19); The gate of the fifth transistor (17) is connected to the first input terminal (15), the first electrode of the fifth transistor (17) is connected to the first output terminal (11), and the second electrode of the fifth transistor (17) is connected to the first electrode of the seventh transistor (19); The gate of the sixth transistor (18) is connected to the second input terminal (16), the first electrode of the sixth transistor (18) is connected to the second output terminal (12), and the second electrode of the sixth transistor (18) is connected to the first electrode of the seventh transistor (19); The gate of the seventh transistor (19) is connected to a clock signal source, and the second electrode of the seventh transistor (19) is grounded.

6. The latch according to claim 5, characterized in that: The latch circuit (1) further comprises an eighth transistor (110), a ninth transistor (111), a tenth transistor (112), and an eleventh transistor (113); A first electrode of the eighth transistor (110) is connected to the first power supply terminal (13), a second electrode of the eighth transistor (110) is connected to the first output terminal (11), and a gate of the eighth transistor (110) is connected to the second output terminal (12); A first electrode of the ninth transistor (111) is connected to the second power supply terminal (14), a second electrode of the ninth transistor (111) is connected to the second output terminal (12), and a gate of the ninth transistor (111) is connected to the first output terminal (11); A first electrode of the tenth transistor (112) is connected to the first output terminal (11), a second electrode of the tenth transistor (112) is grounded, and a gate of the tenth transistor (112) is connected to the second output terminal (12); A first electrode of the eleventh transistor (113) is connected to the second output terminal (12), a second electrode of the eleventh transistor (113) is grounded, and a gate of the eleventh transistor (113) is connected to the first output terminal (11).

7. The latch according to claim 5, characterized in that: The types of the first transistor (211), the second transistor (212), the third transistor (221) and the fourth transistor (222) are different from the type of the seventh transistor (19), wherein the types include P-type MOS transistors or N-type MOS transistors.

8. A latch, characterized in that: The latch comprises a latch circuit (3) and a blocking circuit (4), wherein the latch circuit (3) has a third output terminal (31), a fourth output terminal (32), a first ground terminal (33) and a second ground terminal (34), the third output terminal (31) is grounded via the first ground terminal (33), and the fourth output terminal (32) is grounded via the second ground terminal (34); The blocking circuit (4) is used for: After the output signal of the third output terminal (31) changes from a low level to a high level, blocking the first ground terminal (33) from being grounded; After the output signal of the fourth output terminal (32) changes from a low level to a high level, the second ground terminal (34) is blocked from being grounded.

9. The latch according to claim 8, characterized in that: The latch circuit (3) has a third input terminal (35) and a fourth input terminal (36), and the blocking circuit (4) includes a third switch circuit (41) and a fourth switch circuit (42); The third switch circuit (41) is respectively connected to the first ground terminal (33), the third input terminal (35) and the clock signal source, and the fourth switch circuit (42) is respectively connected to the second ground terminal (34), the fourth input terminal (36) and the clock signal source; The third switch circuit (41) is used to: after the input signal of the third input terminal (35) and the clock signal source drives the output signal of the third output terminal (31) to a high level, block the first ground terminal (33) from being grounded; The fourth switch circuit (42) is used to block the second grounding terminal (34) from being grounded after the input signal of the fourth input terminal (36) and the clock signal source drives the output signal of the fourth output terminal (32) to a high level.

10. The latch according to claim 9, characterized in that: The third switch circuit (41) comprises a twelfth transistor (411) and a thirteenth transistor (412); The gate of the twelfth transistor (411) is connected to the third input terminal (35), and the gate of the thirteenth transistor (412) is connected to the clock signal source; A first electrode of the twelfth transistor (411) is connected to the first ground terminal (33), a second electrode of the twelfth transistor (411) is grounded, a first electrode of the thirteenth transistor (412) is connected to the first ground terminal (33), and a second electrode of the thirteenth transistor (412) is grounded.

11. The latch according to claim 10, characterized in that: The fourth switch circuit (42) comprises a fourteenth transistor (421) and a fifteenth transistor (422); The gate of the fourteenth transistor (421) is connected to the fourth input terminal (36), and the gate of the fifteenth transistor (422) is connected to the clock signal source; A first electrode of the fourteenth transistor (421) is connected to the second ground terminal (34), a second electrode of the fourteenth transistor (421) is grounded, a first electrode of the fifteenth transistor (422) is connected to the second ground terminal (34), and a second electrode of the fifteenth transistor (422) is grounded.

12. The latch according to any one of claims 9 to 11, characterized in that: The latch circuit (3) comprises a sixteenth transistor (37), a seventeenth transistor (38), and an eighteenth transistor (39); The gate of the sixteenth transistor (37) is connected to the third input terminal (35), the first electrode of the sixteenth transistor (37) is connected to the second electrode of the eighteenth transistor (39), and the second electrode of the sixteenth transistor (37) is connected to the third output terminal (31); The gate of the seventeenth transistor (38) is connected to the fourth input terminal (36), the first electrode of the seventeenth transistor (38) is connected to the second electrode of the eighteenth transistor (39), and the second electrode of the seventeenth transistor (38) is connected to the fourth output terminal (32); The gate of the eighteenth transistor (39) is connected to a clock signal source, and the first electrode of the eighteenth transistor (39) is grounded.

13. The latch according to claim 12, characterized in that: The latch circuit (3) further comprises a nineteenth transistor (310), a twentieth transistor (311), a twenty-first transistor (312), and a twenty-second transistor (313); A first electrode of the nineteenth transistor (310) is connected to a power supply, a second electrode of the nineteenth transistor (310) is connected to the third output terminal (31), and a gate of the nineteenth transistor (310) is connected to the fourth output terminal (32); A first electrode of the twentieth transistor (311) is connected to a power supply, a second electrode of the twentieth transistor (311) is connected to the fourth output terminal (32), and a gate of the twentieth transistor (311) is connected to the third output terminal (31); A first electrode of the twenty-first transistor (312) is connected to the third output terminal (31), a second electrode of the twenty-first transistor (312) is connected to the first ground terminal (33), and a gate of the twenty-first transistor (312) is connected to the fourth output terminal (42); A first electrode of the twenty-second transistor (313) is connected to the fourth output terminal (32), a second electrode of the twenty-second transistor (313) is connected to the second ground terminal (34), and a gate of the twenty-second transistor (313) is connected to the third output terminal (31).

14. The latch according to claim 12, wherein: The types of the twelfth transistor (411), the thirteenth transistor (412), the fourteenth transistor (421) and the fifteenth transistor (422) are different from the type of the eighteenth transistor (39), wherein the types include P-type MOS transistors or N-type MOS transistors.

15. A memory, characterized in that: The memory comprises a peripheral circuit, wherein the peripheral circuit comprises at least one latch as claimed in any one of claims 1 to 14 above.

16. A sequential circuit, characterized in that: The sequential circuit comprises at least one latch as claimed in any one of claims 1 to 14 above.

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