Memory testing method and device, storage medium and electronic equipment

Abstract

The invention provides a memory testing method and device, a storage medium and electronic equipment, and relates to the field of semiconductors. In the method, a test program of a memory is obtained, and a first loading area in the memory and a relative address of each symbol reference in a test source code of the first test program and the first loading area are specified in the test program; and loading the test program to the first loading area, so that the test program executes a preset test item on the unused residual area in the memory. Therefore, the test program is limited in the first loading area, and the remaining area in the memory is regarded as a physical continuous space, so that the test program can conveniently test the memory.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular, to a memory testing method, device, storage medium and electronic device. Background Art

[0002] It should be understood that in the process of memory testing of memory products, the effect of continuous memory space testing is usually more significant. Therefore, in the related art, the test program can be run on a test device with independent memory and processor, and then the memory to be tested is accessed through a specific bus and its continuous storage interval is read and written. However, this method is not suitable for memory products that are directly integrated on circuit boards.

[0003] Therefore, for these memory products, it is necessary to load the test program into the memory, and then use the processor on the circuit board to run the test program from the memory to test the memory product. However, it is found in practice that in modern computing systems, most operating systems use virtual addresses to manage applications. Virtual addresses can provide an abstract memory model. By dividing the memory into several fixed-size blocks (such as pages or segments), when a process requests memory, the system allocates one or more such blocks to it, so that each process believes that it has a continuous and independent memory space. This not only improves memory utilization and multi-tasking capabilities, but also enhances the stability and security of the system, because memory isolation between processes prevents mutual interference, and the operating system can control memory access rights to protect key data and code from illegal access.

[0004] Therefore, in actual use, although the code can logically jump from the previous free memory area to the next free area for data storage, at the physical level, these free areas are often scattered rather than continuously distributed, and then it is difficult to obtain ideal test results during the testing of memory products. Summary of the invention

[0005] In order to overcome at least one of the deficiencies in the prior art, the present application provides a memory testing method, device, storage medium and electronic device, specifically including:

[0006] In a first aspect, the present invention provides a memory testing method, the method comprising:

[0007] Obtaining a first test program from memory, wherein the first test program specifies a first loading area in memory and a relative address between each symbol reference in a test source code of the first test program and the first loading area;

[0008] The first test program is loaded into the first loading area, so that the first test program executes preset test items on the remaining unused area in the memory.

[0009] In conjunction with the optional implementation manner of the first aspect, the obtaining the first test program of the memory includes:

[0010] Compiling the test source code into an intermediate compilation result, wherein each symbol reference in the test source code is initialized to a relative address with respect to the first loading area;

[0011] Obtaining a linker script of the intermediate compilation result, wherein the linker script specifies the first loading area;

[0012] The intermediate compilation result is linked into the first test program through the linker script.

[0013] In combination with the optional implementation manner of the first aspect, the test item includes testing a bit flip fault in the remaining area.

[0014] In conjunction with an optional implementation manner of the first aspect, before loading the first test program into the first loading area, the method further includes:

[0015] Loading the second test program in the memory into the cache space of the processor;

[0016] The second test program is run from the cache space to perform a BIST test on the first loading region.

[0017] In conjunction with an optional implementation manner of the first aspect, the first test program needs to be loaded into the first loading area through an operating system, and the method further includes:

[0018] The second test program is run from the cache space to perform a BIST test on a second loading area of ​​the operating system.

[0019] In conjunction with an optional implementation manner of the first aspect, before loading the first test program into the first loading area, the method further includes:

[0020] The BIST test result of the first loading area and the BIST test result of the second loading area are written into a temporary cache area preset in the memory, so that after the first test program is loaded into the first loading area, the BIST test result is obtained from the temporary cache area.

[0021] In combination with the optional implementation manner of the first aspect, loading the second test program in the memory into the cache space of the processor includes:

[0022] The second test program is loaded into the cache space of the processor through the boot loader.

[0023] In a second aspect, the present invention provides a memory testing device, the device comprising:

[0024] A program acquisition module, used for acquiring a first test program in a memory, wherein the first test program specifies a first loading area in the memory and a relative address of each symbol reference in a test source code of the first test program and the first loading area;

[0025] A program loading module is used to load the first test program into the first loading area so that the first test program executes preset test items on the remaining unused area in the memory.

[0026] In conjunction with the optional implementation manner of the second aspect, the program acquisition module is further specifically used for:

[0027] Compiling the test source code into an intermediate compilation result, wherein each symbol reference in the test source code is initialized to a relative address with respect to the first loading area;

[0028] Obtaining a linker script of the intermediate compilation result, wherein the linker script specifies the first loading area;

[0029] The intermediate compilation result is linked into the first test program through the linker script.

[0030] In combination with an optional implementation manner of the second aspect, the test item includes testing a bit flip fault in the remaining area.

[0031] In conjunction with an optional implementation manner of the second aspect, before loading the first test program into the first loading area, the program loading module is further used to:

[0032] Loading the second test program in the memory into the cache space of the processor;

[0033] The second test program is run from the cache space to perform a BIST test on the first loading region.

[0034] In conjunction with an optional implementation manner of the second aspect, the first test program needs to be loaded into the first loading area through an operating system, and the program loading module is further used to:

[0035] The second test program is run from the cache space to perform a BIST test on a second loading area of ​​the operating system.

[0036] In conjunction with an optional implementation manner of the second aspect, before loading the second test program into the first loading area, the program loading module is further used to:

[0037] The BIST test result of the first loading area and the BIST test result of the second loading area are written into a temporary cache area preset in the memory, so that after the first test program is loaded into the first loading area, the BIST test result is obtained from the temporary cache area.

[0038] In conjunction with the optional implementation manner of the second aspect, the program loading module is further specifically used for:

[0039] The second test program is loaded into the cache space of the processor through the boot loader.

[0040] In a third aspect, the present invention provides a storage medium storing a computer program, which, when executed by a processor, implements the memory testing method described in any one of the aforementioned implementations.

[0041] In a fourth aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the memory testing method described in any one of the aforementioned embodiments is implemented.

[0042] Compared with the prior art, this application has the following beneficial effects:

[0043] The present application provides a memory testing method, device, storage medium and electronic device. In the method, a first test program of the memory is obtained, wherein the first test program specifies a first loading area in the memory and the relative addresses of each symbol reference in the test source code of the first test program and the first loading area; the first test program is loaded into the first loading area so that the first test program executes preset test items on the remaining unused area in the memory. In this way, the first test program is restricted to the first loading area, and the remaining area in the memory is regarded as a physically continuous space, so that it is convenient for the first test program to test it. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0045] Figure 1 A flowchart of a memory testing method provided in an embodiment of the present application;

[0046] Figure 2 A schematic diagram of the remaining area provided for an embodiment of the present application;

[0047] Figure 3 A schematic diagram of a cache space provided in an embodiment of the present application;

[0048] Figure 4 A schematic diagram of the structure of a memory testing device provided in an embodiment of the present application;

[0049] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0052] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0053] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. In addition, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0054] Based on the above statement, as introduced in the background technology, although the code can logically jump from the previous free memory area to the next free area for data storage, due to the virtual address, these free areas are often scattered rather than continuously distributed at the physical level, and then it is difficult to obtain ideal test results during the testing of memory products.

[0055] It should be noted that the memory product in this embodiment can be, but is not limited to, LPDDR (Low Power Double Data Rate), DDR SDRAM (Double Data Rate Synchronous Dynamic Random-Access Memory), SDRAM (Synchronous Dynamic Random-Access Memory), etc.

[0056] Based on the discovery of the above technical problems, the inventors have proposed the following technical solutions to solve or improve the above problems through creative work. It should be noted that the defects in the solutions in the above prior art are the results obtained by the inventors after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of the present application for the above problems below should all be the contributions made by the inventors to the present application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0057] In view of this, the present embodiment provides a memory testing method. In the method, a first test program of the memory is obtained, wherein the first test program specifies a first loading area in the memory and the relative addresses of each symbol reference in the test source code and the first loading area; the first test program is loaded into the first loading area so that the first test program executes preset test items on the remaining unused area in the memory. In this way, the first test program is limited to the first loading area, and the remaining area in the memory is regarded as a physically continuous space, so that it is convenient for the first test program to test it.

[0058] The electronic device implementing the method may be, but is not limited to, a mobile terminal, a tablet computer, a laptop computer, a desktop computer, etc. The mobile terminal may include a smart home device, a wearable device, a smart mobile device, a virtual reality device, or an augmented reality device, etc.

[0059] To make the solution provided by this embodiment clearer, Figure 1Each step of the method is described in detail. However, it should be understood that the operations of the flowchart may not be implemented in order, and steps without logical contextual relationships may be reversed in order or implemented simultaneously. In addition, those skilled in the art may add one or more other operations to the flowchart, or remove one or more operations from the flowchart under the guidance of the content of this application. Figure 1 As shown, the method includes:

[0060] S1, obtain the first test program in memory.

[0061] The first test program specifies the first loading area in the memory and the relative addresses of each symbol reference in the test source code of the first test program and the first loading area. In this embodiment, the test source code can be compiled into an intermediate compilation result, wherein each symbol reference in the test source code is initialized to a relative address with the first loading area; a linker script of the intermediate compilation result is obtained, wherein the linker script specifies the first loading area; and the intermediate compilation result is linked into the first test program through the linker script.

[0062] It should be understood that the above-mentioned symbolic references refer to variables, functions, constants, etc. in the source code, and the corresponding first test program is loaded into the memory and has accessible addresses. For example, the access address of variables, the access address of functions, and the access address of constants. The intermediate compilation result refers to a series of files generated after the test source code is compiled. These files contain the intermediate or final products of the compiler converting the source code into machine language. For example, for languages ​​such as C / C++, "xxx.o" files may be generated during the source code compilation process. These files contain the machine code of each function or class member, as well as related information such as the location of variables, call stack, etc. In addition, the intermediate files also refer to the dynamic link library (DLL or shared library) files needed during the operation of the first test program.

[0063] In addition, it should be understood that specifying the physical address of program loading when compiling a program is usually not a standard practice, because modern operating systems usually use virtual memory management, and the physical memory address of the program is determined by the operating system's memory management unit (MMU) and page table management. In order to prevent the operating system from arbitrarily loading the first test program of the test source code, this embodiment limits the first test program to a preset first loading area through a linker script, so that the remaining area in the memory is regarded as a physically continuous area.

[0064] The first test program generated by compiling the source code is usually called an ELF (Executable and Linkable Format) file, and its structure includes an ELF header, a program header table, a section header table, and a series of sections. These components work together to enable different parts of code and data to be efficiently loaded and executed at runtime. In the ELF file system, through a flexible segment table design, different parts of code and data are allowed to be associated with each other in a dynamic linking manner in memory. For example, when using the GCC compiler, by creating a linker script, the developer can accurately specify the load address of a specific segment such as ".text" (code segment). This not only enhances the flexibility of the program, but also facilitates deployment and execution in different system environments.

[0065] Here is an example of a simple linker script "linkscript.ld" that specifies that the load address of the ".text" segment is 0x10000:

[0066] SECTIONS

[0067] {

[0068] .=0x10000; / / Set the initial position

[0069] .text:{*(.text)} / / Load all content under the .text tag here

[0070] / * Other segments can be defined here, such as data segments, uninitialized data segments, etc. * /

[0071] }

[0072] In the actual compilation process, the "-T" option is passed through the command line to specify the above linker script to generate the final binary file. For example:

[0073] gcc -T linkscript.ld -o output.elf source.c

[0074] This process converts the source code into a first test program that can be loaded into a specific memory area. Since each symbol reference in the test source code is initialized as a relative address to the first loading area, the loading position of each symbol reference in the first loading area can be determined.

[0075] Based on the above implementation, the first test program of the test source code is introduced. Figure 1 , the method provided in this embodiment also includes:

[0076] S2, loading the first test program into the first loading area, so that the first test program executes preset test items on the remaining unused area in the memory.

[0077] In this embodiment, when the first test program is run in a logical manner, the remaining area refers to the space in the memory excluding the first loading area. When the first test program is a program dependent on the operating system, the remaining area refers to the space in the memory excluding the first loading area and the second loading area occupied by the operating system.

[0078] For example, Figure 2 As shown in the figure, the first loading area and the second loading area are shown. The remaining area excluding the first loading area and the second loading area can be regarded as a physically continuous space. This facilitates the first test program to test this remaining area. In this way, the first test program is limited to the first loading area, and the remaining area in the memory is regarded as a physically continuous space, which facilitates the first test program to test it.

[0079] The above test items include testing bit flip faults in the remaining area. Bit flip faults refer to the unexpected change of the state (0 or 1) of a storage bit due to various reasons during computer memory or data transmission, for example, from 1 to 0, or from 0 to 1. This kind of fault may have unpredictable effects on the calculation results, especially in systems with high reliability and security requirements.

[0080] In the case of a bit flip fault, when the tested area is not a continuous memory area, the first test program is required to distinguish which are the tested areas and which are the areas occupied by the tested program. Therefore, a continuous memory area means that the physical layout of the memory is consistent, and this consistency allows the first test program to access and manage memory resources more efficiently. In a continuous space, adjacent memory cells can be accessed by simple address addition without additional lookup or addressing operations.

[0081] Furthermore, in a continuous memory space, data integrity and consistency can be verified through simpler data copying and comparison operations. When testing bit flips between adjacent memory cells, the contents of these cells can be directly compared without the need for additional logic to handle differences in memory layout. This makes detecting and locating faults more direct and faster.

[0082] In addition, in discontinuous memory spaces, boundary effects may interfere with test results. For example, when a program runs between memory blocks with different intervals, the execution environment of the program may be different, which may lead to abnormal behavior or hidden errors at the boundary. Continuous memory space can reduce the impact of such boundary effects and make test results more accurate and consistent.

[0083] In practice, it is found that the first test program itself needs to occupy the first loading area, which means that the first test program cannot test the first loading area. In this regard, before loading the first test program into the first loading area, this embodiment loads the second test program in the memory into the cache space of the processor; runs the second test program from the cache space to perform a BIST (Built-In Self-Test) test on the first loading area.

[0084] like Figure 3 As shown, a cache space is also provided between the processor core (CPU Core) of the processor and the memory, which is used to cache part of the data in the memory, thereby improving the processing efficiency of the processor core. In this embodiment, before loading the first test program into the first loading area, the second test program is first loaded into the cache space of the processor, so that the first loading area is in an idle state, and then the BIST test is performed on the first loading area.

[0085] Among them, BIST testing refers to detecting and diagnosing potential defects or faults of a circuit through an internally generated test sequence, thereby effectively verifying the functionality and integrity of each part of the integrated circuit without the need for additional external test equipment. In this embodiment, when performing BIST testing on the memory, the automatically generated test sequence is executed on the memory to detect various fault types, such as single-bit errors, multi-bit errors, and bit flips.

[0086] In addition, when the first test program is not run in a bare metal mode, the first test program needs to be loaded into the first loading area through the operating system. This means that the first test program cannot test the second loading area of ​​the operating system either. Therefore, this embodiment also runs the second test program from the cache space to perform a BIST test on the second loading area of ​​the operating system.

[0087] It can be understood that this embodiment needs to first load the operating system into the second loading area, and then load the first test program into the first test interval through the operating system. The loading of the operating system needs to rely on the boot loader, so this embodiment can load the second test program into the cache space of the processor through the boot loader. The boot loader is also known as Bootloader. Its main function is to initialize hardware devices and load the operating system kernel into the memory, and then transfer control to the operating system to start the entire system. Windows systems usually use UEFI (Unified Extensible Firmware Interface) as the boot loader, Linux systems usually use GRUB (Grand Unified Bootloader) as the boot loader, and embedded systems use U-Boot as the boot loader.

[0088] However, it should be understood that the main function of the boot loader is to initialize the hardware device. Therefore, before the hardware device is initialized, the second test program runs slowly due to the limitations of the processor frequency and the size of the cache space, and is not suitable for testing the entire memory. Therefore, this embodiment only performs BIST testing on the first loading area of ​​the first test program and the second loading area of ​​the operating system, and other areas are tested by the first test program running in the memory after the operating system is running.

[0089] In practice, it is also found that after the operating system obtains control of the processor's cache space, the data in the cache space will be overwritten. Therefore, if the BIST test results are stored in the cache space, data loss will occur. In this regard, this embodiment writes the BIST test results of the first loading area and the BIST test results of the second loading area into a temporary cache area preset in the memory, so that after the first test program is loaded into the first loading area, the BIST test results are obtained from the temporary cache area.

[0090] The temporary cache area is located outside the first loading area and the second loading area of ​​the memory, so that after the first test program is run, the BIST test result can be read from the memory.

[0091] Based on the same inventive concept as the memory testing method provided in this embodiment, this embodiment also provides a memory testing device. The device includes at least one software function module that can be stored in a memory or fixed in an electronic device in the form of software. The processor in the electronic device is used to execute the executable module stored in the memory. For example, the software function module and computer program included in the device. Please refer to Figure 4 , functionally speaking, the device may include:

[0092] A program acquisition module 11 is used to acquire a first test program of a test source code, wherein the first test program specifies a first loading area in a memory and a relative address of each symbol reference in the test source code of the first test program and the first loading area;

[0093] The program loading module 12 is used to load the first test program into the first loading area, so that the first test program executes preset test items on the remaining unused area in the memory.

[0094] In this embodiment, the program acquisition module 11 is used to implement Figure 1 In step S1, the program loading module 12 is used to implement Figure 1 For the detailed description of the above modules, please refer to the specific implementation of the corresponding steps. Of course, in view of the same inventive concept as the memory testing method provided in this embodiment, the memory testing device can also implement other steps or sub-steps of the method through the above modules or other modules, which will not be described in detail in this embodiment.

[0095] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0096] It should also be understood that if the above implementation is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0097] Therefore, this embodiment also provides a storage medium, which is a computer-readable storage medium. The storage medium stores a computer program, and when the computer program is executed by the processor, the memory testing method provided in this embodiment is implemented. Among them, the storage medium can be a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, etc., which can store program codes.

[0098] This embodiment provides an electronic device for implementing a memory testing method. Figure 4As shown, the electronic device may include a processor 22 and a memory 21. In addition, the memory 21 stores a computer program, and the processor implements the memory test method provided in this embodiment by reading and executing the computer program corresponding to the above implementation in the memory 21.

[0099] Continue to see Figure 5 The electronic device further includes a communication unit 23. The memory 21, the processor 22 and the communication unit 23 are electrically connected to each other directly or indirectly through a system bus 24 to achieve data transmission or interaction.

[0100] The memory 21 may be an information recording device based on any electronic, magnetic, optical or other physical principle, used to record execution instructions, data, etc. In some embodiments, the memory 21 may be, but is not limited to, a volatile memory, a non-volatile memory, a storage drive, etc.

[0101] In some embodiments, the volatile memory may be a random access memory (RAM); in some embodiments, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), a flash memory, etc.; in some embodiments, the storage drive may be a disk drive, a solid-state drive, any type of storage disk (such as a CD, a DVD, etc.), or a similar storage medium, or a combination thereof, etc.

[0102] The communication unit 23 is used to send and receive data through a network. In some embodiments, the network may include a wired network, a wireless network, a fiber optic network, a telecommunication network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth network, a ZigBee network, or a near field communication (NFC) network, or any combination thereof. In some embodiments, the network may include one or more network access points. For example, the network may include a wired or wireless network access point, such as a base station and / or a network switching node, through which one or more components of the service request processing system may be connected to the network to exchange data and / or information.

[0103] The processor 22 may be an integrated circuit chip having a signal processing capability, and the processor may include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor may include a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction set processor (ASIP), a graphics processing unit (GPU), a physical processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0104] Understandably, Figure 5The structure shown is for illustration only. The electronic device may also have Figure 5 More or fewer components than shown, or with Figure 5 Different configurations are shown. Figure 5 The components shown may be implemented in hardware, software or a combination thereof.

[0105] It should be understood that the apparatus and method disclosed in the above-mentioned embodiments can also be implemented in other ways. The apparatus embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the apparatus, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0106] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory testing method, characterized in that: The method comprises: Obtaining a first test program from memory, wherein the first test program specifies a first loading area in memory and a relative address between each symbol reference in a test source code of the first test program and the first loading area; The first test program is loaded into the first loading area, so that the first test program executes preset test items on the remaining unused area in the memory.

2. The memory testing method according to claim 1, characterized in that: The first test program of obtaining the memory includes: Compiling the test source code into an intermediate compilation result, wherein each symbol reference in the test source code is initialized to a relative address with respect to the first loading area; Obtaining a linker script of the intermediate compilation result, wherein the linker script specifies the first loading area; The intermediate compilation result is linked into the first test program through the linker script.

3. The memory testing method according to claim 1, characterized in that: The test items include testing a bit flip fault in the remaining area.

4. The memory testing method according to claim 1, characterized in that: Before loading the first test program into the first loading area, the method further includes: Loading the second test program in the memory into the cache space of the processor; The second test program is run from the cache space to perform a BIST test on the first loading region.

5. The memory testing method according to claim 4, characterized in that: The first test program needs to be loaded into the first loading area through the operating system, and the method further includes: The second test program is run from the cache space to perform a BIST test on a second loading area of ​​the operating system.

6. The memory testing method according to claim 5, characterized in that: Before loading the first test program into the first loading area, the method further includes: The BIST test result of the first loading area and the BIST test result of the second loading area are written into a temporary cache area preset in the memory, so that after the first test program is loaded into the first loading area, the BIST test result is obtained from the temporary cache area.

7. The memory testing method according to claim 4, characterized in that: Loading the second test program in the memory into the cache space of the processor comprises: The second test program is loaded into the cache space of the processor through the boot loader.

8. A memory testing device, characterized in that: The device comprises: A program acquisition module, used for acquiring a first test program of a test source code, wherein the first test program specifies a first loading area in a memory and a relative address of each symbol reference in the test source code of the first test program and the first loading area; A program loading module is used to load the first test program into the first loading area so that the first test program executes preset test items on the remaining unused area in the memory.

9. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the memory testing method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, the memory testing method according to any one of claims 1 to 7 is implemented.

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