Manufacturing method of IGBT (Insulated Gate Bipolar Translator) device

Abstract

The invention belongs to the technical field of IGBT (Insulated Gate Bipolar Translator) devices, and particularly discloses a manufacturing method of an IGBT device, which comprises the following steps of: forming a plurality of first grooves in an n-type semiconductor layer; forming a channel injection region on one side of the first groove in the type semiconductor layer through inclined ion injection, and forming a p-type body region through two times of inclined ion injection; forming an n-type charge storage region through vertical ion implantation; forming an n-type source region through inclined ion implantation; forming a first grid electrode and a second groove through a self-alignment process; and forming a second grid electrode in the second groove. According to the invention, the photoetching process times in the manufacturing process of the IGBT device can be reduced, and the manufacturing cost of the IGBT device is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of IGBT devices, and in particular relates to a method for manufacturing an IGBT device. Background Art

[0002] An insulated gate bipolar transistor (IGBT) is a device composed of a MOS transistor and a bipolar transistor. Its input is a MOS transistor and its output is a PNP transistor. It combines the advantages of these two devices, and has the advantages of low driving power and fast switching speed of MOS transistors, as well as low saturation voltage drop and large capacity of bipolar transistors. It has been increasingly widely used in modern power electronics technology, especially in the application of high-frequency and medium-power transistors. In the manufacturing process of IGBT devices in the prior art, a multi-step photolithography process is required, and the high cost of the photolithography process makes it difficult to reduce the manufacturing cost of IGBT devices. Summary of the invention

[0003] In view of this, an object of the present invention is to provide a method for manufacturing an IGBT device to reduce the manufacturing cost of the IGBT device.

[0004] In order to achieve the above-mentioned object of the present invention, the present invention provides a method for manufacturing an IGBT device, comprising:

[0005] forming a first insulating layer on the provided n-type semiconductor layer, etching the first insulating layer and the n-type semiconductor layer, and forming a plurality of first trenches in the n-type semiconductor layer;

[0006] Performing an inclined ion implantation toward one side of the first trench to form a channel implantation region located at one side of the first trench in the n-type semiconductor layer;

[0007] Performing inclined ion implantation on both sides of the first trench to form p-type body regions located on both sides of the first trench in the n-type semiconductor layer;

[0008] Performing vertical ion implantation to form an n-type charge storage region located below the first trench in the n-type semiconductor layer;

[0009] forming a gate dielectric layer on the surface of the first trench, and then forming a first conductive layer and etching back, wherein the upper surface of the remaining first conductive layer after etching back is lower than the upper surface of the n-type semiconductor layer;

[0010] Performing inclined ion implantation on both sides of the first trench to form an n-type source region in the p-type body region;

[0011] Forming a second insulating layer and etching back, forming sidewalls on the first conductive layer on both sides of the first trench respectively, etching the first conductive layer using the first insulating layer and the sidewalls as masks, and forming first gates on both sides of the first trench respectively on the remaining first conductive layer after etching;

[0012] Using the first insulating layer and the sidewall as masks, etching the gate dielectric layer and the n-type semiconductor layer to form a second trench in the n-type semiconductor layer;

[0013] A third insulating layer is formed to cover the formed structure, and then a second conductive layer is formed and etched back. The remaining second conductive layer after etching forms a second gate in the second trench.

[0014] Optionally, the bottom of the second trench is lower than the bottom of the n-type charge storage region.

[0015] Optionally, the first insulating layer is silicon oxide, silicon nitride, or a mixed layer of silicon oxide and silicon nitride.

[0016] Optionally, the second insulating layer is silicon oxide or silicon nitride.

[0017] Optionally, the third insulating layer is silicon oxide.

[0018] Optionally, an interlayer insulating layer, a source metal and a gate metal are formed on the surface of the n-type semiconductor layer.

[0019] Optionally, the method for manufacturing the IGBT device further includes: forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer.

[0020] Optionally, the method for manufacturing the IGBT device further includes: forming a collector metal on the bottom surface of the n-type semiconductor layer.

[0021] Optionally, the second gate extends upward into the first trench.

[0022] Optionally, the doping type of the channel injection region is n-type or p-type.

[0023] The manufacturing method of the IGBT device provided by the present invention forms the first groove through a single photolithography process, and no photolithography process is required during the manufacturing process of the channel injection region, the p-type body region, the n-type source region, the first gate, the second groove and the second gate, thereby reducing the number of photolithography processes in the manufacturing process of the IGBT device and effectively reducing the manufacturing cost of the IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solution of the exemplary embodiment of the present invention, the following briefly introduces the drawings required for describing the embodiment.

[0025] Figures 1 to 9 It is a schematic cross-sectional structure diagram of the main structures in the manufacturing process of an embodiment of the method for manufacturing an IGBT device provided by the present invention. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be described in detail below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. It should be understood that the terms such as "having", "including" and "comprising" used in the present invention do not indicate the existence or addition of one or more other elements or their combinations. At the same time, in order to clearly illustrate the specific implementation methods of the present invention, the schematic diagrams listed in the drawings of the specification magnify the thickness of the layers and regions described in the present invention, and the listed graphic sizes do not represent the actual sizes.

[0027] Figures 1 to 9 It is a schematic cross-sectional structure diagram of the main structures in the manufacturing process of an embodiment of the method for manufacturing an IGBT device provided by the present invention.

[0028] First, if Figure 1 As shown, a first insulating layer 41 is formed on the provided n-type semiconductor layer 20, and the first insulating layer 41 is generally a mixed layer of silicon oxide, silicon nitride, or silicon oxide and silicon nitride. The position of the first groove is defined by a photolithography process, and then the first insulating layer 41 and the n-type semiconductor layer 20 are etched to form a plurality of first grooves 51 arranged in sequence in the n-type semiconductor layer 20. The material of the n-type semiconductor layer 20 is generally silicon. The number of the first grooves 51 is determined by the specific device design, and only two first grooves 51 are shown exemplarily in the embodiment of the present invention.

[0029] Next, if Figure 2As shown, ion implantation is performed obliquely toward one side of the first trench 51, and a channel implantation region 42 located at one side of the first trench 51 is formed in the n-type semiconductor layer 20. The doping type of the channel implantation region 42 can be n-type or p-type. The channel implantation region 42 is used to adjust the doping concentration of the channel region in the p-type body region formed subsequently. When the channel implantation region 42 is n-type doped, the p-type ion doping concentration of the channel region in the p-type body region formed subsequently can be reduced, thereby reducing the threshold voltage for opening the channel region; when the channel implantation region 42 is p-type doped, the doping concentration of the channel region in the p-type body region formed subsequently can be increased, thereby increasing the threshold voltage for opening the channel region. Forming the channel implantation region 42 only on one side of the first trench 51 can make the p-type doping concentrations of the channel regions at the two side walls of the first trench 51 unequal, that is, the IGBT device has different threshold voltages Vth, thereby reducing the turn-off loss of the IGBT device.

[0030] Next, if Figure 3 As shown, inclined ion implantation is performed on both sides of the first trench 51 to form p-type body regions 21 located on both sides of the first trench 51 in the n-type semiconductor layer 20 .

[0031] Next, if Figure 4 As shown, vertical ion implantation is performed to form an n-type charge storage region 22 located below the first trench 51 in the n-type semiconductor layer 20. Optionally, according to the actual manufacturing process, after the n-type charge storage region 22 is diffused, the n-type charge storage regions 22 located below the adjacent first trenches 51 can be connected together, and this structure is no longer shown in the embodiment of the present invention.

[0032] Next, if Figure 5 As shown, a gate dielectric layer 23 is formed on the surface of the first trench, and the gate dielectric layer 23 is usually formed by a thermal oxidation process. Then, a first conductive layer 24 is formed and etched back. After the etching back, the upper surface of the remaining first conductive layer 24 is lower than the upper surface of the n-type semiconductor layer 20, which can make it easier to form the subsequent n-type source region.

[0033] Next, if Figure 6 As shown, inclined ion implantation is performed on both sides of the first trench to form an n-type source region 25 in the p-type body region 21. Therefore, the formation of the n-type source region 25 does not require a separate photolithography process.

[0034] Next, if Figure 7As shown, a second insulating layer is formed and etched back, and sidewalls 26 located on the first conductive layer are formed on both sides of the first trench, and then the first conductive layer is etched using the first insulating layer 41 and the sidewalls 26 as masks, and the remaining first conductive layer after etching forms first gates 27 on both sides of the first trench. The first gate 27 is formed by a self-alignment process, and a separate photolithography process is not required. The second insulating layer can be silicon oxide or silicon nitride.

[0035] Next, if Figure 8 As shown, the gate dielectric layer and the n-type semiconductor layer 20 are etched using the first insulating layer 41 and the sidewall 26 as masks to form a second trench 52 in the n-type semiconductor layer 20. The bottom of the optional second trench 52 can be lower than the bottom of the n-type charge storage region 22, so that the n-type charge storage region 22 is located between adjacent second trenches 52.

[0036] Next, if Fig. 9 As shown, a third insulating layer 28 is formed to cover the formed structure, and then a second conductive layer is formed and etched back. The remaining second conductive layer after etching forms a second gate 29 in the second trench. Optionally, the second gate 29 extends upward into the first trench. The third insulating layer 28 is usually silicon oxide.

[0037] Finally, an IGBT device can be formed through conventional processes, including, for example: forming an interlayer insulating layer, a source metal, and a gate metal on the surface of the n-type semiconductor layer; forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer; and forming a collector metal on the bottom surface of the n-type semiconductor layer. These processes are conventional manufacturing processes in the industry and will not be described in detail in the embodiments of the present invention.

[0038] The above specific implementation methods and examples are specific supports for the technical ideas of the present invention, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or equivalent modifications made on the basis of this technical solution in accordance with the technical ideas proposed by the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing an IGBT device, characterized in that: include: forming a first insulating layer on the provided n-type semiconductor layer, etching the first insulating layer and the n-type semiconductor layer, and forming a plurality of first trenches in the n-type semiconductor layer; Performing an inclined ion implantation toward one side of the first trench to form a channel implantation region located at one side of the first trench in the n-type semiconductor layer; Performing inclined ion implantation on both sides of the first trench to form p-type body regions located on both sides of the first trench in the n-type semiconductor layer; Performing vertical ion implantation to form an n-type charge storage region located below the first trench in the n-type semiconductor layer; forming a gate dielectric layer on the surface of the first trench, and then forming a first conductive layer and etching back, wherein the upper surface of the remaining first conductive layer after etching back is lower than the upper surface of the n-type semiconductor layer; Performing inclined ion implantation on both sides of the first trench to form an n-type source region in the p-type body region; Forming a second insulating layer and etching back, forming sidewalls on the first conductive layer on both sides of the first trench respectively, etching the first conductive layer using the first insulating layer and the sidewalls as masks, and forming first gates on both sides of the first trench respectively on the remaining first conductive layer after etching; Using the first insulating layer and the sidewall as masks, etching the gate dielectric layer and the n-type semiconductor layer to form a second trench in the n-type semiconductor layer; A third insulating layer is formed to cover the formed structure, and then a second conductive layer is formed and etched back. The remaining second conductive layer after etching forms a second gate in the second trench.

2. The method for manufacturing an IGBT device according to claim 1, wherein: The bottom of the second trench is lower than the bottom of the n-type charge storage region.

3. The method for manufacturing an IGBT device according to claim 1, wherein: The first insulating layer is silicon oxide, silicon nitride, or a mixed layer of silicon oxide and silicon nitride.

4. The method for manufacturing an IGBT device according to claim 1, wherein: The second insulating layer is silicon oxide or silicon nitride.

5. The method for manufacturing an IGBT device according to claim 1, wherein: The third insulating layer is silicon oxide.

6. The method for manufacturing an IGBT device according to claim 1, wherein: Also includes: An interlayer insulating layer, a source metal and a gate metal are formed on the surface of the n-type semiconductor layer.

7. The method for manufacturing an IGBT device according to claim 1, wherein: Also includes: An n-type field stop region and a p-type collector region are formed at the bottom of the n-type semiconductor layer.

8. The method for manufacturing an IGBT device according to claim 7, wherein: Also includes: A collector metal is formed on the bottom surface of the n-type semiconductor layer.

9. The method for manufacturing an IGBT device according to claim 1, wherein: The second gate extends upward into the first trench.

10. The method for manufacturing an IGBT device according to claim 1, wherein: The doping type of the channel implantation region is n-type or p-type.

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